Abstract: An electrode passivation layer of a semiconductor device and a method for forming the same having improved corrosion-resistance and oxidation-resistance are disclosed, the electrode passivation film including a semiconductor substrate; a conductive layer pattern formed on the semiconductor substrate; and an amorphous passivation film formed on the conductive layer pattern.

Abstract: The present invention provides a method of forming a film, having the step of allowing a first chemical substance to be adsorbed on a surface of a silicon substrate by a gaseous phase method, and the step of introducing a gas containing a second chemical substance onto the substrate surface having the first chemical substance adsorbed thereon for forming a silicon compound layer on the silicon substrate, the silicon compound layer consisting essentially of a silicon compound formed by a reaction between the first chemical substance adsorbed on the substrate surface and the second chemical substance.

Abstract: An apparatus and method for forming thin film aerogels on semiconductor substrates is disclosed. It has been found that in order to produce defect-free nanoporous dielectrics with a controllable high porosity, it is preferable to substantially limit evaporation and condensation of pore fluid in the wet gel thin film, e.g. during gelation, during aging, and at other points prior to obtaining a dried gel. The present invention simplifies the atmospheric control needed to prevent evaporation and condensation by restricting the atmosphere in contact with the wet gel thin film to an extremely small volume. In one embodiment, a substrate 26 is held between a substrate holder 36 and a parallel plate 22, such that a substantially sealed chamber 32 exists between substrate surface 28 and chamber surface 30. Preferably, the average clearance between surfaces 28 and 30 is less than 5 mm, or more preferably, less than 1 mm. Temperature control means 34 may optionally be used to control the temperature in chamber 32.

Abstract: A ceramic layer, in particular having ferroelectric, dielectric or superconducting properties, uses compounds with a simple structure as precursors and only methanoic acid, acetic acid or propionic acid and, where appropriate, water as solvent.

Abstract: A method and apparatus for reducing surface sensitivity of a TEOS/O.sub.3 SACVD silicon oxide layer, formed over a substrate, that deposits a ramp layer while ramping pressure to a target deposition pressure and deposits an SACVD layer over the ramp layer. In one embodiment, the flow of ozone is stopped during the pressure ramp-up to control the thickness of the ramp layer.

Abstract: A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.

Abstract: A process for forming low k silicon oxide dielectric material having a dielectric constant no greater than 3.0, while suppressing pressure spikes during the formation of the low k silicon oxide dielectric material comprises reacting an organo-silane and hydrogen peroxide in a reactor chamber containing a silicon substrate while maintaining an electrical bias on the substrate. In a preferred embodiment the reactants are flowed into the reactor at a reactant flow ratio of organo-silane reactant to hydrogen peroxide reactant of not more than 10.6 sccm of organo-silane reactant per 0.1 grams/minute of hydrogen peroxide reactant; and the substrate is biased with either a positive DC bias potential, with respect to the grounded reactor chamber walls, of about +50 to +300 volts, or a low frequency AC bias potential ranging from a minimum of +50/-50 volts up to a maximum of about +300/-300 volts.

Abstract: A method for forming within a microelectronics fabrication a dielectric layer formed over, around and between patterned conductor layers. There is first provided a substrate employed within a microelectronics fabrication upon which is formed a patterned conductor layers. There is then formed over the patterned conductor layer a silicon oxide dielectric layer. There is then treated the silicon oxide dielectric layer to an anisotropic sputter etching process to remove silicon oxide dielectric material without re-deposition from the bottom of the gap between lines of the patterned conductor layer and to reform the silicon oxide dielectric layers on the sidewalls of the patterned lines to form spacer layers thereon. Both the silicon oxide dielectric layer deposition process and the sputter etching process may be repeated as desired to form the desired depth of trench and shape of spacer layer. There is then exposed the substrate to a nitrogen plasma.

Abstract: A process for forming a nanoporous dielectric silica coating on a surface of a substrate. The process includes spin-depositing alkoxysilane composition onto a surface of a substrate; spin depositing a surface hydrophobizing agent or a solvent onto an edge portion of the substrate to thereby remove the alkoxysilane composition from that area; and then curing the alkoxysilane composition to form a nanoporous dielectric silica coating. In another embodiment, an alkoxysilane composition layer is deposited onto a surface of a substrate. Then a solvent for the alkoxysilane substantially removes a portion of the alkoxysilane layer on the edge portion of the surface. This results in a transfer or cascading of a quantity of the alkoxysilane from a region adjacent to the edge portion to form a relatively thinner layer of the alkoxysilane onto the edge portion of the substrate surface. Then the relatively thinner alkoxysilane layer is removed prior to curing the alkoxysilane.

Abstract: A method of processing a semiconductor substrate, comprising the steps of: heating a substance within a first chamber, at a selected temperature which is above the minimum decomposition temperature of the substance, to cause decomposition of the substance into a predetermined gas; cooling the gas to below the minimum decomposition temperature of the substance; transporting the gas from the first chamber to a second chamber; and exposing a semiconductor substrate, located in the second chamber, to the cooled gas.

Abstract: A method of forming a phosphorus- and/or boron-containing silica layer, such as a PSG, BSG, or BPSG layer, on a substrate, such as a semiconductor substrate or substrate assembly.

Abstract: There is provided a film forming pre-treatment method used when silicon containing insulating film, etc. are to be formed by virtue of thermal CVD method on a substrate 101 on which interconnection layers, etc. are formed. Before an insulating film is deposited on the substrate 101, gaseous H.sub.2 O is plasmanized and then a surface of the substrate 101 is exposed to such plasmanized H.sub.2 O.

Abstract: This invention pertains generally to precursors and deposition methods suited to aerogel thin film fabrication. An aerogel precursor sol which contains an oligomerized metal alkoxide (such as TEOS), a high vapor pressure solvent (such as ethanol) and a low vapor pressure solvent (such as water and 1-butanol) is disclosed. By a method according to the present invention, such a precursor sol is applied as a thin film to a semiconductor wafer, and the high vapor pressure solvent is allowed to evaporate while evaporation of the low vapor pressure solvent is limited, preferably by controlling the atmosphere adjacent to the wafer. The reduced sol is then allowed to gel at a concentration determined by the ratio of metal.alkoxide to low vapor pressure solvent. One advantage of the present invention is that it provides a stable, spinnable sol for setting film thickness and providing good planarity and gap fill for patterned wafers.

Abstract: The invention relates to nanoporous dielectric films and to a process for their manufacture. Such films are useful in the production of integrated circuits. Such films are produced from a precursor of an alkoxysilane; a relatively low volatility solvent composition comprising a e C.sub.1 to C.sub.4 alkylether of a C.sub.1 to C.sub.4 alkylene glycol which is miscible in water and alkoxysilanes, having a hydroxyl concentration of 0.0084 mole/cm.sup.3 or less, a boiling point of about 175.degree. C. or more at atmospheric pressure and a weight average molecular weight of about 120 or more; a relatively high volatility solvent composition having a boiling point below that of the relatively low volatility solvent composition; optional water and an optional catalytic amount of an acid.

Abstract: Gaseous reactants capable of depositing a thin film on a semiconductor substrate are introduced into a deposition zone of a deposition apparatus through a gaseous reactants dispersion apparatus having rounded corners and smoothed anodized surfaces and maintained at a temperature ranging from about 70.degree. C. to about 85.degree. C., and preferably from about 75.degree. C. to about 80.degree. C., to inhibit the deposition and accumulation on such surfaces of charged materials capable of generating particles which may cause damage to the semiconductor substrate.

Abstract: An interlayer insulating film of a semiconductor device is made of a material in which silicon atoms are main elements, and each of the silicon atoms has an oxygen bond and a carbon bond, and further at least some of the silicon atoms have a hydrogen bond. The interlayer insulating film is formed by chemical vapor deposition employing a mixed gas of hydrogen peroxide and a reactive gas having a gas molecular structure in which silicon atoms have a hydrogen bond and a carbon bond.

Abstract: A method and apparatus for forming a halogen-doped silicon oxide film, preferably a fluorinated silicon glass (FSG) film, having compressive stress less than about -5.times.10.sup.8 dynes/cm.sup.2. In a specific embodiment, the FSG film is formed by a sub-atmospheric CVD thermal process at a pressure of between about 60-650 torr. The relatively thin film, besides having a low dielectric constant and good gap fill capability, has low compressive stress, and is particularly suitable for use as an intermetal (IMD) layer.

Abstract: The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

Abstract: The present invention relates to a film forming method for forming a planarized interlayer insulating film to cover wiring layers, etc. of a semiconductor integrated circuit device. The method includes the steps of forming on a substrate 206, a phosphorus-containing insulating film 45a containing P.sub.2 O.sub.3 by using a film forming gas in which an oxidizing.

Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O.sub.3 is disclosed. The entire method, which can be performed in a single cluster tool and even in a single chamber, begins by placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber. A "clean" silicate glass base layer that is substantially free of carbon particle impurities on an upper surface is then formed on the wafer surface in one of two ways. The first employs plasma-enhanced chemical vapor deposition using TEOS and diatomic oxygen gases as precursors to first deposit a "dirty" silicate glass base layer having carbon particle impurities imbedded on an upper surface.

Abstract: The present invention provides a method for forming a gate which provides a reduced recess in an adjacent shallow trench isolation. The process begins by forming a shallow trench isolation on a semiconductor substrate having a cell area and an I/O area. The cell area is separated from the I/O area by the shallow trench isolation. A gate is formed on the cell area of the semiconductor substrate adjacent to the shallow trench isolation. Impurity ions are implanted into the semiconductor substrate adjacent to the gate to form source and drain regions. In a key step, a resist protect oxide layer having a greater porosity than the oxide of the shallow trench isolation, is deposited over the semiconductor substrate, the gate, and the shallow trench isolation. The resist protect oxide layer is patterned to form a resist protect oxide mask over the I/O area; thereby exposing the cell area.

Abstract: Disclosed is a room temperature wet chemical growth (RTWCG) process of SiO-based insulator coatings on silicon substrates for electronic and photonic (optoelectronic) device applications. The process includes soaking the Si substrates into the growth solution. The process utilizes a mixture of H.sub.2 SiF.sub.6, N-n-butylpyridinium chloride, redox Fe.sup.2+ /Fe.sup.3+ aqueous solutions, and a homogeneous catalyst.

Abstract: Disclosed is a method for the formation of a silica-based coating film of a relatively large thickness in the manufacturing process of semiconductor devices and liquid crystal display panels by repeating the sequence consisting of coating of the surface with a coating solution containing a partial hydrolysis-condensation product of a trialkoxy silane compound followed by drying until a desired overall thickness of the coating film is obtained prior to a final baking treatment at 350 to 500.degree. C . The invention provides an improvement obtained by an ultraviolet irradiation treatment of the coating film intervening between a sequence of coating and drying and the next sequence of coating and drying so that the adhesion between the coating layers formed by repeating the sequence of coating and drying can be improved along with an advantage of absence of pinholes in the coating film.

Abstract: Methods of treating surfaces of wafers to be used in forming integrated circuit devices comprise applying dihydropyrane to the surfaces of the wafers wherein hydrophobicity is imparted to the surfaces. The applying steps are carried out prior to applying photoresists to the wafers.

Abstract: A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.

Abstract: An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.

Abstract: A process for forming a nanoporous dielectric coating on a substrate. The process follows the steps of blending an alkoxysilane with a solvent composition and optional water; depositing the mixture onto a substrate while evaporating at least a portion of the solvent composition; placing the substrate in a sealed chamber and evacuating the chamber to a pressure below atmospheric pressure; exposing the substrate to water vapor at a pressure below atmospheric pressure and then exposing the substrate to base vapor.

Abstract: A method for forming a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a silicon oxide layer, where the silicon oxide layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material at an ozone:TEOS volume ratio of from about 10:1 to about 14:1. Finally, there is then annealed thermally the substrate within an oxygen containing atmosphere at a temperature of greater than about 1100 degrees centigrade to form from the silicon oxide layer a densified silicon oxide layer. The densified silicon oxide layer formed employing the method is formed with an unexpectedly low shrinkage.

Abstract: The method for forming an insulating film having a low dielectric constant, which is suitable for intermetal insulating film applications, by plasma enhanced chemical vapor deposition (PECVD) includes the step of supplying a first source gas containing fluorine and carbon to a dual-frequency, high density plasma reactor. The method also includes the step of supplying a second source gas containing silicon dioxide to the reactor. In this manner a fluorocarbon/silicon dioxide film is formed on a substrate in the reactor.

Abstract: A method of manufacturing an insulating layer 30 (IMD layer) that has a uniform etch rate and forms improved via/contact opening profiles. The method forms a coating film 11 of silicon oxide over the chamber walls 22 of a CVD reactor. Next, the wafer 12 is loaded into the CVD reactor 20. A first insulating layer 30 composed of oxide preferably formed by a sub-atmospheric undoped silicon glass (SAUSG) using TEOS is formed over the semiconductor structure 12. Via/Contact Openings 32 are then etched in the insulating layer 30. The coating film 11 over the interior surfaces (e.g., reactor walls) 22 improves the etch rate uniformity of the first insulating layer 30. The first insulating layer 30 is preferably a inter metal dielectric (IMD) layer.

Abstract: Patterned metal layers are gap filled with HSQ and passivated to stabilize the dielectric constant of the HSQ substantially at the as-deposited value prior to oxide deposition by PECVD and planarization. Passivation and stabilization are effected by treating the as--deposited HSQ layer in a silane (SiH.sub.4) containing plasma.

Abstract: A process for forming a nanoporous dielectric coating on a substrate. The process includes either (i) combining a stream of an alkoxysilane composition with a stream of a base containing catalyst composition to form a combined composition stream; immediately depositing the combined composition stream onto a surface of a substrate and exposing the combined composition to water (in either order or simultaneously); and curing the combined composition; or (ii) combining a stream of an alkoxysilane composition with a stream of water to form a combined composition stream; immediately depositing the combined composition stream onto a surface of a substrate; and curing the combined composition.

Abstract: Disclosed is a method of manufacturing a semiconductor device aimed at improving reliability of wiring, more particularly, of a via hole when a silicon oxide film formed by a high density plasma CVD process is used as an inter-level dielectric film in an integrated circuit having a multi-level wiring structure. When the multi-level wiring structure is formed on a semiconductor substrate, after underlying wiring is formed, a silicon oxide film is formed on the entire surface of the substrate by a high density plasma CVD process, and heat treated in inert gas or oxygen atmosphere at a temperature of 300.degree. C. or more but 500.degree. C. or less for 10 minutes or more. Excess hygrogen incorporated in the silicon oxide during the CVD process is removed by the above heat treatment. Subsequently, via holes are opened, and upper wiring is formed.

Abstract: A process for forming air gaps in an interconnect system is disclosed. At least two conductive lines are formed upon a substrate. A low-dielectric constant material (LDCM) is formed between the at least two conductive lines. Formation of the LDCM creates first and second adhesive forces between the LDCM and the at least two conductive lines and between the LDCM and the substrate, respectively. The LDCM is expanded. A dielectric layer is formed onto the LDCM and the at least two conductive lines. Formation of the dielectric layer creates a third adhesive force between the LDCM and the dielectric layer. The LDCM is contracted. Contraction of the LDCM resulting from a fourth force within the LDCM. Each of the first, second, and third adhesive forces are substantially stronger than the fourth force.

Abstract: An apparatus and method for forming thin film aerogels on semiconductor substrates is disclosed. It has been found that in order to produce defect.about.free nanoporous dielectrics with a controllable high porosity, it is preferable to substantially limit evaporation and condensation of pore fluid in the wet gel thin film, e.g. during gelation, during aging, and at other points prior to obtaining a dried gel. The present invention simplifies the atmospheric control needed to prevent evaporation and condensation by restricting the atmosphere in contact with the wet gel thin film to an extremely small volume. In one embodiment, a substrate 26 is held between a substrate holder 36 and a parallel plate 22, such that a substantially sealed chamber 32 exists between substrate surface 28 and chamber surface 30. Preferably, the average clearance between surfaces 28 and 30 is less than 5 mm, or more preferably, less than 1 mm.

Abstract: A process is described for treating damaged surfaces of a low dielectric constant organo silicon oxide insulation layer of an integrated circuit structure to inhibit absorption of moisture which comprises treating such damaged surfaces of said organo silicon oxide insulation layer with a hydrogen plasma. The treatment with hydrogen plasma causes hydrogen to bond to silicon atoms with dangling bonds in the damaged surface of the organo silicon oxide layer to replace organic material severed from such silicon atoms at the damaged surface, whereby absorption of moisture in the damaged surface of the organo silicon oxide layer, by bonding of such silicon dangling bonds with moisture, is inhibited.

Abstract: A material of forming silicon oxide film comprising a polymer having a repeating unit represented by the following general formula (1A), (1B) or (1C); ##STR1## wherein R.sup.1 is a substituent group which can be eliminated at a temperature ranging from 250.degree. C. to the glass transition point of the material of forming silicon oxide film; and R.sup.2 is a substituent group which cannot be eliminated at a temperature of 250.degree. C. or more.

Abstract: A process for the manufacture of nanoporous silica dielectric films by vapor deposition of silica precursors on a substrate. The process provides for vaporizing at least one alkoxysilane composition; depositing the vaporized alkoxysilane composition onto a substrate; exposing the deposited alkoxysilane composition to a water vapor, and either an acid or a base vapor; and drying the exposed alkoxysilane composition, thereby forming a relatively high porosity, low dielectric constant, silicon containing polymer composition on the substrate.

Abstract: A process for the low temperature deposition of a thin film of borophosphosilicate glass ("BPSG") for use in semiconductor devices, such as DRAMs, is disclosed. The process includes utilizing R--OH groups as reagents to provide additional --OH groups so that an intermediate {Si(OH).sub.4 }.sub.n is formed having superior reflow properties so that the annealing and reflow steps may occur at temperatures less than 750.degree. C., which is the current processing temperature.

Abstract: The present invention relates to a method for forming a VIA in an Inter Metal Dielectric (IMD) containing Spin On Glass (SOG). The IMD is formed by 1) depositing a first silicon dioxide layer through a Chemical Vapor Deposition (CVD) process; 2) depositing a Spin On Glass (SOG) layer; and 3) depositing a second silicon dioxide layer through a Chemical Vapor Deposition process. Afterward, before the VIA is formed by an Inter Metal Dielectric (IMD) etching process, a selective ion implantation process is performed to densify the Spin On Glass(SOG) layer. By this arrangement, the outgassing effect of the Spin On Glass (SOG) during a subsequent metal deposition process can be therefore prevented.

Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl doped silicon oxide layer over a substrate. SiO.sub.2 skin is deposited on the methyl doped silicon oxide layer by decreasing the flow of CH.sub.3 SiH.sub.3, increasing the flow of SiH.sub.4 and keeping the flow of H.sub.2 O.sub.2 constant for a period of time. Finally, a cap layer is deposited which adheres to the SiO.sub.2 skin.

Abstract: A method for making a semiconductor device includes:a step for preparing a substrate;a step for forming a wiring layer on the substrate;a step for loading the substrate onto a substrate supporting unit in a reaction chamber;a step for supplying a material gas essentially consisting of a silane gas, an oxidizing gas and a chalcogen fluoride gas into the reaction chamber; anda step for forming a silicon oxide insulating film containing fluorine on the substrate by a plasma CVD process.

Abstract: A process for the chemical vapor deposition of silicon dioxide and silicon oxynitride from reactant gases O.sub.2, O.sub.3, N.sub.2 O, NO, NO.sub.2, NH.sub.3 and a silane of the formula: (t-C.sub.4 H.sub.9 NH).sub.2 SiH.sub.2. A process whereby a stack of silicon containing dielectrics ranging from silicon nitride to silicon oxide may be deposited successively (at the same pressure and temperature) by changing the reactants O.sub.2, O.sub.3, N.sub.2 O, NO, NO.sub.2, NH.sub.3 while maintaing a constant flow of (t-C.sub.4 H.sub.9 NH).sub.2 SiH.sub.2. The films are suitable for use in the semiconductor and related industries.

Abstract: The uniformity of the thickness of a deposition layer, generated by a chemical vapor deposition (CVD) process, on a semiconductor wafer is enhanced by providing an undercoating on the deposition chamber. The undercoating is formed at a deposition rate significantly faster than the deposition rate of the material on the wafer. A thin precoat is typically formed over the undercoating. Another method of providing uniformity of thickness includes altering the temperature of the wafer or a series of wafers to alter the deposition rate. The alteration of the temperature of the wafer may include the use of a temperature ramp which increases or decreases the deposition temperature between two or more wafers in a series of wafers.

Abstract: This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer 1.0-5.0 nm forms an interface to with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps.

Abstract: A silicon oxide film is formed on a wire array by CVD employing a gas mixture composed of a gas containing silicon atoms and hydrogen peroxide, and the thickness of the silicon oxide film in the region apart from the wire array is formed to be at least 50% of the wire thickness. Planarization of the silicon oxide film over the wire array region is attained.

Abstract: A film forming method is provided for forming a planarized interlayer insulating film for covering interconnection layers, etc. of a semiconductor integrated circuit device. While supplying a reaction gas including a phosphorus containing compound which has III valence phosphorus and at least one bond of phosphorus to oxygen, a silicon containing insulating film including P.sub.2 O.sub.3 is formed on a deposition substrate, thereby greatly reducing fluidization temperature for planarization.

Abstract: Controlling the thickness of borophosphorous tetraethyl orthosilicate (BPTEOS) used as all or part of the first inter-layer dielectric (ILD0) in manufacturing a semiconductor device containing an array of transistors to control the field leakage between transistors. Reducing field leakage enables the thickness of field oxide, typically used to reduce field leakage, to be reduced to increase device density in the transistor array.

Abstract: A polysilicon diffusion doping method which employs a deposited dopant-rich oxide layer with a highly uniform distribution of dopant atoms and thickness. Polysilicon layers 1,500 angstroms thick have been doped, achieving average resistance values of 60 ohms and non-uniformity values of 5 percent. Resistance values were measured using the four-point probe method with probe spacings of 0.10 cm. After a polysilicon layer has been formed upon a surface of a silicon wafer, a dopant-rich oxide layer is deposited upon the polysilicon layer at reduced pressure. The dopant-rich oxide layer is deposited, and serves as a source of dopant atoms during the subsequent diffusion process. The dopant-rich oxide layer is a phosphosilicate glass (PSG) including phosphorus pentoxide (P.sub.2 O.sub.5) and phosphorus trioxide (P.sub.2 O.sub.3) and deposited using a PECVD technique.

Abstract: The invention relates to a process for forming an integrated circuit device comprising (i) a substrate; (ii) metallic circuit lines positioned on the substrate and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises porous organic polysilica.