Ionized Irradiation (e.g., Corpuscular Or Plasma Treatment, Etc.) Patents (Class 438/798)
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Patent number: 7524776Abstract: Means and methods for producing surface-activated semiconductor nanoparticles suitable for in vitro and in vivo applications that can fluoresce in response to light excitation. Semiconductor nanostructures can be produced by generating a porous layer in semiconductor substrate comprising a network of nanostructures. Prior or subsequent to cleavage from the substrate, the nanostructures can be activated by an activation means such as exposing their surfaces to a plasma, oxidation or ion implantation. In some embodiments, the surface activation renders the nanostructures more hydrophilic, thereby facilitating functionalization of the nanoparticles for either in vitro or in vivo use.Type: GrantFiled: November 30, 2004Date of Patent: April 28, 2009Assignee: Spire CorporationInventors: Nader M. Kalkhoran, James G. Moe, Kurt J. Linden, Marisa Sambito
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Patent number: 7521382Abstract: The present invention generally relates to a high resistivity CZ silicon wafer, or a high resistivity silicon structure derived therefrom, and a process for the preparation thereof. In particular, the high resistivity silicon structure comprises a large diameter CZ silicon wafer as the substrate thereof, wherein the resistivity of the substrate wafer is decoupled from the concentration of acceptor atoms (e.g., boron) therein, the resistivity of the substrate being substantially greater than the resistivity as calculated based on the concentration of said acceptor atoms therein.Type: GrantFiled: May 18, 2006Date of Patent: April 21, 2009Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Vladimir V. Voronkov, Galina I. Voronkova, Anna V. Batunina
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Patent number: 7521312Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.Type: GrantFiled: January 5, 2007Date of Patent: April 21, 2009Assignee: Atmel CorporationInventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
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Publication number: 20090098710Abstract: An SOI substrate having a single crystal semiconductor layer with high surface planarity is manufactured. A semiconductor substrate is doped with hydrogen, whereby a damaged region which contains large quantity of hydrogen is formed. After a single crystal semiconductor substrate and a supporting substrate are bonded together, the semiconductor substrate is heated, whereby the single crystal semiconductor substrate is separated in the damaged region. While a heated high-purity nitrogen gas is sprayed on a separation plane of the single crystal semiconductor layer separated from the single crystal semiconductor substrate, laser beam irradiation is performed. By irradiation with a laser beam, the single crystal semiconductor layer is melted, whereby planarity of the surface of the single crystal semiconductor layer is improved and re-single-crystallization is performed.Type: ApplicationFiled: October 7, 2008Publication date: April 16, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Shunpei YAMAZAKI
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Patent number: 7517776Abstract: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent and depositing a strained silicon germanium layer on the substrate. The dislocation inducing agent may include ions, electrons, or other radiation source. Dislocations in the silicon germanium layer are located in one or more of the regions. The substrate and strained silicon germanium layer may then be subjected to an annealing process to transform the strained silicon germanium layer into a relaxed state. A top layer of strained silicon or silicon germanium may be deposited on the relaxed silicon germanium layer. Semiconductor-based devices may then be fabricated in the non-damaged regions of the strained silicon or silicon germanium layer. Threading dislocations are confined to damaged areas which may be transformed into SiO2 isolation regions.Type: GrantFiled: January 29, 2007Date of Patent: April 14, 2009Assignee: The Regents of the University of CaliforniaInventors: Ya-Hong Xie, Tae-Sik Yoon
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Publication number: 20090093135Abstract: Low dielectric constant materials are cured in a process chamber during semiconductor processing. The low dielectric constant materials are cured by irradiation with UV light. The atmosphere in the process chamber has an O2 concentration of about 25-10,000 ppm during the irradiation. The O2 limits the formation of —Si—H and —Si—OH groups in the low dielectric constant material, thereby reducing the occurrence of moisture absorption and oxidation in the low dielectric constant material.Type: ApplicationFiled: October 4, 2007Publication date: April 9, 2009Applicant: ASM Japan K.K.Inventors: Kiyohiro Matsushita, Kenichi Kagami
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Patent number: 7514377Abstract: To provide a generator capable of generating plasma and ozone with high efficiency and easy to handle, with a simple structure. An electrode part 10 is formed of electrodes 11 and 12 without dielectric material interposed therebetween. An arc-extinguishing capacitor 13 as a charge storage part for storing charge is connected in series to the electrode part 10. An AC power source 15 generating plasma by causing self-arc-extinguishing discharge between the electrodes 11 and 12 by applying AC voltage to charge and discharge the arc-extinguishing capacitor 13, is connected to both ends of a circuit in which the electrode part 10 and the arc-extinguishing capacitor 13 are connected in series. The arc-extinguishing capacitor 13 and one electrode 12 of the electrode part 10 connected thereto are unitized, for making the electrode part multi-polarized.Type: GrantFiled: December 26, 2003Date of Patent: April 7, 2009Assignees: Hitachi Kokusai Electric Inc., Adtec Plasma Technology Co., Ltd.Inventors: Noriyoshi Sato, Takeshi Taniguchi, Hiroshi Mase, Shuitsu Fujii, Tamiya Fujiwara
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Patent number: 7498242Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed in, preferably, insulating layers. The layers are then adequately treated with a particular plasma process. Following this plasma treatment a self-limiting, self-saturating atomic layer deposition (ALD) reaction can occur without significantly filling the pores forming improved interconnects.Type: GrantFiled: February 21, 2006Date of Patent: March 3, 2009Assignee: ASM America, Inc.Inventors: Devendra Kumar, Kamal Kishore Goundar, Nathanael R. C. Kemeling, Hideaki Fukuda, Hessel Sprey, Maarten Stokhof
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Patent number: 7485473Abstract: A method for manufacturing a semiconductor device, the method including the steps of: (a) forming a titanium layer above a substrate; (b) forming a barrier layer above the titanium layer; (c) changing the titanium layer to a titanium nitride layer by conducting a heat treatment in a nitrogen containing atmosphere; (d) forming a first electrode above the barrier layer; (e) forming a ferroelectric layer above the first electrode; and (f) forming a second electrode above the ferroelectric layer.Type: GrantFiled: August 14, 2006Date of Patent: February 3, 2009Assignee: Seiko Epson CorporationInventor: Hiroaki Tamura
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Patent number: 7482289Abstract: Methods and an apparatus are disclosed for depositing tantalum metal films in next-generation solvent fluids on substrates and/or deposition surfaces useful, e.g., as metal seed layers. Deposition involves low valence oxidation state metal precursors soluble in liquid and/or compressible solvent fluids at liquid, near-critical, or supercritical conditions for the mixed precursor solutions. Metal film deposition is effected via thermal and/or photolytic activation of the metal precursors. The invention finds application in fabrication and processing of semiconductor, metal, polymer, ceramic, and like substrates or composites.Type: GrantFiled: August 25, 2006Date of Patent: January 27, 2009Assignee: Battelle Memorial InstituteInventors: Clement R. Yonker, Dean W. Matson, John T Bays
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Patent number: 7482288Abstract: A method for producing a semiconductor product. Semiconductor product components are formed in a semiconductor product region of the substrate. A layer made of low-k material is subsequently formed on the substrate. Electrically conductive interconnects are formed in and/or on the layer made of low-k material. The layer of low-k material is provided in a wiring plane of the semiconductor product region for the electrical insulation of the interconnects from one another. A grid cap region of the substrate is subjected to a spacially delimited treatment such that the value of the dielectric constant is increased in the crossover region. Accordingly, an interconnect to interconnect capacitance is formed as grid cap capacitance from the interconnects arranged in the crossover region and the material and increased value of dielectric constant. Further, the dielectric constant of the low-k material remains unchanged in the semiconductor product region.Type: GrantFiled: June 16, 2006Date of Patent: January 27, 2009Assignee: Infineon Technologies AGInventors: Sabine Penka, Armin Fischer
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Patent number: 7479466Abstract: A method of heating-treating a semiconductor wafer is provided. In one embodiment, a first layer is formed over a first side of a substrate. A second layer is formed over the first layer and over a second side of the substrate and the wafer is then flash annealed. In another embodiment, a first layer is formed over a first side of a substrate and over a second side of the substrate. A second layer is formed over the first layers and the wafer is then flash annealed.Type: GrantFiled: July 14, 2006Date of Patent: January 20, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiao-Tzu Lu, Burn-Jeng Lin, Chin-Hsiang Lin, Kuei-Shun Chen, Tsai-Sheng Gau
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Publication number: 20090011615Abstract: Removing photoresist from a workpiece is described when a region of tungsten is exposed. A plasma is generated from a gas input consisting essentially of hydrogen gas and oxygen gas in a predetermined ratio. The plasma causes the photoresist to be removed from the workpiece while the region of tungsten is left substantially unmodified. The ratio of the hydrogen to oxygen can be adjusted to a particular value which causes the photoresist to be removed at about a maximum removal rate that corresponds to a minimum tungsten loss rate of about zero. Polysilicon oxidation in the presence of tungsten is described with little or no tungsten loss.Type: ApplicationFiled: July 3, 2007Publication date: January 8, 2009Inventors: Li Diao, Songlin Xu
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Publication number: 20090004822Abstract: A method of manufacturing a semiconductor substrate is demonstrated, which enables the formation of a single crystal semiconductor layer on a substrate having an insulating surface. The manufacturing method includes the steps of: ion irradiation of a surface of a single-crystal semiconductor substrate to form a damaged region; laser light irradiation of the single-crystal semiconductor substrate; formation of an insulating layer on the surface of the single-crystal semiconductor substrate; bonding the insulating layer with a substrate having an insulating surface; separation of the single-crystal semiconductor substrate at the damaged region, resulting in a thin single-crystal semiconductor layer on the surface of the substrate having the insulating surface; and laser light irradiation of the surface of the single-crystal semiconductor layer which is formed on the substrate having the insulating surface.Type: ApplicationFiled: June 13, 2008Publication date: January 1, 2009Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Hiromichi Godo, Atsuo Isobe
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Patent number: 7465680Abstract: A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and bottom surface of the wafer and increases the tensile stress of the deposited layer. Another embodiment of the invention involves biasing of the substrate prior to plasma treatment to bombard the wafer with plasma ions and raise the temperature of the substrate. In another embodiment of the invention, a two-step plasma treatment process can be used where the substrate is first exposed to a plasma at a processing position directly after deposition, and then raised to an elevated position where both the top and bottom of the wafer are exposed to the plasma.Type: GrantFiled: September 7, 2005Date of Patent: December 16, 2008Assignee: Applied Materials, Inc.Inventors: Xiaolin Chen, Srinivas D. Nemani, DongQing Li, Jeffrey C. Munro, Marlon E. Menezes
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Patent number: 7466907Abstract: A device for use in a thermal annealing process for a wafer (T) of material chosen among the semiconductor materials for the purpose of detaching a layer from the wafer at an weakened zone. During annealing, the device applies (1) a basic thermal budget to the wafer, with the basic thermal budget being slightly inferior to the budget necessary to detach the layer, this budget being distributed in an even manner over the weakened zone; and (2) an additional thermal budget is also applied to the wafer locally in a set region of the weakened zone so as to initiate the detachment of the layer in this region.Type: GrantFiled: May 16, 2006Date of Patent: December 16, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Walter Schwarzenbach, Jean-Marc Waechter
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Patent number: 7459403Abstract: In microelectronic circuits involving dielectric/semiconductor interfaces having interstitial sites in the dielectric, a method for hardening these interfaces by introducing a small atomic diameter inert gas into the interstitial sites.Type: GrantFiled: May 1, 2006Date of Patent: December 2, 2008Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Roderick A. B. Devine, Harold L. Hughes, Akos G. Revesz
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Patent number: 7456032Abstract: A method and system for measuring laser induced phenomena changes of at least one of a resistance, a capacitance and an inductance in a semiconductor device. The method comprises interconnecting an electrical bridge circuit across the semiconductor device, the semiconductor device being connected as one of at least four circuit elements of the bridge circuit; inducing the changes in the semiconductor; and monitoring a balance condition of the bridge circuit.Type: GrantFiled: June 21, 2005Date of Patent: November 25, 2008Assignee: Semicaps PTE Ltd.Inventors: Choon Meng Chua, Lian Ser Koh, Hoo Yin Ng, Jacob Chee Hong Phang, Soon Huat Tan
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Patent number: 7446023Abstract: A high-density plasma hydrogenation method is provided. Generally, the method comprises: forming a silicon (Si)/oxide stack layer; plasma oxidizing the Si/oxide stack at a temperature of less than 400° C., using a high density plasma source, such as an inductively coupled plasma (ICP) source; introducing an atmosphere including H2 at a system pressure up to 500 milliTorr; hydrogenating the stack at a temperature of less than 400 degrees C., using the high density plasma source; and forming an electrode overlying the oxide. The electrode may be formed either before or after the hydrogenation. The Si/oxide stack may be formed in a number of ways. In one aspect, a Si layer is formed, and the silicon layer is plasma oxidized at a temperature of less than 400 degrees C., using an ICP source. The oxide formation, additional oxidation, and hydrogenation steps can be conducted in-situ in a common chamber.Type: GrantFiled: December 15, 2004Date of Patent: November 4, 2008Assignee: Sharp Laboratories of America, Inc.Inventors: Pooran Chandra Joshi, Apostolos T. Voutsas, John W. Hartzell
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Publication number: 20080268655Abstract: The present invention is a method of manufacturing a semiconductor device from a layered body including: a semiconductor substrate; a high dielectric film formed on the semiconductor substrate; and an SiC-based film formed on a position upper than the high dielectric film, the SiC-based film having an anti-reflective function and a hardmask function. The present invention comprises a plasma-processing step for plasma-processing the SiC-based film and the high dielectric film to modify the SiC-based film and the high dielectric film by an action of a plasma; and a cleaning step for wet-cleaning the SiC-based film and the high dielectric film modified in the plasma-processing step to collectively remove the SiC-based film and the high dielectric film.Type: ApplicationFiled: November 29, 2005Publication date: October 30, 2008Inventors: Glenn Gale, Yoshihiro Hirota, Yusuke Muraki, Genji Nakamura, Masato Kushibiki, Naoki Shindo, Akitaka Shimizu, Shigeo Ashigaki, Yoshihiro Kato
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Patent number: 7439197Abstract: A method of preparing a semiconductor film on a substrate is disclosed. The method includes arranging an insulating substrate in a deposition chamber and depositing a semiconductor film onto the insulating substrate using ion beam deposition, wherein a temperature of the insulating substrate during the depositing does not exceed 250° C. The method can produce a thin film transistor. The disclosed ion beam deposition method forms, at lower temperature and with low impurities, a film morphology with desired smoothness and grain size. Deposition of semiconductor films on low melting point substrates, such as plastic flexible substrates, is enables.Type: GrantFiled: November 7, 2005Date of Patent: October 21, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-yeon Kwon, Hyuk Lim, Takashi Noguchi, Young-soo Park, Suk-pil Kim, Hans S. Cho, Ji-sim Jung, Kyung-bae Park, Do-young Kim
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Publication number: 20080248656Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.Type: ApplicationFiled: April 4, 2007Publication date: October 9, 2008Applicant: NOVELLUS SYSTEMS, INC.Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
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Publication number: 20080214021Abstract: It is an object of the present invention to align the plane orientations of crystal grains of a semiconductor film crystallized by irradiation with a linear laser beam with a width of less than or equal to 5 ?m. By performing irradiation with the linear laser beam condensed by an aspheric cylindrical lens or a gradient index lens to completely melt the semiconductor film and scanning the linear laser beam, the completely melted semiconductor film is made to grow laterally. Because the linear beam is very narrow, the width of the semiconductor which is in a liquid state is also narrow, so the occurrence of turbulent flow in the liquid semiconductor is suppressed. Therefore, growth directions of adjacent crystal grains do not become disordered due to turbulent flow and are unformalized, and thus the plane orientations of the laterally grown crystal grains can be aligned.Type: ApplicationFiled: January 10, 2008Publication date: September 4, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Koichiro TANAKA, Tomoaki MORIWAKA, Takatsugu OMATA, Junpei MOMO
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Patent number: 7410839Abstract: The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a semiconductor device which realizes high-speed operation and high-performance of the semiconductor device and a manufacturing method thereof. Further in addition, it is an object of the present invention to provide a manufacturing method in which a manufacturing process is simplified. The semiconductor device of the present invention has an island-shaped semiconductor film formed over a substrate having an insulating surface and a gate electrode formed over the island-shaped semiconductor film, in which the gate electrode is oxidized its surface by high-density plasma to be slimmed and the substantial length of a channel is shortened.Type: GrantFiled: April 25, 2006Date of Patent: August 12, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Shunpei Yamazaki
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Publication number: 20080171448Abstract: A method is provided for selectively marking a region of integrated circuit (IC). The method provides an IC die with a first region located on a backside surface of a bulk silicon (Si) layer. A semi-transparent film is formed overlying the bulk Si layer, semi-transparent to light having a first wavelength. The semi-transparent film is irradiated with light having the first wavelength in the range of 1 to 2 microns. In response to irradiating the semi-transparent film with a first power density, the IC die first region is located. Then, in response to irradiating the semi-transparent film with a second power density, greater than the first power density, a region of the semi-transparent film is marked overlying the IC die first region. In one aspect, a region of the bulk Si layer underlying the marked (or ablated away) semi-transparent film is selectively etched to expose the IC die first region.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Inventor: Joseph M. Patterson
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Publication number: 20080166894Abstract: A focus ring heat transfer method improves heat transfer of a focus ring arranged in an outer peripheral portion of a mounting surface of a mounting table adapted to mount a target substrate in a chamber. The method includes steps of: disposing a heat transfer sheet between the focus ring and the mounting table; and vacuum-evacuating the chamber prior to processing the target substrate and then restoring the pressure the inside of the chamber to an atmospheric pressure or a light vacuum pressure. Therefore, air present in a fine gap between the heat transfer sheet and the mounting surface is removed to allow the heat transfer sheet to adhere to the mounting surface.Type: ApplicationFiled: January 8, 2008Publication date: July 10, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Masaaki MIYAGAWA, Akihiro Yoshimura
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Publication number: 20080166893Abstract: A method of forming a semiconductor structure includes oxidizing a gate stack at a temperature of at most 600° C. with a plasma prepared from a gas mixture. The gas mixture includes an oxygen-containing gas and ammonia, and the gate stack is on a semiconductor substrate. The gate stack contains a gate layer, a conductive layer on the gate layer, a metal layer on the conductive layer, and a capping layer on the metal layer.Type: ApplicationFiled: January 3, 2008Publication date: July 10, 2008Inventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Patent number: 7396745Abstract: Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams.Type: GrantFiled: March 11, 2005Date of Patent: July 8, 2008Assignee: TEL Epion Inc.Inventors: John O. Borland, John J. Hautala, Wesley J. Skinner
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Patent number: 7387946Abstract: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.Type: GrantFiled: June 7, 2005Date of Patent: June 17, 2008Assignee: Freescale Semiconductor, Inc.Inventor: Thuy Dao
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Patent number: 7381943Abstract: The present invention relates to a neutral particle beam processing apparatus. More specifically, the present invention relates to a neutral particle beam processing apparatus comprising a plasma discharging space inside which processing gases are converted to plasma ions through a plasma discharge, a heavy metal plate which converts the plasma ions into neutral particles through collisions, a plasma limiter which prevents plasma ions and electrons from passing through and allows the neutral particles produced by collisions of the plasma ions with the heavy metal plate to pass through, and a treating housing inside which a substrate to be treated is located, wherein the plasma discharging space is sandwiched between the heavy metal plate and the plasma limiter.Type: GrantFiled: November 27, 2004Date of Patent: June 3, 2008Assignees: Korea Basic Science Institute, SEM Technology, Co., Ltd.Inventors: Bong-Ju Lee, Suk-Jae Yoo, Hag-Joo Lee
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Publication number: 20080121819Abstract: To provide a laser irradiation apparatus which performs alignment of an irradiated object and emits a laser beam precisely, a laser irradiation method, and a manufacturing method of a TFT with high reliability with the use of a method for precisely targeting a desired irradiation position of the laser beam. A substrate with marker is mounted on a stage formed using a material which transmits infrared light; a marker, which is provided in the substrate with marker mounted on the stage, is detected using a camera capable of sensing infrared light, and a position of the stage is controlled; a laser beam is emitted from a laser oscillator; the laser beam emitted from the laser oscillator is processed into a linear shape by an optical system, and the substrate with marker mounted on the stage is irradiated with the laser beam.Type: ApplicationFiled: November 19, 2007Publication date: May 29, 2008Inventors: Koichiro Tanaka, Takatsugu Omata
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Patent number: 7372049Abstract: An EUV lithographic apparatus includes an EUV radiation source, an optical element and a cleaning device. The cleaning device includes a hydrogen radical source and a flow tube in communication with the hydrogen radical source. The cleaning device is configured to provide a flow of hydrogen radicals and the flow tube is arranged to provide a hydrogen radical flow at a predetermined position within the lithographic apparatus, for example for cleaning a collector mirror.Type: GrantFiled: December 2, 2005Date of Patent: May 13, 2008Assignee: ASML Netherlands B.V.Inventors: Maarten Marinus Johannes Wilhelmus Van Herpen, Derk Jan Wilfred Klunder
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Patent number: 7357963Abstract: A sequential lateral solidification apparatus includes a laser generator for generating and emitting a laser beam; an X-Y stage movable in two orthogonal axial directions; and a mask arranged between the laser generator and the X-Y stage. The mask has a plurality of slits through which the laser beam passes. An objective lens for scaling down the laser beam is arranged between the mask and the X-Y stage. A mask stage is connected to the mask for controlling minute movement of the mask for crystallizing amorphous silicon in one block.Type: GrantFiled: December 26, 2001Date of Patent: April 15, 2008Assignee: LG.Philips LCD Co., Ltd.Inventor: Yun-Ho Jung
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Patent number: 7358200Abstract: A system, method and apparatus for processing a semiconductor device including a processing chamber and a heating assembly positioned within the processing chamber. The heating assembly including at least a plate defining an internal cavity configured to receive gas. The gas enters the internal cavity through a first passage at a first temperature, and exits the internal cavity at a second temperature through a second passage.Type: GrantFiled: November 24, 2004Date of Patent: April 15, 2008Assignee: WaferMasters, Inc.Inventor: Woo Sik Yoo
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Publication number: 20080079119Abstract: A p-n junction is formed at the interface of a low-concentration n-type impurity layer 3 and a p-type diffusion region 5 in the vicinity of the upper major surface of an n-type semiconductor substrate 2 of a semiconductor device 1. A mask 15 composed of an absorber is placed on the upper major surface of the semiconductor device 1, and electron beams are radiated. Thereafter, heat treatment is conducted. As a result, the peak of the crystal lattice defect densities is present in the vicinity of the upper major surface of the n-type semiconductor substrate 2, and the crystal lattice defect densities are decreasingly distributed toward the lower major surface. Thereby, a semiconductor device that can minimize the variation of the breakdown voltage characteristics of the p-n junction of the diode, and can control the optimum carrier lifetime can be obtained.Type: ApplicationFiled: February 23, 2007Publication date: April 3, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Masanori INOUE
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Patent number: 7351669Abstract: To form a substantially closed void between two structures on a substrate, a flowable liquid dielectric material is deposited to fill partially the space between the structures, and a surface is placed to bridge and substantially close the space between the structures. The substrate is then inverted whilst maintaining the bridge and the deposited material is allowed to flow down to be substantially supported by the surface. The material is set in its substantially supported position, and the surface is removed.Type: GrantFiled: August 23, 2004Date of Patent: April 1, 2008Assignee: Aviza Technology LimitedInventor: John MacNeil
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Patent number: 7314838Abstract: A method for forming a high density dielectric film by chemical vapor deposition. The method comprises: (a) a substrate is provided in a processing chamber; (b) a first gas is introduced into the processing chamber with a first pressure and adsorbed on the substrate, wherein the first gas comprises silicon-containing or carbon-containing gas; (c) the first gas is stopped, and the first pressure is lowered to a second pressure; (d) a second gas is introduced into the processing chamber with a third pressure, and forced to react with the first gas absorbed on the substrate and remained in the processing chamber, wherein the second gas comprises oxidizer or reduction agent; (e) the steps (b)˜(d) are repeated until a high density dielectric film is formed on the substrate.Type: GrantFiled: July 21, 2005Date of Patent: January 1, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yuan Tsai, Chih-Lung Lin, You-Hua Chou
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Publication number: 20070293012Abstract: Exemplary embodiments provide methods for reducing and/or removing slip and plastic deformations in semiconductor materials by use of one or more ultra-fast thermal spike anneals. The ultra-fast thermal spike anneal can be an ultra-high temperature (UHT) anneal having an ultra-short annealing time. During the ultra-fast thermal spike anneal, an increased annealing power density can be used to achieve a desired annealing temperature required by manufacturing processes. In an exemplary embodiment, the annealing temperature can be in the range of about 1150° C. to about 1390° C. and the annealing dwell time can be on the order of less than about 0.8 milliseconds. In various embodiments, the disclosed spike-annealing processes can be used to fabrication structures and regions of MOS transistor devices, for example, drain and source extension regions and/or drain and source regions.Type: ApplicationFiled: June 14, 2007Publication date: December 20, 2007Inventor: Amitabh Jain
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Publication number: 20070293057Abstract: A new technique and Method of Direct Coulomb Explosion in Laser Ablation of Semiconductor Structures in semiconductor materials is disclosed. The Method of Direct Coulomb Explosion in Laser Ablation of Semiconductor Structures provides activation of the “Coulomb explosion” mechanism in a manner which does not invoke or require the conventional avalanche photoionization mechanism, but rather utilizes direct interband absorption to generate the Coulomb explosion threshold charge densities. This approach minimizes the laser intensity necessary for material removal and provides optimal machining quality. The technique generally comprises use of a femtosecond pulsed laser to rapidly evacuate electrons from a near surface region of a semiconductor or dielectric structure, and wherein the wavelength of the laser beam is chosen such that interband optical absorption dominates the carrier production throughout the laser pulse.Type: ApplicationFiled: June 20, 2007Publication date: December 20, 2007Inventor: William W. Chism
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Publication number: 20070281497Abstract: Methods are provided for processing a substrate comprising a bilayer barrier film thereon. In one aspect, a method comprises depositing a first barrier layer, depositing a second barrier layer on the first barrier layer, depositing a dielectric layer on the bilayer barrier film formed by the first barrier layer and the second barrier layer, and ultraviolet curing the dielectric layer. In another aspect, a method comprises depositing a first barrier layer, depositing a second barrier layer on the first barrier layer, depositing a dielectric layer on the bilayer barrier film formed by the first barrier layer and the second barrier layer, and curing the dielectric layer with an electron beam treatment.Type: ApplicationFiled: May 21, 2007Publication date: December 6, 2007Inventors: Yijun Liu, Huiwen Xu, Li-Qun Xia, Chad Peterson, Hichem M'saad
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Patent number: 7294590Abstract: Method and apparatus for removing and neutralizing charges. The method includes loading a structure into a chamber. The structure includes a first surface and a plurality of charges away from the first surface. Additionally, the method includes supplying a first ionized gas to the first surface of the structure, and radiating the structure with a first ultraviolate light. The supplying a first ionized gas and the radiating the structure with a first ultraviolate light are performed simultaneously for a first period of time.Type: GrantFiled: January 12, 2005Date of Patent: November 13, 2007Assignee: Hermes-Microvision, Inc.Inventors: Yi Xiang Wang, Guofan Ye
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Patent number: 7288294Abstract: A method of crystallizing amorphous silicon, wherein the method includes supplying nanoparticles over a surface of an amorphous silicon layer; intermittently melting nanoparticles that reach the surface of the amorphous silicon layer while supplying the nanoparticles; and cooling the amorphous silicon layer to grow crystals using unmolten nanoparticles as crystal seeds, thereby forming a polysilicon layer. Externally supplied nanoparticles are used as crystal seeds to crystallize an amorphous silicon layer so that large grains can be formed. Accordingly, since the number and size of nanoparticles may be controlled, the size and arrangement of grains may also be controlled.Type: GrantFiled: April 17, 2003Date of Patent: October 30, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Yoon-ho Khang
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Publication number: 20070227665Abstract: A plasma processing method performs a desired plasma process on substrates by using a plasma generated in a processing space. A first and a second electrode are disposed in parallel in a processing vessel that is grounded, the substrate is supported on the second electrode to face the first electrode, the processing vessel is vacuum evacuated, a desired processing gas is supplied into the processing space formed between the first electrode, the second electrode and a sidewall of the processing vessel, and a first radio frequency power is supplied to the second electrode. The first electrode is connected to the processing vessel via an insulator or a space, and is electrically coupled to a ground potential via a capacitance varying unit whose electrostatic capacitance is varied based on a process condition of the plasma process performed on the substrate.Type: ApplicationFiled: March 30, 2007Publication date: October 4, 2007Applicant: TOKYO ELECTRON LIMITEDInventors: Naoki Matsumoto, Chishio Koshimizu, Manabu Iwata, Satoshi Tanaka
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Publication number: 20070224840Abstract: A method of selecting plasma doping process parameters includes determining a recipe parameter database for achieving at least one plasma doping condition. The initial recipe parameters are determined from the recipe parameter database. In-situ measurements of at least one plasma doping condition are performed. The in-situ measurements of the at least one plasma doping condition are correlated to at least one plasma doping result. At least one recipe parameter is changed in response to the correlation so as to improve at least one plasma doping process performance metric.Type: ApplicationFiled: March 19, 2007Publication date: September 27, 2007Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Anthony Renau, Vikram Singh, Atul Gupta, Timothy Miller, Edwin Arevalo, George Papasouliotis, Yong Bae Jeon
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Patent number: 7268087Abstract: In order to provide a manufacturing method of a semiconductor device which can improve the interconnection lifetime, while controlling the increase in resistance thereof, and, in addition, can raise the manufacturing stability; by applying a plasma treatment to the surface of a copper interconnection 17 with a source gas comprising a nitrogen element being used, a copper nitride layer 24 is formed, and thereafter a silicon nitride film 18 is formed. Hereat, under the copper nitride layer 24, a thin copper silicide layer 25 is formed.Type: GrantFiled: July 28, 2004Date of Patent: September 11, 2007Assignee: NEC Electronics CorporationInventors: Hidemitsu Aoki, Hiroaki Tomimori, Norio Okada, Tatsuya Usami, Koichi Ohto, Takamasa Tanikuni
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Patent number: 7265038Abstract: A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.Type: GrantFiled: November 25, 2003Date of Patent: September 4, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Kun Wu, Horng-Huei Tseng, Chine-Gie Lo, Chao-Hsiung Wang, Shau-Lin Shue
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Patent number: 7262142Abstract: The semiconductor device fabrication method comprises the step of forming a first porous insulation film 38 over a semiconductor substrate 10; the step of forming a second insulation film 40 whose density is higher than that of the first porous insulation film 38; and the step of applying electron beams, UV rays or plasmas with the second insulation film 40 present to the first porous insulation film 38 to cure the first porous insulation film 38. The electron rays, etc. are applied to the first porous insulation film 38 through the denser second insulation film 40, whereby the first porous insulation film 38 can be cured without being damaged. The first porous insulation film 38 can be kept from being damaged, whereby the moisture absorbency and density increase can be prevented, and resultantly the dielectric constant increase can be prevented. Thus, the present invention can provide a semiconductor device including an insulation film of low dielectric constant and high mechanical strength.Type: GrantFiled: October 27, 2005Date of Patent: August 28, 2007Assignee: Fujitsu LimitedInventors: Yoshihiro Nakata, Shirou Ozaki, Ei Yano
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Patent number: 7256148Abstract: A method for treating an edge portion of a wafer with a plasma or select chemical formulation in order to enhance adhesion characteristics and inhibit delamination of a layer of material from the wafer surface only on the edge portion that is being treated. Alternatively, the method may be utilized to effectuate a cleaning of an edge portion of a wafer.Type: GrantFiled: May 12, 2005Date of Patent: August 14, 2007Assignee: International Business Machines CorporationInventors: Bernd E. Kastenmeier, Andreas Knorr
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Patent number: 7235427Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.Type: GrantFiled: February 24, 2005Date of Patent: June 26, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani
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Patent number: 7232773Abstract: The invention drastically improves the accuracy of adhesion position of a liquid drop discharged by a liquid drop discharge method and makes it possible to form a fine and highly accurate pattern directly on a substrate. Therefore, one object of the invention is to provide a method for manufacturing a wiring, a conductive layer and a display device that can respond to upsizing of a substrate. Moreover, another object of the invention is to provide a method for manufacturing a wiring, a conductive layer and a display device that can improve throughput and the efficiency of use of material. The invention can improve the accuracy of adhesion position of a liquid drop drastically at the time of patterning a resist material, a wiring material, or the like directly by the liquid drop discharge method mainly on a substrate having an insulating surface.Type: GrantFiled: April 20, 2004Date of Patent: June 19, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Keitaro Imai, Shunpei Yamazaki