Specified Shape Junction Barrier (e.g., V-grooved Junction, Etc.) Patents (Class 438/81)
  • Publication number: 20150075599
    Abstract: A device operable to convert light to electricity, comprising: a substrate comprising a semiconductor material, one or more structures essentially perpendicular to the substrate, one or more layers conformally disposed on the one or more structures wherein the one or more structures and the one or more layers form one or more junctions, and an electrically conductive material disposed on the substrate in the area between the one or more structures.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: ZENA TECHNOLOGIES, INC.
    Inventors: Young-June YU, Munib WOBER
  • Patent number: 8952242
    Abstract: A photovoltaic device includes one or more structures, an array of at least one of quantum dots and quantum dashes, at least one groove, and at least one conductor. Each of the structures comprises an intrinsic layer on one of an n type layer and a p type layer and the other one of the n type layer and the p type layer on the intrinsic layer. The array of at least one of quantum dots and quantum dashes is located in the intrinsic layer in at least one of the structures. The groove extends into at least one of the structures and the conductor is located along at least a portion of the groove.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: February 10, 2015
    Assignees: Rochester Institute of Technology, The United States of America as represented by the National Aeronautics and Space Administration
    Inventors: Ryne P. Raffaele, David M. Wilt
  • Patent number: 8941145
    Abstract: Systems and methods for dry eteching a photodetector array based on InAsSb are provided. A method for fabricating an array of photodetectors includes receiving a pattern of an array of photodetectors formed from InAsSb, the pattern including at least one trench defined between adjacent photodetectors, and dry etching the at least one trench with a plasma including BrCl3 and Ar.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: January 27, 2015
    Assignee: The Boeing Company
    Inventor: Pierre-Yves Delaunay
  • Publication number: 20150002712
    Abstract: According to one embodiment, a solid-state image pickup device includes a pixel array that includes a two-dimensionally arranged matrix of photoelectric conversion elements corresponding to pixels of a picked-up image. Each of the photoelectric conversion elements includes a first conductive semiconductor region and a second conductive semiconductor region between which an uneven junction plane is formed.
    Type: Application
    Filed: December 2, 2013
    Publication date: January 1, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Motohiro MAEDA, Nagataka Tanaka
  • Patent number: 8829336
    Abstract: A photovoltaic device includes one or more structures, an array of at least one of quantum dots and quantum dashes, at least one groove, and at least one conductor. Each of the structures comprises an intrinsic layer on one of an n type layer and a p type layer and the other one of the n type layer and the p type layer on the intrinsic layer. The array of at least one of quantum dots and quantum dashes is located in the intrinsic layer in at least one of the structures. The groove extends into at least one of the structures and the conductor is located along at least a portion of the groove.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: September 9, 2014
    Assignee: Rochester Institute of Technology
    Inventors: Ryne P. Raffaelle, David M. Wilt
  • Patent number: 8823147
    Abstract: A semiconductor substrate (100) has three doped zones (1), (2) and (3), forming a P-N junction (101), the third zone being located between the first zone and the second zone. The P-N junction of the substrate further has a fourth doped zone (4) having a first portion (4A) in contact with the first zone; and a second portion (4B) in contact with the third zone (3), said second portion (4B) extending in the direction of the second zone (2), and not being in contact with the second zone (2); where the fourth zone (4) being doped with the same type of doping as that of the first zone.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: September 2, 2014
    Assignee: Altis Semiconductor
    Inventors: Olivier Philippe Kellener, Gérard Dubois, Mehdi Mohamed Kanoun, Stephen McArdle
  • Patent number: 8816412
    Abstract: An image sensor having a light receiving region and an optical black region includes a semiconductor substrate, an interconnection disposed on the semiconductor substrate and extending along an interface between the light receiving region and the optical black region, and via plugs disposed between the interconnection and the semiconductor substrate and serving as light shielding members at the interface. The via plugs are arranged in a zigzagging pattern along the interface.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keon Yong Cheon, Jong-Won Choi, Sung-Hyun Yoon
  • Publication number: 20140182653
    Abstract: Disclosed are a solar cell and a solar cell module using the same. The solar cell according to the embodiment includes a stepped portion on a support substrate; a back electrode layer having a first height difference on the support substrate and the stepped portion; a light absorbing layer having a second height difference on the back electrode layer; and a front electrode layer having a third height difference on the light absorbing layer. The solar cell module according to the embodiment includes a stepped portion on a support substrate; a first solar cell on the support substrate; and a second solar cell on the stepped portion, wherein the first solar cell is electrically connected to the second solar cell on a lateral side of the stepped portion.
    Type: Application
    Filed: July 13, 2012
    Publication date: July 3, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventor: Gi Gon Park
  • Patent number: 8729383
    Abstract: Disclosed are a stacked-layered thin film solar cell and a manufacturing method thereof. The stacked-layered thin film solar cell includes plural unit cells connected together electrically, each including a substrate, a first electrode layer, a first photoconductive layer, an interlayer, a second photoconductive layer and a second electrode layer, wherein the first electrode layer is divided by plural first grooves; plural second grooves are formed through the second photoconductive layer, the interlayer, and the first photoconductive layer; and plural third grooves are formed in the second electrode layer and extended downward through the first photoconductive layer. The first, second and third grooves are offset with respect to one another.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: May 20, 2014
    Assignee: Nexpower Technology Corp.
    Inventors: Chun-Hsiung Lu, Chien-Chung Bi
  • Patent number: 8703522
    Abstract: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek
  • Publication number: 20140083486
    Abstract: Disclosed are a solar cell and a method for fabricating the same. The solar cell according to the present invention comprises a substrate including a plurality of unit cell regions and a plurality of wiring regions positioned between the unit cell regions; a first semiconductor layer being formed on any one unit cell area of the plurality of unit cell regions; a partition layer being formed on the first semiconductor layer and partitioning a region on the first semiconductor layer into first and second regions; a separation layer being formed on any one wiring region of the plurality of wiring regions; a first electrode layer being formed on the first region of the first semiconductor layer; a second semiconductor layer being formed on the second region of the first semiconductor layer; a second electrode layer being formed on the second semiconductor layer; and an electrode connection layer being connected to one end of the second electrode layer as the same layer and being formed on the separation layer.
    Type: Application
    Filed: May 23, 2012
    Publication date: March 27, 2014
    Inventors: Byung Kuk Kim, Jae Sung Lee
  • Patent number: 8637986
    Abstract: A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: January 28, 2014
    Assignee: Spansion LLC
    Inventors: Naomi Masuda, Masataka Hoshino, Ryota Fukuyama
  • Patent number: 8476102
    Abstract: A method for manufacturing a solid state image pickup device including a first active region provided with a first conversion unit, a second active region provided with a second conversion unit, and a third active region adjoining the first and the second active regions with a field region therebetween and being provided with a pixel transistor, the method including the steps of ion-implanting first conductivity type impurity ions to form a semiconductor region serving as a potential barrier against the signal carriers at a predetermined depth in the third active region and ion-implanting second conductivity type impurity ions into the third active region with energy lower than the above-described ion-implantation energy.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: July 2, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideaki Takada, Toru Koizumi, Yasuo Yamazaki, Tatsuya Ryoki
  • Patent number: 8455294
    Abstract: A method for making the image sensor structure, for avoiding or mitigating lens shading effect. The image sensor structure includes a substrate, a sensor array disposed at the surface of the substrate, a dielectric layer covering the sensor array, wherein the dielectric layer includes a top surface having a dishing structure, an under layer filled into the dishing structure and having a refraction index greater than that of the dielectric layer, a filter array disposed on the under layer corresponding to the sensor array, and a microlens array disposed above the filter array. A top layer may be additionally disposed to cover the filter array and the microlens array is disposed on the top layer.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: June 4, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Cheng-Hung Yu
  • Patent number: 8409911
    Abstract: A method for metallization of solar cells is disclosed. The method includes providing a superstrate, such as a sheet of polymer film, to be used as a transport during metallization of solar cells. The method includes attaching the back sides of the solar cells to the sheet of polymer film. The method also includes forming contact holes through the sheet of polymer film to expose doped regions of the solar cells. The method also includes forming metals in the contact holes to electrically connect to the exposed doped regions of the solar cells. The method further includes electroplating the metals to form metal contacts of the solar cell. Subsequently, the method also includes separating the solar cells from other solar cells that were metallized while supported by the same sheet of polymer film to form strings of solar cells or individual solar cells.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: April 2, 2013
    Assignee: SunPower Corporation
    Inventor: Peter John Cousins
  • Patent number: 8349640
    Abstract: A method of manufacturing an image sensor having a plurality of pixels, each pixel having a photoelectric converter including an accumulation region, and a transfer gate, the accumulation region extending under a corresponding transfer gate, the plurality of pixels including a plurality of pixel groups, each pixel group including N adjacent pixels, and the channels of the N adjacent pixels, in each pixel group, being configured to transfer the charges of the N adjacent pixels away from each other, the method comprising a step of forming a resist pattern having one opening corresponding to each pixel group, and a step of forming a charge accumulation region for each of the N adjacent pixels by implanting ions into a substrate through the one opening of the resist pattern along N ion implantation directions so as to implant the ions under the transfer gate of each of the N adjacent pixels.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: January 8, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takehiko Soda
  • Patent number: 8263855
    Abstract: Apparatus and Method for Optimizing the Efficiency of a Bypass Diode in Solar Cells. In a preferred embodiment, a layer of TiAu is placed in an etch in a solar cell with a contact at a doped layer of GaAs. Electric current is conducted through a diode and away from the main cell by passing through the contact point at the GaAs and traversing a lateral conduction layer. These means of activating, or “turning on” the diode, and passing the current through the circuit results in greater efficiencies than in prior art devices. The diode is created during the manufacture of the other layers of the cell and does not require additional manufacturing.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: September 11, 2012
    Assignee: Emcore Solar Power, Inc.
    Inventors: Paul R. Sharps, Marvin Brad Clevenger, Mark A Stan
  • Patent number: 8143687
    Abstract: A broadband radiation detector includes a first layer having a first type of electrical conductivity type. A second layer has a second type of electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region. A third layer has the second type of electrical conductivity type and an energy bandgap responsive to radiation in a second spectral region comprising longer wavelengths than the wavelengths of the first spectral region. The broadband radiation detector further includes a plurality of internal regions. Each internal region may be disposed at least partially within the third layer and each internal region may include a refractive index that is different from a refractive index of the third layer. The plurality of internal regions may be arranged according to a regularly repeating pattern.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: March 27, 2012
    Assignee: Raytheon Company
    Inventors: Justin G. A. Wehner, Scott M. Johnson
  • Patent number: 8110426
    Abstract: A pixel of a complementary metal oxide semiconductor (CMOS) image sensor includes a plurality of photodiodes for sensing light to thereby generate photoelectric charges in different regions; a plurality of transfer transistors for transferring photoelectric charges of corresponding photodiodes in response to a first control signal; a floating diffusion region for receiving photoelectric charges transferred by the plurality of transfer transistors; a rest transistor connected between a power supply voltage and the floating diffusion region for resetting the floating diffusion region by controlling a voltage loaded on the floating diffusion region in response to a second control signal; a drive transistor connected between the power supply voltage and the floating diffusion region to serve as a source follower buffer amplifier; and a select transistor connected between the drive transistor and a pixel output terminal for performing an addressing operation in response to a third control signal.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: February 7, 2012
    Assignee: Intellectual Ventures II LLC
    Inventor: Nan-Yi Lee
  • Patent number: 7999340
    Abstract: An apparatus and method for forming optical black pixels having uniformly low dark current. Optical Black opacity is increased without having to increase Ti/TiN layer thickness. A hybrid approach is utilized combining a Ti/TiN OB layer in conjunction with in-pixel metal stubs that further occlude the focal radius of each pixel's incoming light beam. Additional metal layers can be used to increase the opacity into the infrared region.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: August 16, 2011
    Assignee: AltaSens, Inc.
    Inventors: Giuseppe Rossi, Lester Kozlowski, Henry Lin, John Richardson, Gregory Chow, Gaurang Patel
  • Patent number: 7883998
    Abstract: It is to provide a vapor phase growth method in which an epitaxial layer consisting of a compound semiconductor such as InAlAs, can be grown, with superior reproducibility, on a semiconductor substrate such as Fe-doped InP. In vapor phase growth method for growing an epitaxial layer on a semiconductor substrate, a resistivity of the semiconductor substrate at a room temperature is previously measured, a set temperature of the substrate is controlled depending on the resistivity at the room temperature such that a surface temperature of the substrate is a desired temperature regardless of the resistivity of the semiconductor substrate, and the epitaxial layer is grown.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: February 8, 2011
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Masashi Nakamura, Suguru Oota, Ryuichi Hirano
  • Patent number: 7884001
    Abstract: Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a gate over a semiconductor substrate, a first impurity region over the semiconductor substrate, a second impurity region over the semiconductor substrate, the second impurity region being shallower than the first impurity region, and a third impurity region formed in the first impurity region, and bent toward the gate at a predetermined angle. According to embodiments, the third impurity region may be an n-type impurity region. According to embodiments, an area of a photodiode may be increased and a transfer efficiency of electrons generated from a photodiode may be increased.
    Type: Grant
    Filed: December 27, 2008
    Date of Patent: February 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Joung-Ho Lee
  • Publication number: 20100258159
    Abstract: A thin film type solar cell and a method for manufacturing the same is disclosed, the thin film type solar cell comprising a substrate; front electrodes arranged at fixed intervals on the substrate by separating parts for dividing the solar cell into a plurality of unit cells, wherein each separating part is interposed between the front electrodes; semiconductor layer patterns arranged at fixed intervals on the front electrodes by the interposed separating parts; rear electrodes arranged at fixed intervals on the semiconductor layer patterns by the interposed separating parts; and auxiliary electrodes to electrically connect the front electrodes with the rear electrodes, in which the front electrode is electrically connected with the rear electrode through the use of auxiliary electrode, so that it is possible to minimize the laser-scribing procedure for dividing the solar cell into the plurality of unit cells, thereby preventing the particles from being generated.
    Type: Application
    Filed: October 30, 2008
    Publication date: October 14, 2010
    Applicant: JUSUNG ENGINEERING CO., LTD.
    Inventors: Jin Hong, Jae Ho Kim, Joung Sik Kim
  • Patent number: 7786545
    Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type conductive layer formed at side surfaces of the second interconnection, and an intrinsic layer formed between the first and second conductive-type conductive layers thereby forming a P-I-N structure.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: August 31, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Seoung Hyun Kim
  • Patent number: 7781891
    Abstract: A switching element is of a configuration that includes: an ion conduction layer (40) for conducting metal ions, a first electrode (21) and a second electrode (31) provided in contact with the ion conduction layer, a third electrode (35) that can supply metal ions to the ion conduction layer, and a diffusion prevention layer (90) provided between the ion conduction layer (40) and the third electrode (35) for preventing the diffusion of metal ions from the third electrode (35) to the ion conduction layer (40). By adopting this configuration, the set state of a switch can be maintained with greater stability.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: August 24, 2010
    Assignee: Nec Corporation
    Inventors: Toshitsugu Sakamoto, Hisao Kawaura
  • Patent number: 7736927
    Abstract: A photodetector is formed in a semiconductor body. A hard mask grating is photolithographically formed on a surface of the semiconductor body. The semiconductor body is etched using the hard mask grating as a mask. The etching is performed down to a predetermined depth. An implantation is performed such that an anode or cathode of the photodetector that has been interrupted during the etching is re-formed.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: June 15, 2010
    Assignee: Infineon Technologies AG
    Inventors: Holger Wille, Gernot Langguth, Karl-Heinz Mueller
  • Patent number: 7732706
    Abstract: The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: June 8, 2010
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Nick Mardesich
  • Patent number: 7649219
    Abstract: An image sensor and a method of manufacturing the same are provided. The image sensor includes a semiconductor substrate, a metal line layer, a first conduction type conducting layer, a first pixel isolation layer, an intrinsic layer, and second conduction type conducting layer. The semiconductor substrate includes a circuit region. The metal line layer including a plurality of metal lines and an interlayer insulating layer is formed on the semiconductor substrate. The first conductive layer having patterns separated from each other by the pixel isolation layer is formed on the metal lines. The first pixel isolation layer is formed between the separated patterns of the first conduction type conducting layer. The intrinsic layer is formed on the first conductive layer and the first pixel isolation layer. The second conduction type conducting layer is formed on the intrinsic layer.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: January 19, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Seong Gyun Kim
  • Patent number: 7638853
    Abstract: A solid state imaging device includes: an imaging region formed in an upper part of a substrate made of silicon to have a photoelectric conversion portion, a charge accumulation region of the photoelectric conversion portion being of a first conductivity type; a device isolation region formed in at least a part of the substrate to surround the photoelectric conversion portion; and a MOS transistor formed on a part of the imaging region electrically isolated from the photoelectric conversion region by the device isolation region. The width of the device isolation region is smaller in its lower part than in its upper part, and the solid state imaging device further includes a dark current suppression region surrounding the device isolation region and being of a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: December 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Takumi Yamaguchi, Toru Okino
  • Patent number: 7605017
    Abstract: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: October 20, 2009
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7598132
    Abstract: An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integration period, incident light causes electrons to be accumulated inside the buried accumulation region. The resistance characteristic of the channel region changes in response to a field created by the charges accumulated in the accumulation region. Thus, when a voltage is applied to one side of the channel, the current read out from the other side is characteristic of the amount of stored charges.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: October 6, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Dmitri Jerdev, Nail Khaliullin
  • Patent number: 7595543
    Abstract: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: September 29, 2009
    Assignee: Australian National University
    Inventors: Klaus Johannes Weber, Andrew William Blakers
  • Patent number: 7585696
    Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type conductive layer formed at side surfaces of the second interconnection, and an intrinsic layer formed between the first and second conductive-type conductive layers thereby forming a P-I-N structure.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: September 8, 2009
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Seoung Hyun Kim
  • Patent number: 7564083
    Abstract: An active pixel sensor is proposed by the invention. The position of the gate of the reset transistor is kept away from the interface of the isolation region and the silicon so that the depletion region does not reach the isolation. Accordingly, dark currents caused by isolation region damages can be avoided.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: July 21, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Jhy-Jyi Sze, Junbo Chen, Ming-Yi Wang
  • Patent number: 7495264
    Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: February 24, 2009
    Assignee: NEC Corporation
    Inventors: Heiji Watanabe, Haruhiko Ono, Nobuyuki Ikarashi
  • Patent number: 7485947
    Abstract: A zener diode circuit includes a semiconductor substrate having an N-doped region and a P-doped region that form a PN junction. The N-doped region and the P-doped region have areas with widths that decrease as the N-doped region and the P-doped region approach the PN junction. The zener diode circuit also includes a transistor that provides current to the zener diode, and circuitry that detects a state of the zener diode.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: February 3, 2009
    Assignee: Austriamicrosystems AG
    Inventor: Franz Unterleitner
  • Patent number: 7445951
    Abstract: A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the trench photosensor.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: November 4, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 7238968
    Abstract: The present invention presents a semiconductor device (10) which is adapted to a solar cell, and in which a semiconductor element (1) is produced by forming one flat surface (2) on a spherical or substantially spherical silicon single crystal (1a, 1b). A diffusion layer (3) and a substantially spherical pn junction (4) are formed on this semiconductor element (1), and a diffusion-mask thin film (5) and a positive electrode (6a) are formed on the flat surface (2). A negative electrode 6b is formed at the apex on the opposite side to the positive electrode (6a), and an antireflection film (7) is formed on the surface side of the diffusion layer (3).
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: July 3, 2007
    Inventor: Josuke Nakata
  • Patent number: 7217883
    Abstract: A solar cell involving a silicon wafer having a basic doping, a light-receiving front side and a backside, which is provided with an interdigital semiconductor pattern, which interdigital semiconductor pattern has a first pattern of at least one first diffusion zone having a first doping and a second pattern of at least one second diffusion zone, separated from the first diffusion zone(s) and having a second doping that differs from the first doping, wherein each second diffusion zone is arranged along the sides of at least one groove extending from the backside into the silicon wafer.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 15, 2007
    Assignee: Shell Solar GmbH
    Inventor: Adolf Münzer
  • Patent number: 7132297
    Abstract: A thin-film multilayer high-Q inductor having a ferromagnetic core and spanning at least three metal layers is formed by forming a plurality of parallel first metal runners on the semiconductor substrate. A plurality of first and second vertical conductive vias are formed in electrical connection with each end of the plurality of metal runners. A plurality of third and fourth conductive vias are formed over the plurality of first and second conductive vias and a plurality of second metal runners are formed interconnecting the plurality of third and fourth conductive vias. The first metal runners and second metal runners are oriented such that one end of a first metal runner is connected to an overlying end of a second metal runner by way of the first and third vertical conductive vias. The other end of the second metal runner is connected to the next metal one runner by way of the second and fourth vertical conductive vias., forming a continuously conductive structure having a generally helical shape.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: November 7, 2006
    Assignee: Agere Systems Inc.
    Inventors: Michelle D. Griglione, Paul Arthur Layman, Mohamed Laradji, J. Ross Thomson, Samir Chaudhry
  • Patent number: 7064418
    Abstract: A method and a structure of a diode are provided. The diode is used in an electrostatic discharge protection circuit using TFT (Thin Film Transistor) fabrication technology. A semiconductor layer is formed on a substrate. A first region of a first carrier concentration is formed in the semiconductor layer. A second region of a second carrier concentration is formed in the semiconductor layer. An insulator is formed on the semiconductor layer. The insulator layer is etched to form at least a contact window. The contact window exposes a portion of an upper surface of the semiconductor layer. A metal layer is formed on the insulator layer. The metal layer fills up the contact window to contact the semiconductor layer.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: June 20, 2006
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Ying-Hsin Li, Sheng-Chieh Yang, An Shih, Ming-Dou Ker, Tang-Kui Tseng, Chih-Kang Deng
  • Patent number: 7057255
    Abstract: A photodiode (PD chip) includes a substrate, an absorption layer, a p-n junction in the absorption layer, a passivation film for protecting the end of the p-n junction, a p-electrode, and an n-electrode. The passivation film is covered with a protective layer composed of an insulative resin and having a thickness larger than that of the passivation film such that the passivation film of the PD chip fixed to the Si wafer and hence the p-n junction are not damaged or contaminated when an Si wafer including a number of horizontally and vertically arranged chip units, each having a V-groove for fixing an optical fiber, a marker, and a metallized pattern, is diced. Thus, a low-cost optical receiver module that does not generate dark current can be produced.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: June 6, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naoyuki Yamabayashi, Yoshiki Kuhara
  • Patent number: 7049167
    Abstract: The method for manufacturing a test pattern for use in a CMOS image sensor is employed to measure a sheet resistivity of each ion implantation region, respectively.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: May 23, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won-Ho Lee
  • Patent number: 7041525
    Abstract: A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.
    Type: Grant
    Filed: January 2, 2004
    Date of Patent: May 9, 2006
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Louis L. Hsu, Carl J. Radens, Li-Kong Wang, Kwong Hon Wong
  • Patent number: 6864414
    Abstract: A solar cell having a multijunction solar cell structure with a bypass diode is disclosed. The bypass diode provides a reverse bias protection for the multijunction solar cell structure. In one embodiment, the multifunction solar cell structure includes a substrate, a bottom cell, a middle cell, a top cell, a bypass diode, a lateral conduction layer, and a shunt. The lateral conduction layer is deposited over the top cell. The bypass diode is deposited over the lateral conduction layer. One side of the shunt is connected to the substrate and another side of the shunt is connected to the lateral conduction layer. In another embodiment, the bypass diode contains an i-layer to enhance the diode performance.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: March 8, 2005
    Assignee: Emcore Corporation
    Inventors: Paul R. Sharps, Daniel J. Aiken, Doug Collins, Mark A. Stan
  • Patent number: 6815792
    Abstract: The present invention provides an epitaxially grown compound semiconductor film having a low density of crystal defects which are generated during the course of crystal growth of a compound semiconductor. The present invention also provides a compound semiconductor multi-layer structure including an n-type InP substrate, an n-type InP buffer layer, an undoped InGaAs light-absorbing layer, and an n-type InP cap layer, the layers being successively grown on the substrate through MOCVD. In the InGaAs layer, the compositional ratio of In/Ga is cyclically varied in a thickness direction (cyclic intervals: 80 nm) so as to fall within a range of ±2% with respect to a predetermined compositional ratio that establishes lattice matching between InGaAs and InP; specifically, within a range between 0.54/0.46 (i.e., In0.54Ga0.46As) and 0.52/0.48 (i.e., In0.52Ga0.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: November 9, 2004
    Assignee: Nippon Sheet Glass Company, Limited
    Inventors: Hisao Nagata, Yasunori Arima, Nobuyuki Komaba
  • Patent number: 6815347
    Abstract: The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applied. A photosensitive film 8 is formed on a metal film 7. Then, remaining portions 81, 82 and 83 are formed from the photosensitive film 8. Then, the metal film 7 is etched by using the remaining portions 81, 82 and 83 as masks. And then, a photosensitive film 9 and a reflective electrode film 10 are formed without removing the remaining portions 81, 82 and 83.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: November 9, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Naoki Sumi
  • Publication number: 20040207051
    Abstract: The invention provides a semiconductor device having a pn diode that includes a p-type SiGe layer and a n-type Si layer junctioned to the p-type SiGe layer. A built-in potential of the pn diode can be reduced, and thus obtaining a diode characteristics with lower impedance compared to the conventional scheme. Further, by forming a bridge-rectifier circuit with the pn diode or the like, alternating-current voltages can efficiently be converted into direct-current voltages. Accordingly, the invention provides a semiconductor device and method of manufacturing the same that can flow a larger electrical current in the forward direction of a diode by improving the voltage-current characteristics of the diode.
    Type: Application
    Filed: February 25, 2004
    Publication date: October 21, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Teruo Takizawa
  • Publication number: 20040099929
    Abstract: A semiconductor system (200), particularly a diode, having a p-n junction is proposed, that is formed as a chip having an edge area, which includes a first layer (2) of a first conductivity type and a second layer (1, 3) of a second conductivity type; the second layer (1, 3) including at least two sublayers (1, 3); both sublayers (1, 3) forming a p-n junction with the first layer (2); the p-n junction of the first layer (2) with the first sublayer (3) being provided exclusively in the interior of the chip, and the p-n junction between the first layer (2) and the second sublayer (1) being provided in the edge area of the chip; for each cross-section of the chip area parallel to the chip plane, the first sublayer (3) corresponding only to a part of such a cross-section.
    Type: Application
    Filed: December 23, 2003
    Publication date: May 27, 2004
    Inventor: Alfred Goerlach
  • Patent number: 6706550
    Abstract: The present invention relates to a pinned photodiode for an image sensor and a method for manufacturing the same; and, more particularly, to a pinned photodiode of an image sensor fabricated by CMOS processes and a manufacturing method thereof The pinned photodiode, according to an embodiment of the present invention, includes a semiconductor layer of a first conductivity type; and at least two first doping regions of a second conductivity type alternately formed in the semiconductor layer and connected to each other at edges thereof so that the first doping regions have the same potential, wherein a plurality of PN junctions is formed in the semiconductor layer and the PN junctions improves a capturing capacity of photoelectric charges generated in the photodiode.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: March 16, 2004
    Assignee: Hyundai Electronics Industries Co, Ltd.
    Inventors: Ju Il Lee, Myung Hwan Cha, Nan Yi Lee