Lateral Series Connected Array Patents (Class 438/80)
  • Patent number: 10090430
    Abstract: A high efficiency configuration for a solar cell module comprises solar cells conductively bonded to each other in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. The front surface metallization patterns on the solar cells may be configured to enable single step stencil printing, which is facilitated by the overlapping configuration of the solar cells in the super cells. A solar photovoltaic system may comprise two or more such high voltage solar cell modules electrically connected in parallel with each other and to an inverter. Solar cell cleaving tools and solar cell cleaving methods apply a vacuum between bottom surfaces of a solar cell wafer and a curved supporting surface to flex the solar cell wafer against the curved supporting surface and thereby cleave the solar cell wafer along one or more previously prepared scribe lines to provide a plurality of solar cells.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: October 2, 2018
    Assignee: SunPower Corporation
    Inventors: Ratson Morad, Gilad Almogy, Itai Suez, Jean Hummel, Nathan Beckett, Yafu Lin, John Gannon, Michael J. Starkey, Robert Stuart, Tamir Lance, Dan Maydan
  • Patent number: 9246040
    Abstract: A thin film solar cell module according to an embodiment of the invention includes a substrate, a plurality of solar cells each including a first electrode on the substrate, a second electrode on the first electrode, and a photoelectric conversion unit between the first electrode and the second electrode, a ribbon positioned on each of first and second outermost solar cells among the solar cells, and a conductive adhesive part positioned between the first outermost solar cell and the ribbon and between the second outermost solar cell and the ribbon. The conductive adhesive part positioned between the second electrode of the first outermost solar cell and the ribbon includes a first connector, which is electrically connected to the first electrode, the photoelectric conversion unit, and the second electrode of the first outermost solar cell.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: January 26, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Junoh Shin, Huijae Lee, Sungeun Lee, Jeonghun Son
  • Patent number: 9202947
    Abstract: A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Patent number: 9177972
    Abstract: An array substrate and a display device incorporating the array substrate are disclosed. The array substrate includes an alignment mark formed in a source-drain electrode layer, and a detection hole formed in a region in a pixel electrode layer and a passivation layer that corresponds to the alignment mark, such that normal detection of the alignment mark can be carried out by irradiating an electronic beam into the detection hole. The structure of the array substrate reduces the likelihood of detection failures.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 3, 2015
    Assignees: Boe Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventor: Zhenfei Cai
  • Patent number: 9147701
    Abstract: A single monolithic integrated circuit (10) containing a solar cell (or cells) with a DC-DC converter includes: a substrate (120, 220); the solar cell (101) or a solar cell array (100, 100?) on the substrate for generating an output voltage; and the DC-DC converter (102) integrated on the substrate for receiving the output voltage to generate a converted voltage, which may be higher or lower than the solar generated voltage. The substrate may be a silicon <111>, silicon carbide, or sapphire substrate. A GaN RF power amplifier and a CMOS controller including PWM modulator may also be monolithically integrated with an InGaN solar cell array and a GaN DC-DC converter. GaN switches (113, 115, 117, 119) may be used to couple InGaN solar cells (101) in series or parallel within the solar cell array (100, 100?) to yield improved or optimal voltage and current levels as required by the load.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 29, 2015
    Assignee: RAYTHEON COMPANY
    Inventor: Jeffrey H. Saunders
  • Patent number: 9147794
    Abstract: Thin film photovoltaic devices are generally provided having three terminals. In one embodiment, the thin film photovoltaic device can include a first submodule defined by a first plurality of photovoltaic cells between a first dead cell and a first terminal cell; a second submodule defined by a second plurality of photovoltaic cells between a second dead cell and a second terminal cell; and a joint bus bar electrically connected to the first dead cell and the second dead cell. The first dead cell is adjacent to the second dead cell, with the first dead cell being separated from the second dead cell via a separation scribe. Methods are also generally provided for forming a thin film photovoltaic device.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 29, 2015
    Assignee: First Solar, Inc.
    Inventors: Scott Daniel Feldman-Peabody, Luke W. Jacobson, Robert A. Garber, Fred Harper Seymour, Troy Alan Berens
  • Patent number: 9142706
    Abstract: A second semiconductor layer is formed to cover a first principle surface of a semiconductor substrate including a insulating layer formed on the first principle surface. A portion of the second semiconductor layer formed on the insulating layer is partially removed by etching using a first etchant whose etching rate is higher for the second semiconductor layer than for the insulating layer. A portion of the insulating layer is removed by etching, through the removed portion of the second semiconductor layer, using a second etchant whose etching rate for the insulating layer is higher than that for the second semiconductor layer, thereby exposing apart of the first semiconductor layer. Electrodes are formed on the exposed part of the first semiconductor layer and the second semiconductor layer, respectively.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: September 22, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Takahiro Mishima
  • Patent number: 9099588
    Abstract: A thin-film component comprising a film structure and an electrically conductive protection device is disclosed, together with a method for the production and use thereof.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: August 4, 2015
    Assignee: SAINT-GOBAIN GLASS FRANCE
    Inventors: Philippe Letocart, Dang Cuong Phan, Dana Pakosch, Jean-Christophe Giron, Pascal Remy
  • Patent number: 9093601
    Abstract: An object is to provide a photoelectric conversion device which has little loss of light absorption in a window layer and has high conversion efficiency. A photoelectric conversion device including a crystalline silicon substrate having n-type conductivity and a light-transmitting semiconductor layer having p-type conductivity between a pair of electrodes is formed. In the photoelectric conversion device, a p-n junction is formed between the crystalline silicon substrate and the light-transmitting semiconductor layer, and the light-transmitting semiconductor layer serves as a window layer. The light-transmitting semiconductor layer includes an organic compound and an inorganic compound. As the organic compound and the inorganic compound, a material having a high hole-transport property and a transition metal oxide having an electron-accepting property are respectively used.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: July 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Fumito Isaka, Jiro Nishida
  • Patent number: 9076860
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the mask to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing etch residue from sidewalls of the singulated integrated circuits.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: July 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Prabhat Kumar, James S. Papanu, Ajay Kumar, Brad Eaton
  • Patent number: 9041072
    Abstract: A pixel cell includes a photodiode, a storage transistor, a transfer transistor and an output transistor disposed in a semiconductor substrate. The transfer transistor selectively transfers image charge accumulated in the photodiode from the photodiode to the storage transistor. The output transistor selectively transfers the image charge from the storage transistor to a readout node. A first isolation fence is disposed over the semiconductor substrate separating a transfer gate of the transfer transistor from a storage gate of the storage transistor. A second isolation fence is disposed over the semiconductor substrate separating the storage gate from an output gate of the output transistor. Thicknesses of the first and second isolation fences are substantially equal to spacing distances between the transfer gate and the storage gate, and between the storage gate and the output gate, respectively.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 26, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai
  • Patent number: 9035408
    Abstract: A ramped etalon cavity structure and a method of fabricating same. A bi-layer stack is deposited on a substrate. The bi-layer stack includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch stop layer and a bulk layer. A three dimensional photoresist structure is formed by using gray-tone lithography. The three dimensional photoresist is plasma etched into the bi-layer stack, thereby generating an etched bi-layer stack. The etched bi-layer stack is chemically etched with a first chemical etchant to generate a multiple-step structure on the substrate, wherein the first chemical etchant stops at the etch stop layer.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: May 19, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Andrew J. Boudreau, Michael K. Yetzbacher, Marc Christophersen, Bernard F. Phlips
  • Publication number: 20150130009
    Abstract: To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 14, 2015
    Inventors: Katsumi EIKYU, Atsushi SAKAI, Hiroyuki ARIE
  • Patent number: 9029689
    Abstract: A method of connecting two solar cells is disclosed. In one embodiment, the method comprises gripping an interconnect with a head of positioning device, heating the interconnect with the head of the positioning device to between two predetermined temperatures, where one is higher than the other, positioning the interconnect so as to overlay two adjacent solar cells, coupling the interconnect to each of the two adjacent solar cells, and releasing the interconnect from the head.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: May 12, 2015
    Assignee: SunPower Corporation
    Inventors: Thomas Phu, Shashwat Kumaria, Briccio deLeon
  • Patent number: 9024288
    Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 5, 2015
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Tuo Sun
  • Publication number: 20150108509
    Abstract: The invention relates to a method for producing serially interconnected optoelectronic components as well as optoelectronic components interconnected according to the method. In a first step, an electrically non-conductive layer with optoelectronic material introduced therein and at least one first wire or thread (2) located in the layer is produced. The first wire or thread either is electrically conductive from the outset or can subsequently be treated in such a way that it becomes electrically conductive as a result of the treatment. A first and second electrooptically active region of the layer is electrically connected to the first wire or thread in such a way that they are electrically interconnected to each other in series. By the wire, regions of the layer are subdivided in a simple manner, as a result of which a plurality of optoelectronic components are produced in a technically simple manner. Continuous production is possible.
    Type: Application
    Filed: March 26, 2013
    Publication date: April 23, 2015
    Inventor: Dieter Meissner
  • Publication number: 20150107643
    Abstract: A photovoltaic module including first photovoltaic cells and second photovoltaic cells, electrically connected to each other and arranged adjacent to each other, in which a value of a short circuit current of each of the first photovoltaic cells is less than a value of a short circuit current of each of the second photovoltaic cells of the photovoltaic module, and the first photovoltaic cells are arranged at edges and/or ends of the photovoltaic module.
    Type: Application
    Filed: May 7, 2013
    Publication date: April 23, 2015
    Applicant: Commissariat a I'energie atomique et aux ene alt
    Inventors: Philippe Voarino, Paul Lefillastre
  • Publication number: 20150101649
    Abstract: An article of manufacture includes a first and second PV cell layer, where the first and second PV cell layers are at least partially displaced from each other and define a continuous optical coverage area throughout a solar active area. The article provides for enhanced utilization of the active solar area.
    Type: Application
    Filed: May 29, 2013
    Publication date: April 16, 2015
    Inventors: Hua Liu, Jie Feng, Leonardo Lopez, Rebekah Feist, Keith Kauffmann
  • Publication number: 20150096606
    Abstract: The present invention concerns a method for producing an intermediate product for obtaining a photovoltaic module comprising a plurality of solar cells, said method comprising the following steps: (a) localised deposition on a substrate (4) of a layer (7) of an Se or S material, so as to cover at least one portion (400) of the substrate, (b) deposition on this localised layer (7), of a layer (41) of conductive material, said layer coating the localised layer.
    Type: Application
    Filed: April 2, 2013
    Publication date: April 9, 2015
    Inventors: Nicolas Karst, Charles Roger
  • Publication number: 20150083182
    Abstract: The present invention relates to a dye-sensitized solar cell module (1) which comprises at least two dye-sensitized solar cell units (2a-c) arranged adjacent to each other and connected in series. The dye-sensitized solar cell module comprises a porous insulating substrate (7), the first conducting layer (4) is a porous conducting layer formed on one side of the porous insulating substrate, and the second conducting layer (5) is a porous conducting layer formed on the opposite side of the porous insulating substrate. A series connecting element (6) is penetrating through the porous insulating substrate and extending between the first conducting layer of one of the cell units and the second conducting layer of the adjacent cell unit, thereby electrically connecting the first conducting layer of one of the cell units with the second conducting layer of the adjacent cell unit. This invention also relates to a method for manufacturing the dye-sensitized solar cell module.
    Type: Application
    Filed: March 8, 2013
    Publication date: March 26, 2015
    Inventors: Henrik Lindström, Giovanni Fili
  • Publication number: 20150076648
    Abstract: Systems and methods are provided for fabricating a backside illuminated image sensor including an array of pixels. An example image sensor includes a first pixel, a second pixel, and an isolation structure. The first pixel is disposed in a front side of a substrate and is configured to generate charged carriers in response to light incident upon a backside of the substrate. The second pixel is disposed in the front side of the substrate and is configured to generate charged carriers in response to light incident upon the backside of the substrate. The isolation structure is disposed to separate the second pixel from the first pixel, and extends from the backside of the substrate toward the front side of the substrate. The isolation structure includes a sidewall substantially vertically to the front side of the substrate.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Inventor: SHIH-I YANG
  • Publication number: 20150075580
    Abstract: A method for producing an intermediate product for obtaining a photovoltaic module comprising a plurality of solar cells, said method comprising the following steps: (a) localised deposition on a substrate (4) of a layer of metal (8) so as to cover at least one portion (401) of the substrate, (b) deposition on this localised layer (8) of a layer (41) of conductive material, said layer coating the localised layer (8).
    Type: Application
    Filed: March 28, 2013
    Publication date: March 19, 2015
    Inventors: Nicolas Karst, Charles Roger
  • Publication number: 20150068578
    Abstract: A method for manufacturing photovoltaic thin-film solar modules, including: applying a back electrode layer to a substrate, applying at least one conductive barrier layer, applying at least one contact layer, applying at least one kesterite or chalcopyrite semiconductor absorber layer, applying at least one buffer layer, removing the applied layers with laser treatment with formation of first separating trenches, filling the first separating trenches using at least one insulating material, removing layers extending from the barrier layer in the direction of the semiconductor absorber layer with formation of second separating trenches, or chemical phase transformation or thermal decomposition of layers extending from the barrier layer in the direction of the semiconductor absorber layer with the formation of first linear conductive areas, applying at least one transparent front electrode layer with filling and contacting of the second separating trenches or with contacting of the first linear conductive areas,
    Type: Application
    Filed: February 15, 2013
    Publication date: March 12, 2015
    Applicant: Robert Bosch GmbH
    Inventor: Volker Probst
  • Publication number: 20150070556
    Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 12, 2015
    Inventors: Masahiro Joei, Kaori Takimoto
  • Patent number: 8940574
    Abstract: A method includes forming a plurality of image sensors on a front side of a semiconductor substrate, and forming a dielectric layer on a backside of the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The dielectric layer is patterned into a plurality of grid-filling regions, wherein each of the plurality of grid-filling regions overlaps one of the plurality of image sensors. A metal layer is formed on top surfaces and sidewalls of the plurality of grid-filling regions. The metal layer is etched to remove horizontal portions of the metal layer, wherein vertical portions of the metal layer remain after the step of etching to form a metal grid. A transparent material is filled into grid openings of the metal grid.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Wang, Chu-Wei Chang, Wang-Pen Mo, Hung-Chang Hsieh
  • Publication number: 20150020864
    Abstract: The invention relates to a method for manufacturing a photovoltaic module comprising a plurality of solar cells in a thin-layer structure, in which the following are consecutively formed: an electrode on the rear surface (41), a photovoltaic layer (46) obtained by depositing a layer (42) of precursors and by annealing such as to convert the precursors into a semiconductor material, and another semiconductor layer (43) in order to create a pn junction with the photovoltaic layer (46); characterised in that the layer (42) is deposited in a localised manner, such as to leave free at least one area (410) of the electrode on the rear surface (41) placed between two adjacent cells, wherein the annealing step modifies said area (410) which has higher resistivity than the rest of the electrode on the rear surface (41), such as to provide electric insulation between two adjacent cells.
    Type: Application
    Filed: January 9, 2013
    Publication date: January 22, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Joël Dufourcq, Sévak Amtablian, Nicolas Karst, Frédéric Roux
  • Publication number: 20150020868
    Abstract: A thin-film solar cell includes a substrate, a back surface electrode layer, a light-absorbing layer, and a transparent electrode layer, layered on the substrate, in this order. The layers are divided into multiple unit cells by a scribed groove, and the cells serially connected. At an inside of an end side of the solar cell perpendicular to the scribed groove, a groove is formed perpendicular to the scribed groove and has the back surface electrode is removed therefrom. The thin-film solar cell is produced by emitting a laser beam on the solar cell element of an end part of a side perpendicular to the scribed groove so as to form a new end surface by removing the back surface electrode layer, the light-absorbing layer and the transparent electrode layer, and mechanically forming the perpendicular groove perpendicular to the scribed groove, at inside of the new end surface.
    Type: Application
    Filed: January 23, 2013
    Publication date: January 22, 2015
    Inventors: Satoshi Oyama, Tomoyuki Kume
  • Publication number: 20150007866
    Abstract: The invention relates to a method for manufacturing a photovoltaic module comprising plurality of solar cells in a thin-layer structure, in which the following are formed consecutively in the structure: an electrode on the rear surface (41), a photovoltaic layer (43) obtained by depositing components including metal precursors and at least one element taken from Se and S and by annealing such as to convert said components into a semiconductor material, and another semiconductor layer (44) in order to create a pn junction with the photovoltaic layer (43); characterised in that the metal precursors form, on the electrode on the rear surface (41), a continuous layer, while said at least one element forms a layer having at least one break making it possible, at the end of the annealing step, to leave an area (430) of the layer of metal precursors in the metal state at said break.
    Type: Application
    Filed: January 9, 2013
    Publication date: January 8, 2015
    Inventors: Nicolas Karst, Sévak Amtablian, Simon Perraud
  • Patent number: 8927322
    Abstract: The present disclosure is directed to methods of forming different types of Cu2ZnSnS4 (CZTS) solar cells and Copper Indium Gallium DiSelenide (CIGS) solar cells that can be combinatorially varied and evaluated. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: January 6, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Upendra Avachat, Tony Chiang, Craig Hunter, Jian Li, Guizhen Zhang
  • Publication number: 20140367817
    Abstract: The present invention reduces color mixture (cross talk) and the degradation of sensitivity in a peripheral region of a pixel area to achieve a reduction of sensitivity irregularity in the pixel area. A solid-state imaging apparatus having a pixel area including a plurality of photoelectric conversion elements includes: a semiconductor substrate in which the plurality of photoelectric conversion elements are formed; a plurality of air gap formed layers which are arranged above the semiconductor substrate, and correspond to the photoelectric conversion elements in the plurality of photoelectric conversion elements, respectively; and air gaps arranged between the air gap formed layers in the plurality of air gap formed layers, respectively, wherein the air gap in a peripheral region B of the pixel area has a width larger than the air gap in a central region A of the pixel area.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 18, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Mariko Furuta
  • Patent number: 8912616
    Abstract: A photodiode device including a photosensitive diffusion junction within a single layer. The photodiode device further includes a resonant grating located within the single layer. The photosensitive diffusion junction is located within the resonant grating.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporaion
    Inventors: Matthias Fertig, Thomas Morf, Nkolaj Moll, Martin Kreissig, Karl-Heinz Brenner, Maximilian Auer
  • Publication number: 20140352777
    Abstract: A method for forming photovoltaic cells comprises providing a first roll of a photovoltaic material and a second roll of an expanded metallic mesh. The photovoltaic material comprises a photoactive material adjacent to a flexible substrate, and the expanded metallic mesh comprises a plurality of openings. Next, an electrically insulating material is provided adjacent to an edge portion of the photovoltaic material. The photovoltaic material from the first roll can then be brought in proximity to the expanded mesh from the second roll to form a nascent photovoltaic cell. The electrically insulating material can be disposed between the expanded metallic mesh and the photovoltaic material. Next, the nascent photovoltaic cell is cut into individual sections to form a plurality of photovoltaic cells.
    Type: Application
    Filed: December 6, 2012
    Publication date: December 4, 2014
    Inventors: Bruce D. Hachtmann, Christine Tsai, Thomas M. Valeri, Herb Delarosa
  • Patent number: 8900891
    Abstract: A method for manufacturing interdigitated back contact photovoltaic cells is disclosed. In one aspect, the method includes providing on a rear surface of a substrate a first doped layer of a first dopant type, and providing a dielectric masking layer overlaying it. Grooves are formed through the dielectric masking layer and first doped layer, extending into the substrate in a direction substantially orthogonal to the rear surface and extending in a lateral direction underneath the first doped layer at sides of the grooves. Directional doping is performed in a direction substantially orthogonal to the rear surface, thereby providing doped regions with dopants of a second dopant type at a bottom of the grooves. Dopant diffusion is performed to form at the rear side of the substrate one of the emitter regions and back surface field regions between the grooves and the other at the bottom of the grooves.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: December 2, 2014
    Assignee: IMEC
    Inventors: Bartlomiej Jan Pawlak, Tom Janssens
  • Publication number: 20140345668
    Abstract: Disclosed are a solar cell module and a method of fabricating the same. The solar cell module according to the embodiment includes first solar cells including a first P-type semiconductor layer, a first buffer layer, and a first N-type semiconductor layer sequentially disposed on a support substrate; second solar cells including a second N-type semiconductor layer, a second buffer layer, and a second N-type semiconductor layer sequentially disposed on the support substrate; and a connecting electrode connecting the first solar cells to the second solar cells.
    Type: Application
    Filed: December 10, 2012
    Publication date: November 27, 2014
    Inventor: Suk Jae Jee
  • Patent number: 8894888
    Abstract: A conductive paste composition contains a source of an electrically conductive metal, a fusible material, a synthetic clay additive, and an optional etchant additive, dispersed in an organic medium. An article such as a photovoltaic cell is formed by a process having the steps of deposition of the paste composition on a semiconductor substrate by a process such as screen printing and firing the paste to remove the organic medium and sinter the metal and fusible material. The synthetic clay additive aids in establishing a low resistance electrical contact between the front side metallization and underlying semiconductor substrate during firing.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: November 25, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Steven Dale Ittel, John Graeme Pepin
  • Publication number: 20140332050
    Abstract: A solar cell string having a plurality of solar cells disposed in a row includes contact elements for electrically connecting the solar cells. The contact elements have cup-shaped indentations, created through deep-drawing or stamping, that establish contact with the solar cells through holes in insulating strips applied to the solar cells.
    Type: Application
    Filed: April 22, 2014
    Publication date: November 13, 2014
    Inventors: Stefan Kaufmann, Adolf Hofer
  • Publication number: 20140327099
    Abstract: A ramped etalon cavity structure and a method of fabricating same. A bi-layer stack is deposited on a substrate. The bi-layer stack includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch stop layer and a bulk layer. A three dimensional photoresist structure is formed by using gray-tone lithography. The three dimensional photoresist is plasma etched into the bi-layer stack, thereby generating an etched bi-layer stack. The etched bi-layer stack is chemically etched with a first chemical etchant to generate a multiple-step structure on the substrate, wherein the first chemical etchant stops at the etch stop layer.
    Type: Application
    Filed: May 5, 2014
    Publication date: November 6, 2014
    Inventors: Andrew J. Boudreau, Michael K. Yetzbacher, Marc Christophersen, Bernard F. Phlips
  • Patent number: 8877541
    Abstract: Nanostructures and photovoltaic structures are disclosed. A nanostructure according to one embodiment includes an array of nanocables extending from a substrate, the nanocables in the array being characterized as having a spacing and surface texture defined by inner surfaces of voids of a template; an electrically insulating layer extending along the substrate; and at least one layer overlaying the nanocables. A nanostructure according to another embodiment includes a substrate; a portion of a template extending along the substrate, the template being electrically insulative; an array of nanocables extending from the template, portions of the nanocables protruding from the template being characterized as having a spacing, shape, and surface texture defined by previously-present inner surface of voids of the template; and at least one layer overlaying the nanocables.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 4, 2014
    Assignees: Q1 Nanosystems, Inc., The Regents of the University of California
    Inventors: Brian Argo, Ruxandra Vidu, Pieter Stroeve, John Argo, Jie-Ren Ku
  • Publication number: 20140307850
    Abstract: The present invention relates to a detector tile, a detector panel arrangement, an X-ray detector, an X-ray imaging system, and a method for providing a detector tile for a seamless detector surface with a continuous pixel array. In order to build a large area detector with reduced gap appearance, a detector tile (30) is provided having a flat primary substrate (32) and a surface layer (34) with a circuitry arrangement (36). The surface layer is arranged on a front side (38) of the primary substrate covering the primary substrate. The circuitry arrangement comprises a number of detector pixels (40) providing a pixel array (42), wherein at least one connection opening (44) is provided in the surface layer and the flat primary substrate at least at one edge of the detector tile, which connection opening is leading from the surface layer to the rear of the substrate for guiding electrical connection elements between the front side and the rear of the detector tiles.
    Type: Application
    Filed: November 6, 2012
    Publication date: October 16, 2014
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Tiemen Poorter, Ronald Dekker, Vincent Adrianus Henneken, Nicolaas Johannes Anthonius Van Veen
  • Publication number: 20140291793
    Abstract: There is provided a solid-state imaging apparatus including a plurality of photoelectric conversion regions which photoelectrically convert light incident from a rear surface side of a semiconductor substrate, element isolation regions formed between the plurality of photoelectric conversion regions arranged in a matrix shape, and shielding members formed on upper surfaces of the element isolation regions. The element isolation regions have high impurity concentration regions of a high impurity concentration connected to at least a part of the shielding members.
    Type: Application
    Filed: March 21, 2014
    Publication date: October 2, 2014
    Applicant: SONY CORPORATION
    Inventor: Yusuke Tanaka
  • Publication number: 20140261618
    Abstract: The present invention relates to multi-cell devices fabricated on a common substrate that are more desirable than single cell devices, particularly in photovoltaic applications. Multi-cell devices operate with lower currents, higher output voltages, and lower internal power losses. Prior art multi-cell devices use physical isolation to achieve electrical isolation between cells. In order to fabricate a multicell device on a common substrate, the individual cells must be electrically isolated from one another. In the prior art, isolation generally required creating a physical dielectric barrier between the cells, which adds complexity and cost to the fabrication process. The disclosed invention achieves electrical isolation without physical isolation by proper orientation of interdigitated junctions such that the diffusion fields present in the interdigitated region essentially prevent the formation of a significant parasitic current which would be in opposition to the output of the device.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: MTPV Power Corporation
    Inventors: Eric Brown, Andrew Walsh, Jose Borrego, Paul Greiff
  • Publication number: 20140264706
    Abstract: A solid state imaging device including: a plurality of sensor sections formed in a semiconductor substrate in order to convert incident light into an electric signal; a peripheral circuit section formed in the semiconductor substrate so as to be positioned beside the sensor sections; and a layer having negative fixed electric charges that is formed on a light incidence side of the sensor sections in order to form a hole accumulation layer on light receiving surfaces of the sensor sections.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 18, 2014
    Applicant: Sony Corporation
    Inventor: Yuko Ohgishi
  • Publication number: 20140273332
    Abstract: Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P? epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicants: Yissum Research Development Company of the Hebrew University of Jerusalem Ltd., Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Evgeny Pikhay, Irit Chen-Zamero, Ora Eli, Micha Asscher, Amir Saar
  • Patent number: 8835211
    Abstract: A pixel cell includes a photodiode, a storage transistor, a transfer transistor and an output transistor disposed in a semiconductor substrate. The transfer transistor selectively transfers image charge accumulated in the photodiode from the photodiode to the storage transistor. The output transistor selectively transfers the image charge from the storage transistor to a readout node. A first isolation fence is disposed over the semiconductor substrate separating a transfer gate of the transfer transistor from a storage gate of the storage transistor. A second isolation fence is disposed over the semiconductor substrate separating the storage gate from an output gate of the output transistor. Thicknesses of the first and second isolation fences are substantially equal to spacing distances between the transfer gate and the storage gate, and between the storage gate and the output gate, respectively.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: September 16, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai
  • Patent number: 8828781
    Abstract: Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P? epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 9, 2014
    Assignees: Tower Semiconductor Ltd., Yissum Research Development Company of the Hebrew University of Jerusalem Ltd.
    Inventors: Yakov Roizin, Evgeny Pikhay, Irit Chen-Zamero, Ora Eli, Micha Asscher, Amir Saar
  • Publication number: 20140246070
    Abstract: A thin film solar module having a series connection is described. The thin film solar module has a back electrode layer that is divided into regions by a first set of structuring lines, a photoactive semiconductor layer that is arranged on the back electrode layer and divided by a second set of structuring lines, and a front electrode layer that is arranged on the side of the photoactive semiconductor layer opposite the back electrode layer and divided into regions by a third set of structuring lines.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 4, 2014
    Inventor: Franz Karg
  • Patent number: 8822255
    Abstract: A method of manufacturing a solar cell, which includes an edge deletion step using a laser beam, and a manufacturing apparatus which is used in such a method, the method and the apparatus being capable of preventing a shunt and cracks from being generated are provided. By radiating a first laser beam to a multilayer body, which includes a transparent electrode layer, a photoelectric conversion layer, and a back electrode layer sequentially formed on a transparent substrate, from a side of the transparent substrate, the photoelectric conversion layer and the back electrode layer in a first region are removed, and by radiating a second laser beam into the region such that the second laser beam is spaced from a peripheral rim of the region, the transparent electrode layer in a second region is removed.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: September 2, 2014
    Assignee: Ulvac, Inc.
    Inventors: Yoshiaki Yamamoto, Hitoshi Ikeda, Tomoki Ohnishi, Kouichi Tamagawa
  • Patent number: 8822813
    Abstract: An improved submicron gap thermophotovoltaic structure and method comprising an emitter substrate with a first surface for receiving heat energy and a second surface for emitting infrared radiation across an evacuated submicron gap to a juxtaposed first surface of an infrared radiation-transparent window substrate having a high refractive index. A second surface of the infrared radiation-transparent substrate opposite the first surface is affixed to a photovoltaic cell substrate by an infrared-transparent compliant adhesive layer. Relying on the high refractive index of the infrared radiation-transparent window substrate, the low refractive index of the submicron gap and Snell's law, the infrared radiation received by the first surface of the infrared radiation-transparent window substrate is focused onto a more perpendicular path to the surface of the photovoltaic cell substrate. This results in increased electrical power output and improved efficiency by the thermophotovoltaic structure.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 2, 2014
    Assignee: MTPV Power Corporation
    Inventors: Paul Greiff, Robert Dimatteo, Eric Brown, Christopher Leitz
  • Publication number: 20140231950
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first circuit substrate having a first interconnection; forming a second circuit substrate having a second interconnection; bonding the first circuit substrate to the top surface of the second circuit substrate so as to be stacked facing each other; and performing an etching process of simultaneously removing parts formed on the first interconnection and the second interconnection in a stacked body of the first circuit substrate and the second circuit substrate so as to form a first opening in the top surface of the first interconnection and to form a second opening in the top surface of the second interconnection. The forming of the first circuit substrate includes forming an etching stopper layer on the surface of the first interconnection out of a material having an etching rate lower than that of the first interconnection in the etching process.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 21, 2014
    Applicant: Sony Corporation
    Inventor: Ikue Mitsuhashi
  • Patent number: 8809109
    Abstract: A method for manufacturing a thin-film photovoltaic device includes providing a glass substrate contained sodium species. The glass substrate comprising a surface region and a peripheral edge region surround the surface region. The method further includes forming a barrier material overlying the surface region and partially overlying the peripheral edge region and forming a conductor material overlying the barrier material. Additionally, the method includes forming at least a first trench in a vicinity of the peripheral edge region to remove substantially the conductor material therein and forming precursor materials overlying the patterned conductor material. Furthermore, the method includes thermally treating the precursor materials to transform the precursor materials into a film of photovoltaic absorber. The first trench is configured to maintain the film of photovoltaic absorber substantially free from peeling off the conductor material.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 19, 2014
    Assignee: Stion Corporation
    Inventors: Laila Dounas, Robert D. Wieting, Chester A. Farris, III