Graded Composition Patents (Class 438/87)
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Publication number: 20100184251Abstract: A plasma inside vapor deposition apparatus for making silicon thin film solar cell modules including means for supporting a substrate, the substrate having an outer surface and an inner surface; plasma torch means located proximal to the inner surface for depositing at least one thin film layer on the inner surface of the substrate, the plasma torch means located a distance from the substrate; and means for supplying reagent chemicals to the plasma torch means, wherein the at least one thin film layer form the silicon thin film solar cell modules.Type: ApplicationFiled: January 29, 2010Publication date: July 22, 2010Inventors: Mohd A. Aslami, Dau Wu
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Publication number: 20100176423Abstract: A floating diffusion (331) is created substantially at center of the light-receiving surface of an embedded photodiode (31), with a gate electrode of a transfer transistor (32) surrounding the floating diffusion. The concentration (or depth) of impurities in a p+-type semiconductor region, n-type semiconductor region or p-well region is changed in an inclined form so that a potential gradient being inclined downwards from the circumference to the center is created when an appropriate bias voltage is applied to the pn junction. The photocharges produced by incident light are rapidly moved along the potential gradient toward the center. Even in the case where the photocharge storage time is short, the photocharges can be efficiently collected since the maximum moving distance from the circumference of the photodiode (31) to the floating diffusion (331). Thus, the photocharges produced by the photodiode (31) are efficiently utilized, whereby the detection sensitivity is improved.Type: ApplicationFiled: September 4, 2008Publication date: July 15, 2010Applicants: TOHOKU UNIVERSITY, SHIMADZU CORPORATIONInventors: Shigetoshi Sugawa, Yasushi Kondo, Hideki Tominaga
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Publication number: 20100177231Abstract: A solid-state image capturing apparatus is manufactured, which has a high sensitivity and high resolution with no color filter or no on-chip microlens required and with no shading generated or no variance in performance between pixel sections. In a solid-state image capturing apparatus 1, a plurality of pixel sections 2 (solid-state image capturing devices), each having light receiving sections 21 to 23 laminated in a depth direction of a semiconductor substrate 3, is repeatedly arranged according to a sequence in a direction along a plane of the semiconductor substrate 3. For incident light, electromagnetic waves having wavelength bands corresponding to the depths of the respective light receiving sections 21 to 23 are detected at the light receiving sections 21 to 23 in accordance with the wavelength dependency of optical absorption coefficient of semiconductor substrate material, and signal charges are generated.Type: ApplicationFiled: November 21, 2007Publication date: July 15, 2010Applicant: SHARP KABUSHIKI KAISHAInventor: Takahiro Tsuchida
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Publication number: 20100170565Abstract: A photovoltaic device having improved conversion efficiency as a result of an increase in the open-circuit voltage is provided. The photovoltaic device comprises a photovoltaic layer having a stacked p-layer, i-layer and n-layer, wherein the p-layer is a nitrogen-containing layer comprising nitrogen atoms at an atomic concentration of not less than 1% and not more than 25%, and the crystallization ratio of the p-layer is not less than 0 but less than 3. Alternatively, the n-layer may be a nitrogen-containing layer comprising nitrogen atoms at an atomic concentration of not less than 1% and not more than 20%, wherein the crystallization ratio of the n-layer is not less than 0 but less than 3. Alternatively, an interface layer may be formed at the interface between the p-layer and the i-layer, wherein the interface layer is a nitrogen-containing layer comprising nitrogen atoms at an atomic concentration of not less than 1% and not more than 30%.Type: ApplicationFiled: December 5, 2008Publication date: July 8, 2010Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Shigenori Tsuruga, Kengo Yamaguchi, Saneyuki Goya, Satoshi Sakai
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Publication number: 20100163942Abstract: A method for manufacturing a CMOS image sensor includes: preparing a semiconductor substrate incorporating therein a p-type epitaxial layer by epitaxially growing up an upper portion of the semiconductor substrate; forming a pixel array in one predetermined location of the semiconductor substrate, the pixel array having a plurality of transistors and a photodiode therein, wherein each transistor employs a gate insulator with a thickness ranging from 40 ? to 90 ?; and forming a logic circuit in the other predetermined location of the semiconductor substrate, the logic circuit having at least one transistor, wherein the transistor employs a gate insulator with a thickness ranging from 5 ? to 40 ?.Type: ApplicationFiled: March 12, 2010Publication date: July 1, 2010Inventor: Ju-Il Lee
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Publication number: 20100155867Abstract: A semiconductor device (1) includes a plurality of photodiodes (20) on a semiconductor substrate (11). Cathodes (22) and a common anode (21) of the plurality of photodiodes (20 (20a, 20b)) are formed so as to be electrically independent from the semiconductor substrate (11), the plurality of photodiodes (20) have the common anode (21) and the plurality of separate cathodes (22), and an output of the common anode (21) is considered to be equivalent to a sum of outputs of the plurality of separate photodiodes (20). Alternatively, the plurality of photodiodes have a common cathode and a plurality of separate anodes, and an output of the common cathode is considered to be equivalent to a sum of outputs of a plurality of separate photodiodes. By completely electrically isolating the anode and the cathode of the photodiodes from the substrate, the noise characteristic can be reduced, and crosstalk can be reduced.Type: ApplicationFiled: August 10, 2006Publication date: June 24, 2010Applicant: SONY CORPORATIONInventor: Chihiro Arai
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Publication number: 20100154870Abstract: An improved, lower cost method of processing substrates, such as to create solar cells is disclosed. The doped regions are created on the substrate, using a mask or without the use of lithography or masks. After the implantation is complete, visual recognition is used to determine the exact region that was implanted. This information can then be used by subsequent process steps to maintain this alignment. This information can also be fed back to the ion implantation equipment to modify the implant parameters. These techniques can also be used in other ion implanter applications.Type: ApplicationFiled: June 18, 2009Publication date: June 24, 2010Inventors: Nicholas Bateman, Paul Murphy
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Semiconductor device provided with photodiode, manufacturing method thereof, and optical disc device
Publication number: 20100155875Abstract: A semiconductor device includes: a P-type semiconductor substrate; a first P-type semiconductor layer formed on the P-type semiconductor substrate; a second P-type semiconductor layer formed on the first P-type semiconductor layer and having a lower P-type impurity concentration than the first P-type semiconductor layer; an N-type semiconductor layer, which will form a cathode region, formed on the second P-type semiconductor layer; a first P-type diffusion layer formed by diffusing a P-type impurity in a partial region of the second P-type semiconductor layer; a second P-type diffusion layer formed by diffusing a P-type impurity in the second P-type semiconductor layer so as to be present adjacently beneath the first P-type diffusion layer at a lower P-type impurity concentration than the first P-type diffusion layer; and a photodiode formed in such a manner that the N-type semiconductor layer and the first P-type diffusion layer are isolated from each other.Type: ApplicationFiled: November 30, 2009Publication date: June 24, 2010Applicant: Sony CorporationInventors: Hiroshi Yumoto, Shuji Yoneda, Tomokazu Mukai, Katsuhiko Takeuchi -
Publication number: 20100154874Abstract: The oxidation of a lower electrode by the reaction between a metal element in the lower electrode and oxygen in a bonding layer is suppressed. The contamination of a semiconductor layer that is a photoelectric conversion layer by the diffusion of the metal element in the lower electrode into the semiconductor layer is suppressed.Type: ApplicationFiled: September 23, 2009Publication date: June 24, 2010Inventors: Takashi HIROSE, Riho KATAISHI, Akihisa SHIMOMURA
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Patent number: 7741146Abstract: A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; attaching a surrogate second substrate over the third solar subcell and removing the first substrate; and etching a first trough around the periphery of the solar cell to the surrogate second substrate so as to form a mesa structure on the surrogate second substrate and facilitate the removal of said soType: GrantFiled: August 12, 2008Date of Patent: June 22, 2010Assignee: Emcore Solar Power, Inc.Inventors: Arthur Cornfeld, Tansen Varghese, Jacqueline Diaz
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Publication number: 20100148297Abstract: There is provided a semiconductor substrate for solid-state image sensing device in which the production cost is lower than that of a gettering method through a carbon ion implantation and problems such as occurrence of particles at a device production step and the like are solved. Silicon substrate contains solid-soluted carbon having a concentration of 1×1016-1×1017 atoms/cm3 and solid-soluted oxygen having a concentration of 1.4×1018-1.6×1018 atoms/cm3.Type: ApplicationFiled: September 7, 2007Publication date: June 17, 2010Applicant: SUMCO CORPORATIONInventor: Kazunari Kurita
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Publication number: 20100147366Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap; a middle second solar subcell adjacent to the first solar subcell and having a second band gap smaller than the first band gap, and having a base layer and an emitter layer, a graded interlayer adjacent to the second solar subcell; the graded interlayer having a third band gap greater than said second band gap; a third solar subcell adjacent to the interlayer, the third subcell having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and a distributed Bragg reflector (DBR) adjacent the second or third subcell.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: Emcore Solar Power, Inc.Inventors: Mark A. Stan, Arthur Cornfeld
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Publication number: 20100126570Abstract: Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. In one embodiment of a photovoltaic (PV) device, the PV device generally includes an n-doped layer and a p+-doped layer adjacent to the n-doped layer to form a p-n layer such that electric energy is created when electromagnetic radiation is absorbed by the p-n layer. The n-doped layer and the p+-doped layer may compose an absorber layer having a thickness less than 500 nm. Such a thin absorber layer may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.Type: ApplicationFiled: October 23, 2009Publication date: May 27, 2010Inventors: Isik C. Kizilyalli, Melissa Archer, Harry Atwater, Thomas J. Gmitter, Gang He, Andreas Hegedus, Gregg Higashi
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Patent number: 7723215Abstract: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The device includes an insulator layer; a semiconductor substrate, having an interface with the insulator layer; an epitaxial layer grown on the semiconductor substrate by epitaxial growth; and one or more imaging components in the epitaxial layer in proximity to a face of the epitaxial layer, the face being opposite the interface of the semiconductor substrate and the insulator layer, the imaging components comprising junctions within the epitaxial layer; wherein the semiconductor substrate and the epitaxial layer exhibit a net doping concentration having a maximum value at a predetermined distance from the interface of the insulating layer and the semiconductor substrate and which decreases monotonically on both sides of the profile from the maximum value within a portion of the semiconductor substrate and the epitaxial layer.Type: GrantFiled: May 23, 2007Date of Patent: May 25, 2010Assignee: Sarnoff CorporationInventors: Peter Alan Levine, Pradyumna Swain, Mahalingam Bhaskaran
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Publication number: 20100108130Abstract: A design and manufacturing method for an interdigitated backside contact photovoltaic (PV) solar cell less than 100 ?m thick are disclosed. A porous silicon layer is formed on a wafer substrate. Portions of the PV cell are then formed using diffusion, epitaxy and autodoping from the substrate. All backside processing of the solar cell (junctions, passivation layer, metal contacts to the N+ and P+ regions) is performed while the thin epitaxial layer is attached to the porous layer and substrate. After backside processing, the wafer is clamped and exfoliated. The front of the PV cell is completed from the region of the wafer near the exfoliation fracture layer, with subsequent removal of the porous layer, texturing, passivation and deposition of an antireflective coating. During manufacturing, the cell is always supported by either the bulk wafer or a wafer chuck, with no processing of bare thin PV cells.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Applicant: Crystal Solar, Inc.Inventor: Kramadhati V. Ravi
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Publication number: 20100096010Abstract: A new solar cell structure called a heterojunction barrier solar cell is described. As with previously reported quantum-well and quantum-dot solar cell structures, a layer of narrow band-gap material, such as GaAs or indium-rich InGaP, is inserted into the depletion region of a wide band-gap PN junction. Rather than being thin, however, the layer of narrow band-gap material is about 400-430 nm wide and forms a single, ultrawide well in the depletion region. Thin (e.g., 20-50 nm), wide band-gap InGaP barrier layers in the depletion region reduce the diode dark current. Engineering the electric field and barrier profile of the absorber layer, barrier layer, and p-type layer of the PN junction maximizes photogenerated carrier escape. This new twist on nanostructured solar cell design allows the separate optimization of current and voltage to maximize conversion efficiency.Type: ApplicationFiled: October 15, 2009Publication date: April 22, 2010Applicant: Kopin CorporationInventor: Roger E. Welser
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Patent number: 7691663Abstract: A method for manufacturing a CMOS image sensor includes: preparing a semiconductor substrate incorporating therein a p-type epitaxial layer by epitaxially growing up an upper portion of the semiconductor substrate; forming a pixel array in one predetermined location of the semiconductor substrate, the pixel array having a plurality of transistors and a photodiode therein, wherein each transistor employs a gate insulator with a thickness ranging from 40 ? to 90 ?; and forming a logic circuit in the other predetermined location of the semiconductor substrate, the logic circuit having at least one transistor, wherein the transistor employs a gate insulator with a thickness ranging from 5 ? to 40 ?.Type: GrantFiled: January 24, 2007Date of Patent: April 6, 2010Inventor: Ju-Il Lee
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Publication number: 20100072567Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes an isolation trench formed in a semiconductor substrate corresponding to a logic region and a pixel separating trench formed on the semiconductor substrate corresponding to a pixel region and having a depth shallower than a depth of the isolation trench of the logic region, a barrier region formed below the pixel separating trench, a pixel separator formed inside the pixel separating trench, a gate formed above the semiconductor substrate, a first doped region formed at a deep region of the semiconductor substrate corresponding to one side of the gate, an additionally-doped region interposed between the first doped region and the barrier region, and a second doped region formed at a shallow region of the semiconductor substrate such that the second doped region makes contact with the first doped region.Type: ApplicationFiled: September 22, 2009Publication date: March 25, 2010Inventor: SUN JAE HWANG
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Publication number: 20100047957Abstract: A method and apparatus for solar cell having graded energy wells is provided. The active region of the solar cell comprises nanostructures. The nanostructures are formed from a material that comprises a III-V compound semiconductor and an element that alters the band gap of the III-V compound semiconductor. For example, the III-V compound semiconductor could be gallium nitride (GaN). As an example, the “band gap altering element” could be indium (In). The concentration of the indium in the active region is non-uniform such that the active region has a number of energy wells, separated by barriers. The energy wells may be “graded”, by which it is meant that the energy wells have a different band gap from one another, generally increasing or decreasing from one well to another monotonically.Type: ApplicationFiled: November 3, 2009Publication date: February 25, 2010Inventors: James C. Kim, Sungsoo Yi
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Publication number: 20100012175Abstract: A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10?4 ohms-cm2.Type: ApplicationFiled: July 16, 2008Publication date: January 21, 2010Applicant: Emcore Solar Power, Inc.Inventors: Tansen Varghese, Arthur Cornfeld
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Publication number: 20100012174Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact layer over the third subcell having a fifth band gap greater than at least the magnitude of the second band gap.Type: ApplicationFiled: July 16, 2008Publication date: January 21, 2010Applicant: Emcore CorporationInventors: Tansen Varghese, Mark A. Stan, Arthur Cornfeld, Fred Newman, Allen A. Gray
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Patent number: 7648853Abstract: Dual channel heterostructures comprising strained Si and strained Ge-containing layers are disclosed, along with methods for producing such structures. In preferred embodiments, a strain-relaxed buffer layer is deposited on a carrier substrate, a strained Si layer is deposited over the strain-relaxed buffer layer and a strained Ge-containing layer is deposited over the strained Si layer. The structure can be transferred to a host substrate to produce the strained Si layer over the strained Ge-containing layer. By depositing the Si layer first, the process avoids Ge agglomeration problems.Type: GrantFiled: July 11, 2006Date of Patent: January 19, 2010Assignee: ASM America, Inc.Inventor: Matthias Bauer
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Publication number: 20090308438Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. An interrupted trench structure separates the P-type doped region from the N-type doped region in some locations but allows the P-type doped region and the N-type doped region to touch in other locations. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. Among other advantages, the resulting solar cell structure allows for increased efficiency while having a relatively low reverse breakdown voltage.Type: ApplicationFiled: February 25, 2009Publication date: December 17, 2009Inventors: Denis DE CEUSTER, Peter John COUSINS, David D. SMITH
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Publication number: 20090288703Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell, the method including: providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap and including a pseudomorphic window layer; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second solar subcell.Type: ApplicationFiled: May 20, 2008Publication date: November 26, 2009Applicant: Emcore CorporationInventors: Mark A. Stan, Arthur Cornfeld, Benjamin Cho
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Patent number: 7618839Abstract: An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface of a substrate and a graded pinned surface layer, self-aligned to a gate stack is provided. These photodiodes exhibit reduced image lag, transfer gate leakage, and photodiode dark current generation.Type: GrantFiled: April 7, 2008Date of Patent: November 17, 2009Assignee: Aptina Imaging CorporationInventor: Howard E. Rhodes
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Patent number: 7608835Abstract: The present invention relates to a radiation image converting panel that effectively prevents deterioration in fluorescence lifetime by a simpler structure. The radiation image converting panel comprises a support body, and a radiation converting film formed on the support body. The radiation converting film is formed on a film forming region which exists within a first main surface of the support body and includes at least a gravity center position of the first main surface. The radiation converting film is doped with Eu, and an Eu concentration distribution has a concentration gradient so as to become higher in the periphery than in the vicinity of the center of the radiation convert film. By thus providing a concentration gradient for the concentration of Eu to be doped, a drop in luminance in the periphery of the radiation converting film can be reduced.Type: GrantFiled: December 10, 2008Date of Patent: October 27, 2009Assignee: Hamamatsu Photonics K.K.Inventors: Jun Sakurai, Ichinobu Shimizu, Gouji Kamimura
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Publication number: 20090257703Abstract: An optical device includes at least two materials forming a structure with a graded bandgap where photocarriers are generated. A first of the at least two materials has a larger concentration at opposed ends of the graded bandgap structure than a concentration of the first of the at least two materials at an interior region of the graded bandgap structure. The second of the at least two materials has a larger concentration at the interior region of the graded bandgap structure than the concentration of the second of the at least two materials at the opposed ends of the graded bandgap structure.Type: ApplicationFiled: October 31, 2008Publication date: October 15, 2009Inventors: Alexandre Bratkovski, Theodore I. Kamins, David Fattal, Raymond Beausoleil
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Patent number: 7601558Abstract: A method of reactively sputtering from a metallic zinc target a transparent conductive oxide electrode of zinc oxide from a metallic zinc in a silicon photo diode device and the resultant product, such as a solar cell. The electrode in deposited on a transparent substrate in at least two steps. The oxygen partial pressure is reduced in the first step to produce an oxygen-deficient ZnO layer, which is highly conductive and has a textured surface, and is increased in the second step to produce a more stoichiometric ZnO, which has a refractive index more closely matched to the overlying silicon device. The second layer is substantially thinner than the first so the surface texture is transferred across it and the overall sheet resistance of the stack structure is reduced.Type: GrantFiled: October 24, 2006Date of Patent: October 13, 2009Assignee: Applied Materials, Inc.Inventors: Yanping Li, Yan Ye
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Publication number: 20090250112Abstract: Disclosed are a relatively high-efficiency solar cell and a method for fabricating the same using a micro-heater array. The solar cell may include first and second micro-heaters intersecting each other or being parallel to each other on a substrate, and a plurality of InxGa1-xN p-n junction layers formed using the first and second micro-heaters. The solar cell has improved efficiency because sunlight with various wavelengths may be effectively absorbed by the plurality of InxGa1-xN p-n junction layers. Furthermore, relatively large-sized solar cells may be fabricated, because the plurality of InxGa1-xN p-n junction layers may be formed on a glass substrate using a micro-heater array.Type: ApplicationFiled: February 9, 2009Publication date: October 8, 2009Inventors: Junhee Choi, Jai Yong Han, Andrei Zoulkarneev
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Publication number: 20090229658Abstract: A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell, the method including: providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell using a non-isoelectronic surfactant such as selenium or tellurium, the graded interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell.Type: ApplicationFiled: March 13, 2008Publication date: September 17, 2009Applicant: Emcore CorporationInventors: Mark A. Stan, Arthur Comfeld, Fred Newman
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Publication number: 20090215220Abstract: A solid-state image capturing device, includes a semiconductor board, upon which same semiconductor board are disposed in a predetermined order: a first detecting unit for detecting a first wavelength region component within an electromagnetic wave; and a second detecting unit for detecting a second wavelength region component which is longer wavelength side than at least the first wavelength region component, wherein in the depth direction from the surface of the semiconductor board, a valid region where a first electroconductive type dopant of the second detecting unit is formed reaches a portion deeper than a valid region where a first electroconductive type dopant of the first detecting unit is formed.Type: ApplicationFiled: May 4, 2009Publication date: August 27, 2009Applicant: Sony CorporationInventor: Atsushi TODA
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Patent number: 7569284Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.Type: GrantFiled: July 3, 2008Date of Patent: August 4, 2009Assignee: ASM America, Inc.Inventors: Eric J Shero, Christophe Pomarede
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Publication number: 20090186441Abstract: The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to decrease transient enhanced diffusion effects, minimize fixed pattern noise and fill factor loss.Type: ApplicationFiled: April 18, 2008Publication date: July 23, 2009Inventor: Chandra Mouli
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Publication number: 20090184388Abstract: A photodiode includes a silicon semiconductor layer; a P-type high concentration diffusion layer with a P-type impurity diffused therein at a high concentration; an N-type high concentration diffusion layer with an N-type impurity diffused therein at a high concentration; and a low concentration diffusion layer with one of the P-type impurity and the N-type impurity diffused therein at a low concentration. The P-type high concentration diffusion layer and the N-type high concentration diffusion layer are formed in the silicon semiconductor layer, and are arranged to face each other with the low concentration diffusion layer in between. The photodiode further includes an interlayer insulation film formed on the silicon semiconductor layer, so that a covalent bond between silicon and hydrogen is formed in an atom row of the low concentration layer adjacent to an interface thereof with respect to the interlayer insulation film.Type: ApplicationFiled: January 9, 2009Publication date: July 23, 2009Inventor: Takashi Izumi
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Patent number: 7550309Abstract: The present invention is a method for producing a semiconductor wafer, comprising at least steps of, epitaxially growing a Si1-XGeX layer (0<X<1) on an SOI wafer, forming a Si1-YGeY layer (0?Y<X) on the epitaxially grown Si1-XGeX layer, and then enriching Ge in the epitaxially grown Si1-XGeX layer by an oxidation heat treatment so that the Si1-XGeX layer becomes an enriched SiGe layer, wherein, at least, the oxidation heat treatment is initiated from 950° C. or less under an oxidizing atmosphere, and the oxidation is performed so that the formed Si1-YGeY layer remains during a temperature rise to 950° C. Thereby, there can be provided a method for producing a semiconductor wafer by which the lattice relaxation of the SiGe layer in an SGOI wafer can be sufficiently performed by a heat treatment for a short time and its production cost can be reduced.Type: GrantFiled: September 16, 2005Date of Patent: June 23, 2009Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Isao Yokokawa, Nobuhiko Noto, Kiyoshi Mitani
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Publication number: 20090140367Abstract: An optical semiconductor device is provided with a low concentration p-type silicon substrate (1); a low dopant concentration n-type epitaxial layer (second epitaxial layer) (26); a low dopant concentration p-type anode layer (27); a high concentration n-type cathode contact layer (9); a photodiode (2) made of the anode layer (27) and the cathode contact layer (9); and an NPN transistor (3) formed on the n-type epitaxial layer (26). The anode can be substantially completely depleted in the case where the anode layer (27) has its dopant concentration peak in the vicinity of the interface between the silicon substrate (1) and the n-type epitaxial layer (26). Therefore, high speed and high light receiving sensitivity characteristics can be obtained, and further, any influence of auto-doping from peripheral embedding layers can be controlled, so that a depletion layer can be stably formed in the anode.Type: ApplicationFiled: April 3, 2007Publication date: June 4, 2009Inventor: Takaki Iwai
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Publication number: 20090140368Abstract: A photodiode includes a photosensitive element formed in a silicon semiconductor layer on an insulation layer. The photosensitive element includes a low concentration diffusion layer, a P-type high concentration diffusion layer, and an N-type high concentration diffusion layer. A method of producing the photodiode includes the steps of: forming an insulation material layer on the silicon semiconductor layer after the P-type impurity and the N-type impurity are implanted into the low concentration diffusion layer, the P-type high concentration diffusion layer, and the N-type high concentration diffusion layer; forming an opening portion in the insulation material layer in an area for forming the low concentration diffusion layer; and etching the silicon semiconductor layer in the area for forming the low concentration diffusion layer so that a thickness of the silicon semiconductor layer is reduced to a specific level.Type: ApplicationFiled: November 13, 2008Publication date: June 4, 2009Inventor: Noriyuki Miura
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Publication number: 20090078311Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell, the method including: providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a barrier layer over the second subcell using a surfactant, preferably a isoelectronic surfactant such as bismuth or antimony; forming a graded interlayer over the barrier layer, the graded interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell.Type: ApplicationFiled: April 14, 2008Publication date: March 26, 2009Applicant: Emcore CorporationInventors: Mark A. Stan, Arthur Cornfeld, Fred Newman
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Publication number: 20090020782Abstract: The invention relates to an avalanche photodiode having enhanced gain uniformity enabled by a tailored diffused p-n junction profile. The tailoring is achieved by a two stage doping process incorporating a solid source diffusion in combination with conventional gas source diffusion. The solid source diffusion material is selected for its solubility to the dopant compared to the solubility of the multiplication layer to dopant. The solid source has a diameter between the first and second diffusion windows. Thus, there are three distinct diffusion regions during the second diffusion. The dopant in the multiplication layer at the edge region, the dopant from the solid source material with a relatively higher dopant concentration (limited by the solubility of the dopant in the solid source material) at the intermediate region, and the central region exposed to an infinite diffusion source from the solid source material as it is continually charged with new dopant from the external gas source.Type: ApplicationFiled: July 15, 2008Publication date: January 22, 2009Applicant: JDS Uniphase CorporationInventors: Zhong Pan, David Venables, Craig Ciesla
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Patent number: 7442627Abstract: A transparent conductive layer forming method is disclosed which comprises the steps of introducing a reactive gas to a discharge space, exciting the reactive gas in a plasma state by discharge at atmospheric pressure or at approximately atmospheric pressure, and exposing a substrate to the reactive gas in a plasma state to form a transparent conductive layer on the substrate, wherein the reactive gas comprises a reducing gas.Type: GrantFiled: September 29, 2006Date of Patent: October 28, 2008Assignee: Konica CorporationInventors: Toshio Tsuji, Hiroto Itoh, Takakazu Kiyomura
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Patent number: 7416909Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.Type: GrantFiled: February 6, 2007Date of Patent: August 26, 2008Assignee: AmberWave Systems CorporationInventors: Matthew T. Currie, Anthony J. Lochtefeld
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Publication number: 20080173347Abstract: One exemplary embodiment is a semiconductor structure, that can include a semiconductor substrate of one conductivity type, having a front surface and a back surface, a first semiconductor layer disposed on the front surface of the semiconductor substrate, a second semiconductor layer disposed on a portion of the back surface of the semiconductor substrate, and a third semiconductor layer disposed on another portion of the back surface of the semiconductor substrate. Each of the second and third semiconductor layers may be compositionally graded through its depth, from substantially intrinsic at an interface with the substrate, to substantially conductive at an opposite side, and have a selected conductivity type obtained by the incorporation of one or more selected dopants.Type: ApplicationFiled: January 23, 2007Publication date: July 24, 2008Applicant: General Electric CompanyInventors: Bastiaan Arie Korevaar, James Neil Johnson
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Publication number: 20080128849Abstract: A photodetector is formed from a body of semiconductor material substantially surrounded by dielectric surfaces. A passivation process is applied to at least one surface to reduce the rate of carrier generation and recombination on that surface. Photocurrent is read out from at least one electrical contact, which is formed on a doped region whose surface lies entirely on a passivated surface. Unwanted leakage current from un-passivated surfaces is reduced through one of the following methods. (a) The un-passivated surface is separated from the photo-collecting contact by at least two junctions (b) The un-passivated surface is doped to a very high level, at least equal to the conduction band or valence band density of states of the semiconductor (c) An accumulation or inversion layer is formed on the un-passivated surface by the application of an electric field. Electrical contacts are made to all doped regions, and bias is applied so that a reverse bias is maintained across all junctions.Type: ApplicationFiled: October 29, 2007Publication date: June 5, 2008Applicant: Noble Peak Vision Corp.Inventors: Conor S. Rafferty, Clifford A. King
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Patent number: 7368308Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.Type: GrantFiled: September 15, 2005Date of Patent: May 6, 2008Assignee: AmberWave Systems CorporationInventors: Christopher Vineis, Vicky Yang, Matthew Currie, Richard Westhoff, Christopher Leitz
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Patent number: 7259036Abstract: Methods and apparatus are described for irradiating one or more substrate surfaces with accelerated gas clusters including strain-inducing atoms for blanket and/or localized introduction of such atoms into semiconductor substrates, with additional, optional introduction of dopant atoms and/or C. Processes for forming semiconductor films infused into and/or deposited onto the surfaces of semiconductor and/or dielectric substrates are also described. Such films may be doped and/or strained as well.Type: GrantFiled: February 14, 2005Date of Patent: August 21, 2007Assignee: TEL Epion Inc.Inventors: John O. Borland, John J. Hautala, Wesley J. Skinner, Martin D. Tabat
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Patent number: 7256075Abstract: The invention relates to a method of transferring useful layers from a donor wafer which includes a multi-layer structure on the surface of the donor wafer that has a thickness sufficient to form multiple useful layers for subsequent detachment. The layers may be formed of materials having sufficiently different properties such that they may be selectively removed. The layers of material may also include sub-layers that can be selectively removed from each other.Type: GrantFiled: March 7, 2005Date of Patent: August 14, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Yves Mathieu Le Vaillant
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Patent number: 7211458Abstract: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.Type: GrantFiled: August 8, 2005Date of Patent: May 1, 2007Assignee: North Carolina State UniversityInventors: Mehmet Ozturk, Veena Misra, Saurabh Chopra
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Patent number: 7049627Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.Type: GrantFiled: August 22, 2003Date of Patent: May 23, 2006Assignee: AmberWave Systems CorporationInventors: Christopher Vineis, Vicky Yang, Matthew Currie, Richard Westhoff, Christopher Leitz
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Patent number: 6991956Abstract: A method for transferring a layer of semiconductor material from a wafer is described. The wafer includes a support substrate and an upper surface that includes a buffer layer of a material having a first lattice parameter. In an embodiment, the technique includes growing a strained layer on the buffer layer. The strained layer is made of a semiconductor material having a nominal lattice parameter that is substantially different from the first lattice parameter, and it is grown to a thickness that is sufficiently thin to avoid relaxation of the strain therein. The method also includes growing a relaxed layer on the strained layer. The relaxed layer is made of silicon and has a concentration of at least one other semiconductor material that has a nominal lattice parameter that is substantially identical to the first lattice parameter. The technique also includes providing a weakened zone in the buffer layer, and supplying energy to detach a structure at the weakened zone.Type: GrantFiled: January 10, 2005Date of Patent: January 31, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Nicolas Daval
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Patent number: 6949809Abstract: A light receiving element, comprising a semiconductor structure comprising at least a first conductivity type semiconductor layer, a first, second conductivity type semiconductor layer provided on the first conductivity type semiconductor layer in the semiconductor structure, a second, second conductivity type semiconductor layer having an impurity concentration lower than that of the first, second conductivity type semiconductor layer, a second, first conductivity type semiconductor layer provided on the second, second conductivity type semiconductor layer, or a second, first conductivity type semiconductor layer provided within the second, second conductivity type semiconductor layer.Type: GrantFiled: October 30, 2002Date of Patent: September 27, 2005Assignee: Sharp Kabushiki KaishaInventors: Takahiro Takimoto, Isamu Ohkubo, Masaru Kubo, Hiroki Nakamura, Toshihiko Fukushima, Toshifumi Yoshikawa