Chalcogen (i.e., Oxygen (o), Sulfur (s), Selenium (se), Tellurium (te)) Containing Patents (Class 438/95)
  • Patent number: 10319871
    Abstract: Photovoltaic devices based on an Ag2ZnSn(S,Se)4 (AZTSSe) absorber and techniques for formation thereof are provided. In one aspect, a method for forming a photovoltaic device includes the steps of: coating a substrate with a conductive layer; contacting the substrate with an Ag source, a Zn source, a Sn source, and at least one of a S source and a Se source under conditions sufficient to form an absorber layer on the conductive layer having Ag, Zn, Sn, and at least one of S and Se; and annealing the absorber layer. Methods of doping the AZTSSe are provided. A photovoltaic device is also provided.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Supratik Guha, Oki Gunawan, Richard A. Haight, Yun Seog Lee
  • Patent number: 10276740
    Abstract: A method for forming a photon absorbing layer. A substrate having a target surface is introduced into a controllable environment, and the pressure within the controllable environment is reduced. A first flux of a semiconductor material and a second flux of a dopant are simultaneously directed toward the target surface for a period of time, thereby producing a thickness of a substantially amorphous layer of the semiconductor material and dopant on the target surface. The semiconductor layer is laser annealed to convert it to a substantially multi-crystalline layer.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 30, 2019
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Rajani Ayachitula, Kimberly D. de La Harpe, Daniel E. Weisz, John M. Testerman, William J. Mandeville, Randall J. Knize, Brian M. Patterson
  • Patent number: 10170649
    Abstract: Disclosed are metal chalcogenide nanoparticles forming a light absorption layer of solar cells including a first phase including copper (Cu)-tin (Sn) chalcogenide and a second phase including zinc (Zn) chalcogenide, and a method of preparing the same.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 1, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Eunju Park, Seokhee Yoon, Seokhyun Yoon, Hosub Lee
  • Patent number: 10059810
    Abstract: The present invention provides a method for synthesizing a new class of inorganic-organic polymeric materials. These polymers are made with a backbone comprising chalcogenide elements such as sulfur, selenium, and/or tellurium along with organic crosslinking moieties that determine its physical and optical properties. Also disclosed are the related polymeric materials. These polymers are suitable for optical applications in short wave infrared (SWIR, 1-3 ?m) and mid wave infrared (MWIR, 3-8 ?m) regions.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: August 28, 2018
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Colin C. Baker, Darryl A. Boyd, Jason D. Myers, Vinh Q. Nguyen, Gryphon A. Drake, Woohong Kim, Steven R. Bowman, Jasbinder S. Sanghera
  • Patent number: 10048411
    Abstract: The present invention provides an optical coating structure (10) applied to the surface of an object. “Scattering structures” are introduced to the basal, upper or middle layers of a multilayer reflector to cause a particular (calculated) degree of scattering, or to the surface of a black/color pigmented object to cause either enhanced transmission at the environment-object interface or omni-directional (as opposed to directional) reflections of which only a narrow portion can be observed. The scattering structures are mainly sub-micron in size, and arranged in a pseudo-random or non-periodic manner so as to prevent significant diffraction by themselves.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: August 14, 2018
    Inventor: Andrew Richard Parker
  • Patent number: 10032949
    Abstract: Photovoltaic devices based on an Ag2ZnSn(S,Se)4 (AZTSSe) absorber and techniques for formation thereof are provided. In one aspect, a method for forming a photovoltaic device includes the steps of: coating a substrate with a conductive layer; contacting the substrate with an Ag source, a Zn source, a Sn source, and at least one of a S source and a Se source under conditions sufficient to form an absorber layer on the conductive layer having Ag, Zn, Sn, and at least one of S and Se; and annealing the absorber layer. Methods of doping the AZTSSe are provided. A photovoltaic device is also provided.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Supratik Guha, Oki Gunawan, Richard A. Haight, Yun Seog Lee
  • Patent number: 10011901
    Abstract: A vapor deposition method supplies a material gas onto a substrate while heating the substrate by a heater to sequentially form a plurality of films with vapor deposition, grows the film under a constant output control, which keeps an output of the heater at a predetermined output in each of the plurality of films, until a total film thickness of the films formed on the substrate reaches a threshold value, and grows the film under a temperature feedback control, which controls the output of the heater such that a temperature of the substrate measured by a radiation thermometer becomes a predetermined temperature, after the total film thickness reaches the threshold value.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: July 3, 2018
    Assignee: NuFlare Technology, Inc.
    Inventors: Hideshi Takahashi, Yuusuke Sato
  • Patent number: 9975115
    Abstract: Provided are a photocatalyst having higher activity for hydrogen production through water splitting and a photoelectrode comprising the photocatalyst. The photocatalyst for water splitting of the present invention comprises a Ga selenide, an Ag—Ga selenide, or both thereof.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: May 22, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, THE UNIVERSITY OF TOKYO
    Inventors: Haruyuki Nakanishi, Tsutomu Minegishi, Kazunari Domen, Jun Kubota, Chika Miwada
  • Patent number: 9899561
    Abstract: The present invention relates to a method for producing a compound semiconductor (2), which comprises the following steps: Producing at least one precursor layer stack (11), consisting of a first precursor layer (5.1), a second precursor layer (6), and a third precursor layer (5.2), wherein, in a first stage, the first precursor layer (5.1) is produced by depositing the metals copper, indium, and gallium onto a body (12), and, in a second stage, the second precursor layer (6) is produced by depositing at least one chalcogen, selected from sulfur and selenium, onto the first precursor layer (5.1) and, in a third stage, the third precursor layer (5.2) is produced by depositing the metals copper, indium, and gallium onto the second precursor layer (6); Heat treating the at least one precursor layer stack (11) in a process chamber (13) such that the metals of the first precursor layer (5.1), the at least one chalcogen of the second precursor layer (6), and the metals of the third precursor layer (5.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: February 20, 2018
    Assignee: Bengbu Design & Research Institute for Glass Industry
    Inventors: Stefan Jost, Robert Lechner, Thomas Dalibor, Patrick Eraerds
  • Patent number: 9780246
    Abstract: A method for manufacturing a CZTS based thin film having a dual band gap slope, comprising the steps of: forming a Cu2ZnSnS4 thin film layer; forming a Cu2ZnSn(S,Se)4 thin film layer; and forming a Cu2ZnSnS4 thin film layer. A method for manufacturing a CZTS based solar cell having a dual band gap slope according to another aspect of the present invention comprises the steps of: forming a back contact; and forming a CZTS based thin film layer on the back contact by the method described above.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: October 3, 2017
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Jae Ho Yun, Jihye Gwak, SeJin Ahn, Kyung Hoon Yoon, Kee Shik Shin, SeoungKyu Ahn, Ara Cho, Sang Hyun Park, Jun Sik Cho, Jin Su You, Joo Hyung Park, Young Joo Eo
  • Patent number: 9755145
    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Giorgio Servalli, Carmela Cupeta, Fabio Pellizzer
  • Patent number: 9748422
    Abstract: A semiconductor nanocrystal include a first I-III-VI semiconductor material and have a luminescence quantum yield of at least 10%, at least 20%, or at least 30%. The nanocrystal can be substantially free of toxic elements. Populations of the nanocrystals can have an emission FWHM of no greater than 0.35 eV.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: August 29, 2017
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Peter Matthew Allen, Moungi G. Bawendi
  • Patent number: 9647153
    Abstract: The disclosed technology generally relates to chalcogenide thin films, and more particularly to ternary and quaternary chalcogenide thin films having a wide band-gap, and further relates to photovoltaic cells containing such thin films, e.g., as an absorber layer. In one aspect, a method of forming a ternary or quaternary thin film chalcogenide layer containing Cu and Si comprises depositing a copper layer on a substrate. The method additionally comprises depositing a silicon layer on the copper layer with a [Cu]/[Si] atomic ratio of at least 0.7, and thereafter annealing in an inert atmosphere. The method further includes performing a first selenization or a first sulfurization, thereby forming a ternary thin film chalcogenide layer on the substrate. In another aspect, a composite structure includes a substrate having a service temperature not exceeding 600° C.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: May 9, 2017
    Assignees: IMEC VZW, King Abdulaziz City for Science and Technology, Katholieke Universiteit Leuven, Universiteit Hasselt
    Inventors: Hossam ElAnzeery, Marie Buffiere, Marc Meuris
  • Patent number: 9627200
    Abstract: The present disclosure provides systems, processes, articles of manufacture, and compositions that relate to core/shell semiconductor nanowires. Specifically, the disclosure provides a novel semiconductor material, CdSe/ZnS core/shell nanowires, as well as a method of preparation thereof. The disclosure also provides a new continuous flow method of preparing core/shell nanowires, including CdSe/CdS core/shell nanowire and CdSe/ZnS core/shell nanowires.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: April 18, 2017
    Assignee: US Nano LLC
    Inventors: Anthony C. Onicha, Louise E. Sinks, Stefanie L. Weber
  • Patent number: 9627611
    Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: April 18, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jun Liu, Kunal Parekh
  • Patent number: 9614004
    Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Kristy A. Campbell
  • Patent number: 9583703
    Abstract: A variable resistance memory device may include a first electrode and a second electrode. The device may further include a chalcogenide glass layer between the first electrode and the second electrode. The chalcogenide glass layer may include a chalcogenide glass material co-deposited with a metal material. The device may also include a metal ion source structure between the chalcogenide glass layer and the second electrode. The device may include a buffer layer between the first electrode and the chalcogenide glass layer.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: February 28, 2017
    Assignee: BOISE STATE UNIVERSITY
    Inventor: Kristy A. Campbell
  • Patent number: 9525132
    Abstract: A method for fabricating a phase change memory device uses the well-developed semiconductor process to fabricate a larger-size sacrifice beforehand, and next uses a wet etching technology to form a narrowed sacrifice layer having a smaller size, and then removes the narrowed sacrifice layer to form the desired mask pattern, whereby the method can precisely define and easily adjust a smaller-size heater and have a stable fabrication process.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 20, 2016
    Assignees: NINGBO ADVANCED MEMORY TECHNOLOGY CORP., BEING ADVANCED MEMORY TAIWAN LIMITED
    Inventor: Shui-Chin Su
  • Patent number: 9478695
    Abstract: The invention relates to a method of manufacturing a I-III-VI2 layer with photovoltaic properties, comprising: deposition of a metal on a substrate to form a contact layer, deposition of a precursor of the photovoltaic layer, on the contact layer, and heat treatment of the precursor with an addition of element VI to form the I-III-VI2 layer. The element VI usually diffuses into the contact layer (MO) during the heat treatment and combines with the metal to form a superficial layer (SUP) on the contact layer. In the method of the invention, the metal deposition comprises a step during which an additional element is added to the metal to form a compound (MO-EA), in the contact layer, acting as a barrier to the diffusion of the element VI, which allows precisely controlling the properties of the superficial layer, particularly its thickness.
    Type: Grant
    Filed: November 22, 2012
    Date of Patent: October 25, 2016
    Assignee: NEXCIS
    Inventors: Stephanie Angle, Ludovic Parissi
  • Patent number: 9378947
    Abstract: Improved methods and apparatus for forming thin-film buffer layers of chalcogenide on a substrate web. Solutions containing the reactants for the buffer layer or layers may be dispensed separately to the substrate web, rather than being mixed prior to their application. The web and/or the dispensed solutions may be heated by a plurality of heating elements.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: June 28, 2016
    Assignee: Hanergy Hi-Tech Power (HK) Limited
    Inventors: Jeffrey S. Britt, Scot Albright, Urs Schoop
  • Patent number: 9373784
    Abstract: A semiconductor memory device includes a first insulating portion. The semiconductor memory device further includes a phase-change material element that contacts the first insulating portion. The semiconductor memory device further includes an electrode that contacts a side surface of the phase-change material element, the side surface of the phase-change material element being not parallel to a top surface of the electrode. The semiconductor memory device further includes a second insulating portion surrounding the phase-change material element.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: June 21, 2016
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Jia Xu, GuanPing Wu, Chao Zhang, Daisy Liu
  • Patent number: 9362495
    Abstract: Methods, devices, and systems associated with resistance variable memory device structures can include a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: June 7, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Zailong Bian
  • Patent number: 9337376
    Abstract: A multi-stage method and apparatus for vaporizing and depositing a tellurium containing semiconductor material on a substrate.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: May 10, 2016
    Assignee: First Solar, Inc.
    Inventors: Arnold Allenic, Zhigang Ban, John Barden, Benjamin Milliron, Rick C. Powell
  • Patent number: 9337421
    Abstract: The present invention relates to a phase-change memory device structure and the materials used. The structure comprises a substrate, a single or multiple sandwich-memory-unit(s), a first electrode, and a second electrode. The sandwich-memory-unit contains an upper barrier layer, a lower barrier layer, and a memory layer therebetween. The thickness of the memory-layer is less than 30 nm. The present invention provides a phase-change memory device with a high Tc and a low volume changing rate during phase-change.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: May 10, 2016
    Assignee: FENG CHIA UNIVERSITY
    Inventors: Tsung-Shune Chin, Chih-Chung Chang, Yung-Ching Chu
  • Patent number: 9318642
    Abstract: A method and apparatus are disclosed in which cadmium chloride is deposited on a cadmium telluride layer while simultaneously heat treating the cadmium telluride layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: April 19, 2016
    Assignee: FIRST SOLAR, INC.
    Inventors: Akhlesh Gupta, Markus Gloeckler, Ricky C. Powell
  • Patent number: 9293703
    Abstract: An object is to provide a memory including a memory device which includes a layer whose resistance changes and in which reset can be performed by using a reset gate. The object is achieved by a memory device including a pillar-shaped layer whose resistance changes, a reset gate insulating film surrounding the pillar-shaped layer whose resistance changes, and a reset gate surrounding the reset gate insulating film.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 22, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9287434
    Abstract: Methods for producing a semiconductor layer and for producing a photoelectric conversion device, semiconductor raw material are disclosed. An embodiment of the method for producing a semiconductor layer includes: forming a film containing a metal element and an oxygen element; generating oxygen gas by heating the film; and forming a semiconductor layer containing a metal chalcogenide from the film by allowing the metal element to react with a chalcogen element. Another embodiment of the method includes forming a lower film containing a metal element; forming an upper film, which contains the metal element and a substance that contains oxygen, on the lower film; generating oxygen gas by heating the substance; and forming a semiconductor layer containing a metal chalcogenide from the lower film and the upper film by allowing a chalcogen element to react with the metal element in the lower film and the upper film.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: March 15, 2016
    Assignee: KYOCERA Corporation
    Inventors: Akio Yamamoto, Seiji Oguri, Hiromitsu Ogawa, Aki Kitabayashi, Shinichi Abe, Kazumasa Umesato, Norihiko Matsushima, Keizo Takeda, Manabu Kyuzo, Ken Nishiura, Atsuo Hatate
  • Patent number: 9273389
    Abstract: A quaternary alloy sputtering target composed of copper (Cu), indium (In), gallium (Ga) and selenium (Se), wherein a composition ratio of the respective elements is represented by a formula of CuxIn1-yGaySea (in the formula, 0.84?x?0.98, 0<y?0.5, a=(1/2)x+3/2), and a structure observed via EPMA is configured only from a Cu(In, Ga)Se2 phase without any heterogenous phase of Cu2Se or Cu(In, Ga)3Se5. Provided is a CIGS quaternary alloy sputtering target which is subject to hardly any abnormal discharge even when sputtered for a long period, which is free of any heterogenous phase of Cu2Se or Cu(In, Ga)3Se5 which causes the deterioration in the conversion efficiency of the film after being sputter-deposited, and which can produce a film having superior in-plane uniformity. Additionally provided is a CIGS quaternary alloy sputtering target having a predetermined bulk resistance and a high density.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: March 1, 2016
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Tomoya Tamura, Hideo Takami, Masaru Sakamoto
  • Patent number: 9263623
    Abstract: Methods are described for depositing thin films, such as those used in forming a photovoltaic cell or device. In particular embodiments, one or more layers are deposited on a substrate by plasma spraying over the substrate. A grain size of grains in each of the one or more layers is at least approximately two times greater than a thickness of the respective layer. Accordingly, large flat-grained structures are formed in each respective layer, and grain boundaries within each respective layer can be minimized.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: February 16, 2016
    Assignee: ZETTA RESEARCH AND DEVELOPMENT LLC—AQT SERIES
    Inventors: Brian Josef Bartholomeusz, Michael Bartholomeusz
  • Patent number: 9257642
    Abstract: Some embodiments relate to a resistive random access memory (RRAM). The RRAM includes a RRAM bottom metal electrode, a variable resistance dielectric layer arranged over the RRAM bottom metal electrode, and a RRAM top metal electrode arranged over the variable resistance dielectric layer. A capping layer is arranged over the RRAM top metal electrode. A lower surface of the capping layer and an upper surface of the RRAM top metal electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the RRAM top metal electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the RRAM top metal electrode meets the lower surface of the capping layer.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Jian-Shiou Huang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Patent number: 9219186
    Abstract: A structure and method of making a thin-film solar cell is provided. A thin-film solar cell includes a substrate, absorber layer and a buffer layer. The absorber layer is deposited by a single-step bulk electrochemical process, or a multi-layer electrochemical process. The buffer layer is deposited by an electrochemical deposition process such as a multi-layer deposition or an atomic layer deposition. The absorber and buffer layers are non-toxic materials which can include sulfur incorporated during the deposition process or incorporated after deposition by an anneal step.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: December 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Lian Guo, Raman Vaidyanathan
  • Patent number: 9206054
    Abstract: Materials and methods for preparing Cu2ZnSnS4 (CZTS) layers for use in thin film photovoltaic (PV) cells are disclosed herein. The CZTS materials are nanoparticles prepared by a colloidal synthesis in the presence of a labile organothiol. The organothiol serves as both a sulphur source and as a capping ligand for the nanoparticles.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: December 8, 2015
    Assignee: Nanoco Technologies Ltd.
    Inventors: Nathalie Gresty, Ombretta Masala, James Harris, Nigel Pickett
  • Patent number: 9178103
    Abstract: A method and system for forming chalcogenide semiconductor absorber materials with sodium impurities is provided. The system includes a sodium vaporizer in which a solid sodium source material is vaporized. The sodium vapor is added to reactant gases and/or annealing gases and directed to a furnace that includes a substrate with a metal precursor material. The precursor material reacts with reactant gases such as S-containing gases and Se-containing gases according to various process sequences. In one embodiment, a selenization operation is followed by an annealing operation and a sulfurization operation and the sodium vapor is caused to react with the metal precursor during at least one of the annealing and the sulfurization steps to produce a chalcogenide semiconductor absorber material that includes sodium dopant impurities.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: November 3, 2015
    Assignee: TSMC Solar Ltd.
    Inventors: Chung-Hsien Wu, Wen-Tsai Yen, Jyh-Lih Wu
  • Patent number: 9178097
    Abstract: Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for forming a Cu—In—Ga layer followed by partial or full selenization. This results in a higher Ga concentration at the back interface. The substrate is then exposed to an aluminum CVD precursor while the substrate is still in the selenization equipment to deposit a thin Al layer. The substrate is then exposed to a Se source to fully convert the absorber layer. This results in a higher Al concentration at the front of the absorber.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: November 3, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Jeroen Van Duren
  • Patent number: 9166164
    Abstract: A method for manufacturing a nonvolatile semiconductor storage device according to an embodiment includes laminating a first wire extending in a first direction, and a film made into a variable resistance element made of a metallic material, which are laminated in order on a semiconductor substrate, dividing, into a plurality of pieces, the film made into the variable resistance element, in the first direction and a second direction, forming an interlayer insulating film between the plurality of pieces formed by dividing the film made into the variable resistance element in the second direction, and oxidizing the metallic material of the film made into the variable resistance element, and laminating an upper electrode and a second wire extending in the second direction, which are laminated in order on the film made into the variable resistance element and the interlayer insulating film.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: October 20, 2015
    Assignee: KABUSHIKI KAISHA
    Inventor: Toshiharu Tanaka
  • Patent number: 9142770
    Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: September 22, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Joseph N. Greeley, John A. Smythe, III
  • Patent number: 9136467
    Abstract: A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material as part of either of the first and second electrodes and being devoid of heater material between either of the first and second electrodes and the phase change material. A method of forming a memory cell having first and second electrodes having phase change material there-between includes lining elevationally inner sidewalls of an opening with conductive material to comprise the first electrode of the memory cell. Elevationally outer sidewalls of the opening are lined with dielectric material. Phase change material is formed in the opening laterally inward of and electrically coupled to the conductive material in the opening. Conductive second electrode material is formed that is electrically coupled to the phase change material. Other implementations are disclosed.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: September 15, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Damon E. Van Gerpen, Roberto Bez
  • Patent number: 9130162
    Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 8, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Yu-Wen Liao, Chin-Chieh Yang, Wen-Ting Chu
  • Patent number: 9117515
    Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient bridge in the second dielectric layer, and make a conductive path through the cell if the bridge is present in the first dielectric layer. If the bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 25, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Feng-Ming Lee, Yu-Yu Lin
  • Patent number: 9093600
    Abstract: A method of p-type doping cadmium telluride (CdTe) is disclosed. The method comprising the steps of, (a) providing a first component comprising cadmium telluride (CdTe) comprising an interfacial region, and (b) subjecting the CdTe to a functionalizing treatment to obtain p-type doped CdTe, said functionalizing treatment comprising a thermal treatment of at least a portion of the interfacial region in the presence of a first material comprising a p-type dopant, and of a second material comprising a halogen. A method of making a photovoltaic cell is also disclosed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: July 28, 2015
    Assignee: First Solar, Inc.
    Inventors: John Anthony DeLuca, Scott Feldman-Peabody
  • Patent number: 9087943
    Abstract: A method for forming a thin film photovoltaic device includes providing a transparent substrate comprising a surface region and forming a first electrode layer overlying the surface region. Additionally, the method includes forming a copper indium material comprising an atomic ratio of Cu:In ranging from about 1.35:1 to about 1.60:1 by at least sputtering a target comprising an indium copper material. The method further includes subjecting the copper indium material to thermal treatment process in an environment containing a sulfur bearing species. Furthermore, the method includes forming a copper indium disulfide material from at least the thermal treatment process of the copper indium material and maintaining an interface region between the copper indium disulfide material and electrode substantially free from a metal disulfide layer, which has different semiconductor characteristics from the copper indium disulfide material.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: July 21, 2015
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 9082967
    Abstract: A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer which is in contact with the second electrode; wherein the electrically-conductive layer covers an entire of the second electrode and at least a portion of the side wall protective layer located outward relative to the second electrode, when viewed from a thickness direction; and the side wall protective layer extends across the second electrode to a position above an upper end of the second electrode such that an upper end of the side wall protective layer is located above the upper end of the second electrode, when viewed from a side.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 14, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideaki Murase, Yoshio Kawashima, Atsushi Himeno
  • Patent number: 9059073
    Abstract: A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
  • Patent number: 9054264
    Abstract: Systems and methods for solar cells with CIS and CIGS films made by reacting evaporated copper chlorides with selenium are provided. In one embodiment, a method for fabricating a thin film device comprises: providing a semiconductor film comprising indium (In) and selenium (Se) upon a substrate; heating the substrate and the semiconductor film to a desired temperature; and performing a mass transport through vapor transport of a copper chloride vapor and se vapor to the semiconductor film within a reaction chamber.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: June 9, 2015
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: David S. Albin, Rommel Noufi
  • Publication number: 20150144186
    Abstract: Embodiments disclosed herein include photovoltaic absorber materials (302) and photovoltaic devices (300) having absorber materials (302) with intentionally increased permittivity. Alternative embodiments include methods (200) of producing thin film photovoltaic absorbers (302) from materials having increased permittivity or methods of producing devices having absorbers (302) with increased permittivity. In selected embodiments, the permittivity of an absorber material (302) is increased by incorporating a permittivity increasing material therein.
    Type: Application
    Filed: May 16, 2013
    Publication date: May 28, 2015
    Inventor: Timothy A. Gessert
  • Publication number: 20150140724
    Abstract: In particular embodiments, a method is described for depositing thin films, such as those used in forming a photovoltaic cell or device. In a particular embodiment, the method includes providing a substrate suitable for use in a photovoltaic device and plasma spraying one or more layers over the substrate, the grain size of the grains in each of the one or more layers being at least approximately two times greater than the thickness of the respective layer.
    Type: Application
    Filed: December 15, 2014
    Publication date: May 21, 2015
    Inventors: Brian Josef BARTHOLOMEUSZ, Michael BARTHOLOMEUSZ
  • Publication number: 20150136231
    Abstract: A method for fabricating a thin film photovoltaic device is provided. The method includes providing a substrate comprising a surface region made of a thin-film photovoltaic absorber including copper, indium, gallium, selenium, and sulfur species. Additionally, the method includes applying a dip-in chemical bath deposition process for forming a buffer layer containing at least zinc-oxygen-sulfide material but substantially free of cadmium species. Furthermore, the method includes producing a chemical bath including steps of heating a bath of water to about 75° C., adding aqueous ammonia to mix with the bath of water, adding a solution of sodium hydroxide , adding zinc salt solution, and adding a solution of thiourea. The dip-in chemical bath deposition process includes immersing a plurality of substrates formed with the thin-film photovoltaic absorber substantially vertically in the chemical bath for 30 minutes to form the zinc-oxygen-sulfide buffer layer followed by a cleaning and drying process.
    Type: Application
    Filed: December 9, 2014
    Publication date: May 21, 2015
    Inventors: Robert D. Wieting, Jason Todd Jackson
  • Patent number: 9034686
    Abstract: Embodiments of the present invention include a method. The method includes heating a layer stack. The layer stack includes a first layer comprising cadmium and tin, a metal layer disposed over the first layer, and a window layer disposed over the metal layer. Heating the stack includes transforming at least a portion of the first layer from an amorphous phase to a crystalline phase. Heating may be performed using any of various configurations, such as, for example, heating an individual stack, or using a face-to-face configuration of multiple stacks. The stack may be used for fabricating a photovoltaic device.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 19, 2015
    Assignee: First Solar, Inc.
    Inventors: Hongying Peng, Bastiaan Arie Korevaar, Jinbo Cao, Stephen Lorenco Araujo, Scott Daniel Feldman-Peabody, Robert Dwayne Gossman
  • Publication number: 20150132885
    Abstract: The present invention relates to a method for preparing a CIS- or CIGS-based light-absorbing layer which is included in a thin film solar cell. More particularly, the present invention relates to a method for preparing a CIS- or CIGS-based light-absorbing layer which ultimately improves the efficiency of a solar cell since the remaining carbon impurities in the formed light-absorbing layer are minimized and additional sulfurization treatment or selenium treatment is made optional, not requisite.
    Type: Application
    Filed: October 8, 2014
    Publication date: May 14, 2015
    Inventors: Yeokwon YOON, Tae-Seok LEE, Kyoung-Jun LEE, Jae-Hong KIM
  • Patent number: RE45817
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array where a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other, wherein the memory cells have a variable resistance element and a non-ohmic element laminated in the direction in which the memory cell layers are laminated and tapered in such a manner that the area in a cross section gradually becomes smaller from the bottom memory cell layer towards the top memory cell layer, and the variable resistance element and the non-ohmic element in the memory cells in a certain memory cell layer are laminated in the same order as the variable resistance element and the non-ohmic element of the memory cells in another memory cell layer.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki Nagashima