Abstract: An array substrate, a manufacturing process of an array substrate, and a display panel are disclosed. The array substrate includes a substrate and a photosensitive element. The photosensitive element is disposed on the substrate and includes a doped semiconductor layer, an intrinsic semiconductor layer, and a transparent electrode layer sequentially stacked. By improving an internal structure of the photosensitive element, light absorption by an incident interface of the intrinsic semiconductor layer can be increased, so that sensitivity of the photosensitive element is enhanced.

Abstract: Provided is a solar cell module and a manufacturing method thereof, and a photovoltaic module. The solar cell module includes a substrate; and conductive layers arranged on a surface of the substrate and separated from each other. Solar sub-cells are provided on a surface of the conductive layer. Grooves are provided between adjacent solar sub-cells to separate the solar sub-cells from each other. Each of the solar sub-cells includes a hole transport layer, a perovskite layer and an electron transport layer that are stacked on the surface of the conductive layer. The hole transport layer of each solar sub-cell includes branch electrodes separated from each other. Each of the branch electrodes contacts an interior of the conductive layer. The solar cell module further includes an electrode. The electrode successively passes through the electron transport layer and the perovskite layer and is connected to the branch electrodes.

Abstract: A method may include forming a bottom electrode in an interlayer dielectric, depositing a liner on top of the bottom electrode, depositing a phase change material layer on top of the liner, wherein a top surface of the liner is in direct contact with a bottom surface of the phase change material layer, and depositing a barrier on top of the phase change material layer, wherein a top surface of the phase change material layer is in direct contact with a bottom surface of the barrier. The barrier may be made of doped phase change material. The forming of the bottom electrode may further include forming a via in the interlayer dielectric, depositing an outer layer along a bottom and a sidewall of the via, depositing a middle layer on top of the outer layer, and depositing an inner layer on top of the middle layer.

Abstract: A thermoelectric material of the present invention includes copper, tin, and sulfur, wherein a ratio A/B of the number A of copper atoms to the number B of tin atoms is 0.5 to 2.5 and a content of a metal element other than copper and tin is 5 mol % or less with respect to total metal elements. Additionally, the thermoelectric material of the present invention has a thermal conductivity less than 1.0 W/(m·K) at 200 to 400° C.

Abstract: The present invention proposes a method to form a CdSeTe thin film with a defined amount of selenium and with a high quality. The method comprises the steps of providing a base substrate and of depositing a partial CdSeTe layer on a first portion of the base substrate. The step of depositing a partial CdSeTe layer is performed at least twice, wherein a predetermined time period without deposition of a partial CdSeTe layer on the first portion of the base substrate is provided between two subsequent steps of depositing a partial CdSeTe layer. The temperature of the base substrate and the CdSeTe layer already deposited on the first portion of the base substrate is controlled during the predetermined time period such that re-evaporation of Cd and/or Te from the CdSeTe layer already deposited takes place.

Abstract: A photovoltaic device (100) can include an absorber layer (160). The absorber layer (160) can be doped p-type with a Group V dopant and can have a carrier concentration of the Group V dopant greater than 4×1015 cm?3. The absorber layer (160) can include oxygen in a central region of the absorber layer (160). The absorber layer (160) can include an alkali metal in the central region of the absorber layer (160). Methods for carrier activation can include exposing an absorber layer (160) to an annealing compound in a reducing environment (220). The annealing compound (224) can include cadmium chloride and an alkali metal chloride.

Abstract: Transition metal dichalcogenides (TMDs) are deposited as thin layers on a substrate. The TMDs may be grown on oxide substrates and may have a tunable TMD-oxide interface.

Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.

Abstract: Described herein is a diffusion-based ex-situ group V element doping method in the CdCl2 heat-treated polycrystalline CdTe film. The ex-situ doping using group V halides, such as PCl3, AsCl3, SbCl3, or BiCl3, demonstrated a promising PCE of ˜18% and long-term light soaking stability in CdSe/CdTe and CdS/CdTe devices with decent carrier concentration>1015 cm?3. This ex-situ solution or vapor process can provide a low-cost alternative pathway for effective doping of As, as well as P, Sb, and Bi, in CdTe solar cells with limited deviation from the current CdTe manufacturing process.

Abstract: An apparatus is provided, comprising: a film formation chamber; a substrate holder provided in the film formation chamber and holding a substrate (S) to be formed with a film; a decompressor configured to reduce a pressure in the film formation chamber to a predetermined pressure; a discharge gas introducer configured to introduce a discharge gas into the film formation chamber; two or more sputtering electrodes each provided with a target (T1, T2) to be a film-forming material, the sputtering electrodes facing the substrate as a single substrate; a DC power source configured to supply electric power to the sputtering electrodes; two or more pulse-wave conversion switches connected between the DC power source and the sputtering electrodes, the pulse-wave conversion switches each being configured to convert a DC voltage to be applied to each of the sputtering electrodes to a pulse-wave voltage; a programmable transmitter configured to be programmable with a pulse generation control signal pattern corresponding

Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

Abstract: Provided is a method for fabricating high-uniformity and high-quality metal chalcogenide thin films. The method for fabricating metal chalcogenide thin films may include forming a metal precursor thin film including a metal thin film and a chalcogen thin film disposed on the upper surface or lower surface of the metal thin film; and performing a chalcogenization process for providing a chalcogen source on the metal precursor thin film to form a first metal chalcogenide thin film.

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

Abstract: Photovoltaic devices based on an Ag2ZnSn(S,Se)4 (AZTSSe) absorber and techniques for formation thereof are provided. In one aspect, a method for forming a photovoltaic device includes the steps of: coating a substrate with a conductive layer; contacting the substrate with an Ag source, a Zn source, a Sn source, and at least one of a S source and a Se source under conditions sufficient to form an absorber layer on the conductive layer having Ag, Zn, Sn, and at least one of S and Se; and annealing the absorber layer. Methods of doping the AZTSSe are provided. A photovoltaic device is also provided.

Abstract: A method for forming a photon absorbing layer. A substrate having a target surface is introduced into a controllable environment, and the pressure within the controllable environment is reduced. A first flux of a semiconductor material and a second flux of a dopant are simultaneously directed toward the target surface for a period of time, thereby producing a thickness of a substantially amorphous layer of the semiconductor material and dopant on the target surface. The semiconductor layer is laser annealed to convert it to a substantially multi-crystalline layer.

Abstract: Disclosed are metal chalcogenide nanoparticles forming a light absorption layer of solar cells including a first phase including copper (Cu)-tin (Sn) chalcogenide and a second phase including zinc (Zn) chalcogenide, and a method of preparing the same.

Abstract: The present invention provides a method for synthesizing a new class of inorganic-organic polymeric materials. These polymers are made with a backbone comprising chalcogenide elements such as sulfur, selenium, and/or tellurium along with organic crosslinking moieties that determine its physical and optical properties. Also disclosed are the related polymeric materials. These polymers are suitable for optical applications in short wave infrared (SWIR, 1-3 ?m) and mid wave infrared (MWIR, 3-8 ?m) regions.

Abstract: The present invention provides an optical coating structure (10) applied to the surface of an object. “Scattering structures” are introduced to the basal, upper or middle layers of a multilayer reflector to cause a particular (calculated) degree of scattering, or to the surface of a black/color pigmented object to cause either enhanced transmission at the environment-object interface or omni-directional (as opposed to directional) reflections of which only a narrow portion can be observed. The scattering structures are mainly sub-micron in size, and arranged in a pseudo-random or non-periodic manner so as to prevent significant diffraction by themselves.

Abstract: Photovoltaic devices based on an Ag2ZnSn(S,Se)4 (AZTSSe) absorber and techniques for formation thereof are provided. In one aspect, a method for forming a photovoltaic device includes the steps of: coating a substrate with a conductive layer; contacting the substrate with an Ag source, a Zn source, a Sn source, and at least one of a S source and a Se source under conditions sufficient to form an absorber layer on the conductive layer having Ag, Zn, Sn, and at least one of S and Se; and annealing the absorber layer. Methods of doping the AZTSSe are provided. A photovoltaic device is also provided.

Abstract: A vapor deposition method supplies a material gas onto a substrate while heating the substrate by a heater to sequentially form a plurality of films with vapor deposition, grows the film under a constant output control, which keeps an output of the heater at a predetermined output in each of the plurality of films, until a total film thickness of the films formed on the substrate reaches a threshold value, and grows the film under a temperature feedback control, which controls the output of the heater such that a temperature of the substrate measured by a radiation thermometer becomes a predetermined temperature, after the total film thickness reaches the threshold value.

Abstract: Provided are a photocatalyst having higher activity for hydrogen production through water splitting and a photoelectrode comprising the photocatalyst. The photocatalyst for water splitting of the present invention comprises a Ga selenide, an Ag—Ga selenide, or both thereof.

Abstract: The present invention relates to a method for producing a compound semiconductor (2), which comprises the following steps: Producing at least one precursor layer stack (11), consisting of a first precursor layer (5.1), a second precursor layer (6), and a third precursor layer (5.2), wherein, in a first stage, the first precursor layer (5.1) is produced by depositing the metals copper, indium, and gallium onto a body (12), and, in a second stage, the second precursor layer (6) is produced by depositing at least one chalcogen, selected from sulfur and selenium, onto the first precursor layer (5.1) and, in a third stage, the third precursor layer (5.2) is produced by depositing the metals copper, indium, and gallium onto the second precursor layer (6); Heat treating the at least one precursor layer stack (11) in a process chamber (13) such that the metals of the first precursor layer (5.1), the at least one chalcogen of the second precursor layer (6), and the metals of the third precursor layer (5.

Abstract: A method for manufacturing a CZTS based thin film having a dual band gap slope, comprising the steps of: forming a Cu2ZnSnS4 thin film layer; forming a Cu2ZnSn(S,Se)4 thin film layer; and forming a Cu2ZnSnS4 thin film layer. A method for manufacturing a CZTS based solar cell having a dual band gap slope according to another aspect of the present invention comprises the steps of: forming a back contact; and forming a CZTS based thin film layer on the back contact by the method described above.

Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Abstract: A semiconductor nanocrystal include a first I-III-VI semiconductor material and have a luminescence quantum yield of at least 10%, at least 20%, or at least 30%. The nanocrystal can be substantially free of toxic elements. Populations of the nanocrystals can have an emission FWHM of no greater than 0.35 eV.

Abstract: The disclosed technology generally relates to chalcogenide thin films, and more particularly to ternary and quaternary chalcogenide thin films having a wide band-gap, and further relates to photovoltaic cells containing such thin films, e.g., as an absorber layer. In one aspect, a method of forming a ternary or quaternary thin film chalcogenide layer containing Cu and Si comprises depositing a copper layer on a substrate. The method additionally comprises depositing a silicon layer on the copper layer with a [Cu]/[Si] atomic ratio of at least 0.7, and thereafter annealing in an inert atmosphere. The method further includes performing a first selenization or a first sulfurization, thereby forming a ternary thin film chalcogenide layer on the substrate. In another aspect, a composite structure includes a substrate having a service temperature not exceeding 600° C.

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

Abstract: The present disclosure provides systems, processes, articles of manufacture, and compositions that relate to core/shell semiconductor nanowires. Specifically, the disclosure provides a novel semiconductor material, CdSe/ZnS core/shell nanowires, as well as a method of preparation thereof. The disclosure also provides a new continuous flow method of preparing core/shell nanowires, including CdSe/CdS core/shell nanowire and CdSe/ZnS core/shell nanowires.

Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Abstract: A variable resistance memory device may include a first electrode and a second electrode. The device may further include a chalcogenide glass layer between the first electrode and the second electrode. The chalcogenide glass layer may include a chalcogenide glass material co-deposited with a metal material. The device may also include a metal ion source structure between the chalcogenide glass layer and the second electrode. The device may include a buffer layer between the first electrode and the chalcogenide glass layer.

Abstract: A method for fabricating a phase change memory device uses the well-developed semiconductor process to fabricate a larger-size sacrifice beforehand, and next uses a wet etching technology to form a narrowed sacrifice layer having a smaller size, and then removes the narrowed sacrifice layer to form the desired mask pattern, whereby the method can precisely define and easily adjust a smaller-size heater and have a stable fabrication process.

Abstract: The invention relates to a method of manufacturing a I-III-VI2 layer with photovoltaic properties, comprising: deposition of a metal on a substrate to form a contact layer, deposition of a precursor of the photovoltaic layer, on the contact layer, and heat treatment of the precursor with an addition of element VI to form the I-III-VI2 layer. The element VI usually diffuses into the contact layer (MO) during the heat treatment and combines with the metal to form a superficial layer (SUP) on the contact layer. In the method of the invention, the metal deposition comprises a step during which an additional element is added to the metal to form a compound (MO-EA), in the contact layer, acting as a barrier to the diffusion of the element VI, which allows precisely controlling the properties of the superficial layer, particularly its thickness.

Abstract: Improved methods and apparatus for forming thin-film buffer layers of chalcogenide on a substrate web. Solutions containing the reactants for the buffer layer or layers may be dispensed separately to the substrate web, rather than being mixed prior to their application. The web and/or the dispensed solutions may be heated by a plurality of heating elements.

Abstract: A semiconductor memory device includes a first insulating portion. The semiconductor memory device further includes a phase-change material element that contacts the first insulating portion. The semiconductor memory device further includes an electrode that contacts a side surface of the phase-change material element, the side surface of the phase-change material element being not parallel to a top surface of the electrode. The semiconductor memory device further includes a second insulating portion surrounding the phase-change material element.

Abstract: Methods, devices, and systems associated with resistance variable memory device structures can include a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode.

Abstract: A multi-stage method and apparatus for vaporizing and depositing a tellurium containing semiconductor material on a substrate.

Abstract: The present invention relates to a phase-change memory device structure and the materials used. The structure comprises a substrate, a single or multiple sandwich-memory-unit(s), a first electrode, and a second electrode. The sandwich-memory-unit contains an upper barrier layer, a lower barrier layer, and a memory layer therebetween. The thickness of the memory-layer is less than 30 nm. The present invention provides a phase-change memory device with a high Tc and a low volume changing rate during phase-change.

Abstract: A method and apparatus are disclosed in which cadmium chloride is deposited on a cadmium telluride layer while simultaneously heat treating the cadmium telluride layer.

Abstract: An object is to provide a memory including a memory device which includes a layer whose resistance changes and in which reset can be performed by using a reset gate. The object is achieved by a memory device including a pillar-shaped layer whose resistance changes, a reset gate insulating film surrounding the pillar-shaped layer whose resistance changes, and a reset gate surrounding the reset gate insulating film.

Abstract: Methods for producing a semiconductor layer and for producing a photoelectric conversion device, semiconductor raw material are disclosed. An embodiment of the method for producing a semiconductor layer includes: forming a film containing a metal element and an oxygen element; generating oxygen gas by heating the film; and forming a semiconductor layer containing a metal chalcogenide from the film by allowing the metal element to react with a chalcogen element. Another embodiment of the method includes forming a lower film containing a metal element; forming an upper film, which contains the metal element and a substance that contains oxygen, on the lower film; generating oxygen gas by heating the substance; and forming a semiconductor layer containing a metal chalcogenide from the lower film and the upper film by allowing a chalcogen element to react with the metal element in the lower film and the upper film.

Abstract: A quaternary alloy sputtering target composed of copper (Cu), indium (In), gallium (Ga) and selenium (Se), wherein a composition ratio of the respective elements is represented by a formula of CuxIn1-yGaySea (in the formula, 0.84?x?0.98, 0<y?0.5, a=(1/2)x+3/2), and a structure observed via EPMA is configured only from a Cu(In, Ga)Se2 phase without any heterogenous phase of Cu2Se or Cu(In, Ga)3Se5. Provided is a CIGS quaternary alloy sputtering target which is subject to hardly any abnormal discharge even when sputtered for a long period, which is free of any heterogenous phase of Cu2Se or Cu(In, Ga)3Se5 which causes the deterioration in the conversion efficiency of the film after being sputter-deposited, and which can produce a film having superior in-plane uniformity. Additionally provided is a CIGS quaternary alloy sputtering target having a predetermined bulk resistance and a high density.

Abstract: Methods are described for depositing thin films, such as those used in forming a photovoltaic cell or device. In particular embodiments, one or more layers are deposited on a substrate by plasma spraying over the substrate. A grain size of grains in each of the one or more layers is at least approximately two times greater than a thickness of the respective layer. Accordingly, large flat-grained structures are formed in each respective layer, and grain boundaries within each respective layer can be minimized.

Abstract: Some embodiments relate to a resistive random access memory (RRAM). The RRAM includes a RRAM bottom metal electrode, a variable resistance dielectric layer arranged over the RRAM bottom metal electrode, and a RRAM top metal electrode arranged over the variable resistance dielectric layer. A capping layer is arranged over the RRAM top metal electrode. A lower surface of the capping layer and an upper surface of the RRAM top metal electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the RRAM top metal electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the RRAM top metal electrode meets the lower surface of the capping layer.

Abstract: A structure and method of making a thin-film solar cell is provided. A thin-film solar cell includes a substrate, absorber layer and a buffer layer. The absorber layer is deposited by a single-step bulk electrochemical process, or a multi-layer electrochemical process. The buffer layer is deposited by an electrochemical deposition process such as a multi-layer deposition or an atomic layer deposition. The absorber and buffer layers are non-toxic materials which can include sulfur incorporated during the deposition process or incorporated after deposition by an anneal step.

Abstract: Materials and methods for preparing Cu2ZnSnS4 (CZTS) layers for use in thin film photovoltaic (PV) cells are disclosed herein. The CZTS materials are nanoparticles prepared by a colloidal synthesis in the presence of a labile organothiol. The organothiol serves as both a sulphur source and as a capping ligand for the nanoparticles.

Abstract: A method and system for forming chalcogenide semiconductor absorber materials with sodium impurities is provided. The system includes a sodium vaporizer in which a solid sodium source material is vaporized. The sodium vapor is added to reactant gases and/or annealing gases and directed to a furnace that includes a substrate with a metal precursor material. The precursor material reacts with reactant gases such as S-containing gases and Se-containing gases according to various process sequences. In one embodiment, a selenization operation is followed by an annealing operation and a sulfurization operation and the sodium vapor is caused to react with the metal precursor during at least one of the annealing and the sulfurization steps to produce a chalcogenide semiconductor absorber material that includes sodium dopant impurities.

Abstract: Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for forming a Cu—In—Ga layer followed by partial or full selenization. This results in a higher Ga concentration at the back interface. The substrate is then exposed to an aluminum CVD precursor while the substrate is still in the selenization equipment to deposit a thin Al layer. The substrate is then exposed to a Se source to fully convert the absorber layer. This results in a higher Al concentration at the front of the absorber.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array where a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other, wherein the memory cells have a variable resistance element and a non-ohmic element laminated in the direction in which the memory cell layers are laminated and tapered in such a manner that the area in a cross section gradually becomes smaller from the bottom memory cell layer towards the top memory cell layer, and the variable resistance element and the non-ohmic element in the memory cells in a certain memory cell layer are laminated in the same order as the variable resistance element and the non-ohmic element of the memory cells in another memory cell layer.