Amorphous Semiconductor Patents (Class 438/96)
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Patent number: 12255221Abstract: Microbolometer systems and methods are provided herein. For example, an infrared imaging device includes a substrate having contacts and a surface. The surface defines a plane. The infrared imaging device further includes a microbolometer array coupled to the substrate. Each microbolometer of the microbolometer array includes a cross-section having a first section, a second section substantially parallel to the first section, and a third section joining the first section and the second section.Type: GrantFiled: April 5, 2024Date of Patent: March 18, 2025Assignee: Teledyne FLIR Commercial Systems, Inc.Inventors: Eric A. Kurth, Marin Sigurdson, Robert F. Cannata
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Patent number: 12249649Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.Type: GrantFiled: March 22, 2021Date of Patent: March 11, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
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Patent number: 12243952Abstract: The present disclosure provides a double-sided passivated contact cell, where a front side and a rear side of the double-sided passivated contact cell each are provided with a tunnel layer, a doped polysilicon layer, and a passivation layer sequentially from an inside to an outside; and for the doped polysilicon layer at the front side and the doped polysilicon layer at the rear side, one of the doped polysilicon layer at the front side and the doped polysilicon layer at the rear side is a boron and carbon co-doped polysilicon layer, and the other of the doped polysilicon layer at the front side and the doped polysilicon layer at the rear side is a phosphorus and carbon co-doped polysilicon layer. The present disclosure further provides a preparation method of the double-sided passivated contact cell.Type: GrantFiled: September 15, 2022Date of Patent: March 4, 2025Assignee: CHANGZHOU SHICHUANG ENERGY CO., LTDInventors: Changrui Ren, Songbo Yang, Jianwen Dong, Liming Fu
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Patent number: 12218259Abstract: A solar cell capable of preventing short-circuiting during signaling connection and a method for manufacturing the solar cell. A solar cell includes a semiconductor substrate, a first semiconductor layer having a conductivity type different from that of the semiconductor substrate. The first semiconductor layer includes a main functional portion which has a first base end portion on one side in a first direction of the semiconductor substrate over an entire length in a second direction and a plurality of first collecting portions extending from the first base end portion toward the other side in the first direction and on which a first electrode pattern is stacked, and an isolation portion which is formed linearly at an end portion on the other side in the first direction of the semiconductor substrate over an entire length in the second direction and on which the first electrode pattern is not stacked.Type: GrantFiled: February 1, 2023Date of Patent: February 4, 2025Assignee: KANEKA CORPORATIONInventors: Shimpei Okamoto, Junichi Nakamura
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Patent number: 12199202Abstract: The present disclosure pertains to the field of back contact cell technologies, and particularly relates to a hybrid passivation back contact cell and a fabrication method thereof, the hybrid passivation back contact cell including: an N-type doped silicon substrate having a light receiving surface and a back surface, and a first semiconductor layer and a second semiconductor layer which are arranged on the back surface, wherein the second semiconductor layer includes an intrinsic silicon layer and a P-type doped silicon layer sequentially arranged in an outward direction perpendicular to the back surface, and the first semiconductor layer includes a tunneling oxide layer and an N-type doped silicon crystal layer sequentially arranged in the outward direction perpendicular to the back surface.Type: GrantFiled: March 13, 2023Date of Patent: January 14, 2025Assignee: Golden Solar (Quanzhou) New Energy Technology Co., Ltd.Inventor: Kairui Lin
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Patent number: 12142698Abstract: Provided are a solar cell and a photovoltaic module. The solar cell includes: an N-type silicon substrate, where the N-type silicon substrate has a front surface and a rear surface opposite to the front surface; a passivation layer that contains an aluminum oxide material and that is located on the front surface; a first antireflection layer, a second antireflection layer, and a third antireflection layer that are located on a side of the passivation layer away from the substrate and stacked in a direction in which the substrate points to the passivation layer, where the first antireflection layer contains a silicon nitride material, the second antireflection layer contains a silicon oxynitride material; and the third antireflection layer contains a silicon oxide material; a tunneling dielectric layer located on the rear surface; and a doped conductive layer located on the tunneling dielectric layer.Type: GrantFiled: December 6, 2023Date of Patent: November 12, 2024Assignees: ZHEJIANG JINKO SOLAR CO., LTD., JINKO SOLAR (HAINING) CO., LTD.Inventors: Bike Zhang, Bo Zhang, Xinyu Zhang, Jingsheng Jin, Zhaoxuan Liu, Ziqi Guo
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Patent number: 12113159Abstract: Proposed is a dual emission LED chip that emits light to the upper and lower sides of a PN junction, wherein the duel emission LED chip uses the electroluminescent effect of the PN junction including a P layer and an N layer provided below the P layer, and characterized in that the dual emission LED chip emits light in the upward direction of the P layer and the downward direction of the N layer. The dual emission chip can be applied as a single chip to a field requiring dual emission, thereby enabling miniaturization of applied equipment, and increases power efficiency, thereby reducing manufacturing costs. In addition, as the dual emission LED chip can be manufactured through a batch process, a separate packaging process is not required.Type: GrantFiled: December 31, 2019Date of Patent: October 8, 2024Assignee: NANO-XInventors: Du Jin Park, Pil Kuk Jang
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Patent number: 12107111Abstract: An infrared detector with a multi-layer structure based on a CMOS process. A CMOS measuring circuit system and a CMOS infrared sensing structure in the infrared detector are both fabricated by using the CMOS process, and a CMOS manufacturing process comprises a metal interconnection process, a through hole process, an IMD process and an RDL process. In the infrared detector with the multi-layer structure, a first columnar structure comprises at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, a second columnar structure comprises at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, at least one hole-shaped structure is formed in an absorption plate, and the hole-shaped structure at least penetrates a dielectric layer in the absorption plate; and/or, at least one hole-shaped structure is formed in a beam structure.Type: GrantFiled: March 24, 2022Date of Patent: October 1, 2024Assignee: Beijing North Gaoye Technology Co., Ltd.Inventors: Guangjie Zhai, Pei Wu, Hui Pan, Guangqiang Zhai
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Patent number: 11955504Abstract: Microbolometer systems and methods are provided herein. For example, an infrared imaging device includes a substrate having contacts and a surface. The surface defines a plane. The infrared imaging device further includes a microbolometer array coupled to the substrate. Each microbolometer of the microbolometer array includes a cross-section having a first section, a second section substantially parallel to the first section, and a third section joining the first section and the second section.Type: GrantFiled: September 10, 2021Date of Patent: April 9, 2024Assignee: Teledyne FLIR Commercial Systems, Inc.Inventors: Eric A. Kurth, Marin Sigurdson, Robert F. Cannata
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Patent number: 11949031Abstract: The present application belongs to the technical field of solar cells, and relates to a p-type bifacial solar cell with partial rear surface field passivation and a preparation method therefor. The solar cell includes a p-type silicon substrate. At the bottom portion of the p-type silicon substrate are arranged, from top to bottom, a silicon oxide passivation layer, an aluminum oxide passivation layer and a rear side silicon nitride anti-reflection layer. A plurality of boron source-doped layers are embedded in the bottom portion of the p-type silicon substrate. Connected to the bottom of each of the boron source-doped layers is a rear side metal electrode layer, which penetrates each of the silicon oxide passivation layer, the aluminum oxide passivation layer and the rear side silicon nitride anti-reflection layer.Type: GrantFiled: August 13, 2020Date of Patent: April 2, 2024Assignees: Tongwei Solar (Chengdu) Co., Ltd., Tongwei Solar (Meishan) Co., Ltd.Inventors: Pu Wang, Yi Xie, Peng Zhang, Shan Sui
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Patent number: 11824078Abstract: Microbolometer systems and methods are provided herein. For example, an infrared imaging device includes a substrate having contacts and a surface. The surface defines a plane. The infrared imaging device further includes a microbolometer array coupled to the substrate. Each microbolometer of the microbolometer array includes a second having a first dimension that extends in a first direction substantially parallel to the plane and a second dimension that extends in a second direction away from the plane. The first dimension is less than the second dimension. The segment includes a metal layer and a layer formed on a side of the metal layer.Type: GrantFiled: June 7, 2021Date of Patent: November 21, 2023Assignee: Teledyne FLIR, LLCInventors: Eric A. Kurth, Marin Sigurdson, Robert F. Cannata, James L. Dale, Christopher Chan
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Patent number: 11682737Abstract: A method for fabricating a solar cell and the and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, are described. The method can include: providing a solar cell having metal foil having first regions that are electrically connected to semiconductor regions on a substrate at a plurality of conductive contact structures, and second regions; locating a carrier sheet over the second regions; bonding the carrier sheet to the second regions; and removing the carrier sheet from the substrate to selectively remove the second regions of the metal foil.Type: GrantFiled: January 31, 2022Date of Patent: June 20, 2023Assignee: Maxeon Solar Pte. Ltd.Inventors: Pei Hsuan Lu, Benjamin I. Hsia, David Aaron Randolph Barkhouse, Lewis C. Abra, George G. Correos, Boris Bastien
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Patent number: 11594648Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a solar cell can include a substrate having a light-receiving surface and a back surface. A first doped region of a first conductivity type, wherein the first doped region is disposed in a first portion of the back surface. A first thin dielectric layer disposed over the back surface of the substrate, where a portion of the first thin dielectric layer is disposed over the first doped region of the first conductivity type. A first semiconductor layer disposed over the first thin dielectric layer. A second doped region of a second conductivity type in the first semiconductor layer, where the second doped region is disposed over a second portion of the back surface. A first conductive contact disposed over the first doped region and a second conductive contact disposed over the second doped region.Type: GrantFiled: April 20, 2020Date of Patent: February 28, 2023Assignee: SunPower CorporationInventors: Seung Bum Rim, Michael C. Johnson
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Patent number: 11271129Abstract: Methods of fabricating emitter regions of solar cells using surface treatments, and the resulting solar cells, are described herein. In an example, a method of fabricating a solar cell includes treating a surface of a silicon substrate to form a lyophilic area between two lyophobic areas and depositing a liquid phase material containing a silicon material in the lyophilic area to form an emitter region.Type: GrantFiled: October 17, 2017Date of Patent: March 8, 2022Assignee: Total Marketing ServicesInventor: Nils-Peter Harder
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Patent number: 10916672Abstract: A method of making a photovoltaic cell includes providing a metal oxide substrate. The substrate is at least translucent to light. The substrate is directed through a deposition chamber. A semiconductor is deposited over a first major surface of the substrate. The semiconductor includes a polycrystalline p-type layer. The semiconductor is exposed to a chlorine-containing compound or a chlorine molecule. A second electrode layer is provided over the semiconductor.Type: GrantFiled: March 29, 2019Date of Patent: February 9, 2021Assignee: Lucintech Inc.Inventors: Alvin D. Compaan, Victor V. Plotnikov
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Patent number: 10734548Abstract: A free-standing substrate of a polycrystalline nitride of a group 13 element is composed of a plurality of monocrystalline particles having a particular crystal orientation in approximately a normal direction. The free-standing substrate has a top surface and a bottom surface. The polycrystalline nitride of the group 13 element is gallium nitride, aluminum nitride, indium nitride or a mixed crystal thereof and contains zinc at a concentration of 1×1017 atoms/cm3 or more and 1×1020 atoms/cm3 or less.Type: GrantFiled: August 9, 2018Date of Patent: August 4, 2020Assignee: NGK INSULATORS, LTD.Inventors: Katsuhiro Imai, Yoshitaka Kuraoka, Mikiya Ichimura, Takayuki Hirao
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Patent number: 10559520Abstract: A radio frequency integrated circuit (RFIC) includes a bulk semiconductor die. The RFIC also includes a first active/passive device on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die. The RFIC also includes a contact layer on the second-side of the bulk semiconductor die. The RFIC further includes a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.Type: GrantFiled: May 9, 2018Date of Patent: February 11, 2020Assignee: QUALCOMM IncorporatedInventors: Sinan Goktepeli, George Pete Imthurn, Stephen Alan Fanelli
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Patent number: 10087520Abstract: An ion implantation system is provided having an ion source configured to form an ion beam from aluminum iodide. A beamline assembly selectively transports the ion beam to an end station configured to accept the ion beam for implantation of aluminum ions into a workpiece. The ion source has a solid-state material source having aluminum iodide in a solid form. A solid source vaporizer vaporizes the aluminum iodide, defining gaseous aluminum iodide. An arc chamber forms a plasma from the gaseous aluminum iodide, where arc current from a power supply is configured to dissociate aluminum ions from the aluminum iodide. One or more extraction electrodes extract the ion beam from the arc chamber. A water vapor source further introduces water to react residual aluminum iodide to form hydroiodic acid, where the residual aluminum iodide and hydroiodic acid is evacuated from the system.Type: GrantFiled: June 20, 2017Date of Patent: October 2, 2018Assignee: Axcelis Technologies, Inc.Inventors: Dennis Elliott Kamenitsa, Richard J. Rzeszut, Fernando M. Silva, Neil K. Colvin
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Patent number: 9809871Abstract: A method of preparing silver nanoparticles, including silver nanorings. A zinc oxide thin film is formed initially by direct-current sputtering of a zinc target onto a substrate. A silver thin film is then formed by a similar sputtering technique, of a silver target onto the zinc oxide thin film. After that, the silver thin film is subject to an annealing treatment. The temperature, duration and atmosphere of the annealing treatment can be varied to control the average particle size, average distance between particles (density), particle size distribution of the silver nanoparticles. In at least one embodiment, silver nanoparticles of ring structure are produced.Type: GrantFiled: July 24, 2017Date of Patent: November 7, 2017Assignee: King Fahd University of Petroleum and MineralsInventors: Qasem Ahmed Drmosh, Mohammad Kamal Hossain, Nouar Amor Tabet
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Patent number: 9716204Abstract: The invention relates to a method for producing a photovoltaic solar cell having at least one hetero-junction, including the following steps: A) providing a semiconductor substrate having base doping; B) producing a hetero-junction on at least one side of the semiconductor substrate, which hetero-junction has a doped hetero-junction layer and a dielectric tunnel layer arranged indirectly or directly between the hetero-junction layer and the semiconductor substrate; C) heating at least the hetero-junction layer in order to improve the electrical quality of the heterojunction. The invention is characterized in that, in a step D after step C, hydrogen is diffused into the hetero-junction layer and/or to the interface between the tunnel layer and the semiconductor substrate.Type: GrantFiled: September 22, 2014Date of Patent: July 25, 2017Assignee: Fraunhofer-Gesellschaft Zur Förderung der Angewandten Forschung E.V.Inventor: Frank Feldmann
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Patent number: 9397246Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.Type: GrantFiled: May 21, 2015Date of Patent: July 19, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
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Patent number: 9328414Abstract: Disclosed herein is a method of manufacturing a thin film semiconductor device includes the step of forming a silicon thin film including a crystalline structure on a substrate by a plasma CVD process in which a high order silane gas represented by the formula SinH2n+2 (n=2, 3, . . . ) and a hydrogen gas are used as film forming gases.Type: GrantFiled: June 30, 2008Date of Patent: May 3, 2016Assignee: Japan Display Inc.Inventor: Masafumi Kunii
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Patent number: 9206513Abstract: First and second electrodes are apart from each other in a chamber. Plates are disposed on a substrate in the second electrode. Each of the plates comprises first and second parts for supplying first and second gas to a space between the first and second electrodes, respectively, a first supply path for first gas connected to the first part, and a second supply path for second gas connected to the second part. The substrate comprises a heater for the first gas, a first introducing path for introducing the first gas to the first supply path, and a second introducing path for introducing the second gas to the second supply path. The second supply path comprises a mainstream part without the second part and branch parts with the second part. A connecting portion of the second introducing path and the mainstream part is positioned in an adjacent portion of the plates.Type: GrantFiled: November 22, 2010Date of Patent: December 8, 2015Assignee: KYOCERA CorporationInventors: Norikazu Ito, Koichiro Niira, Shinichiro Inaba
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Patent number: 9059341Abstract: A method for manufacturing an interdigitated back contact solar cell. comprising the steps of: (a) providing a silicon substrate doped with a first dopant; (b) doping the rear surface of the silicon substrate with a second dopant in a first pattern; (c) forming a silicon dioxide layer on the rear surface; (d) depositing a silicon-containing paste comprising silicon-containing particles on the silicon dioxide layer in a second pattern; (e) exposing the substrate to a diffusion ambient, wherein the diffusion ambient comprises a third dopant and wherein the third dopant is a counter dopant to the second dopant; (f) heating the substrate in a drive-in ambient; and (g) removing the silicon dioxide layer and the doped silicate glass layer from the silicon substrate, wherein a region doped with the second dopant and a region doped with the third dopant collectively form an interdigitated pattern on the rear surface of the silicon substrate.Type: GrantFiled: January 23, 2014Date of Patent: June 16, 2015Assignee: E I DU PONT DE NEMOURS AND COMPANYInventors: Giuseppe Scardera, Maxim Kelman, Shannon Dugan, Dmitry Poplavskyy, Daniel Aneurin Inns, Karim Lotfi Bendimerad
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Patent number: 9040340Abstract: A method for fabricating a photovoltaic device includes depositing a p-type layer at a first temperature and depositing an intrinsic layer while gradually increasing a deposition temperature to a final temperature. The intrinsic layer deposition is completed at the final temperature. An n-type layer is formed on the intrinsic layer.Type: GrantFiled: November 14, 2011Date of Patent: May 26, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ahmed Abou-Kandil, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Mohamed Saad, Devendra K. Sadana
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Patent number: 9040812Abstract: A photovoltaic device including a substrate; a first electrode placed on the substrate; a second electrode which is placed opposite to the first electrode and which light is incident on; a first unit cell being placed between the first electrode and the second electrode, and including an intrinsic semiconductor layer including crystalline silicon grains making the surface of the intrinsic semiconductor layer toward the second electrode textured; and a second unit cell placed between the first unit cell and the second electrode.Type: GrantFiled: August 23, 2013Date of Patent: May 26, 2015Assignee: Intellectual Discovery Co., Ltd.Inventor: Seung-Yeop Myong
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Patent number: 9040326Abstract: A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching.Type: GrantFiled: August 11, 2014Date of Patent: May 26, 2015Assignee: The Regents of the University of CaliforniaInventors: Hong Zhong, Anurag Tyagi, Kenneth J. Vampola, James S. Speck, Steven P. DenBaars, Shuji Nakamura
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Patent number: 9035311Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.Type: GrantFiled: March 15, 2013Date of Patent: May 19, 2015Assignee: Samsung Display Co., Ltd.Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
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Patent number: 9029688Abstract: Disclosed is a photovoltaic device. The photovoltaic device includes: a substrate; a first electrode placed on the substrate; a second electrode which is placed opposite to the first electrode and which light is incident on; a first unit cell being placed between the first electrode and the second electrode, and including an intrinsic semiconductor layer including crystalline silicon grains making the surface of the intrinsic semiconductor layer toward the second electrode textured; and a second unit cell placed between the first unit cell and the second electrode.Type: GrantFiled: March 24, 2011Date of Patent: May 12, 2015Assignee: Intellectual Discovery Co., Ltd.Inventor: Seung-Yeop Myong
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Patent number: 9029185Abstract: A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductivity type dopant.Type: GrantFiled: May 11, 2012Date of Patent: May 12, 2015Assignee: LG Electronics Inc.Inventors: Kyoungsoo Lee, Seongeun Lee
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Patent number: 9024177Abstract: A solar cell includes a doped layer disposed on a first surface of a semiconductor substrate, a doped polysilicon layer disposed in a first region of a second surface of the semiconductor substrate, a doped area disposed in a second region of the second surface, and an insulating layer covering the doped polysilicon layer and the doped area. The insulating layer has openings exposing portions of the doped polysilicon layer and the doped layer, and the doped polysilicon layer and doped layer are respectively connected to a first electrode and a second electrode through the openings. The semiconductor substrate and the doped layer have a first doping type. One of the doped polysilicon layer and the doping area has a second doping type, and the other one of the doped polysilicon layer and the doping area has the first doping type which is opposite to the second doping type.Type: GrantFiled: April 10, 2013Date of Patent: May 5, 2015Assignee: AU Optronics Corp.Inventors: Peng Chen, Shuo-Wei Liang
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Publication number: 20150101659Abstract: A hetero-contact solar cell has a front side provided for an incidence of solar radiation. The solar cell has an absorber of a crystalline semiconductor material of a first conductivity type, an amorphous semiconductor layer of the first conductivity type doped more highly than the absorber and an electrically conductive, transparent front side conduction layer provided on the amorphous semiconductor layer. A front side contact is provided on the solar cell and has spaced-apart contact structures. An emitter of a second conductivity type opposite to the first conductivity type is provided on a back side. A back side contact is arranged on the back side. The emitter-related absorption losses of the solar cells can be eliminated by the back side contact having a back side contact layer extending over the surface of the back side, and the front side conduction layer containing a specific resistance from 7×10?4 to 50×10?4 ?cm.Type: ApplicationFiled: May 6, 2013Publication date: April 16, 2015Applicant: ROTH & RAU AGInventors: Giuseppe Citarella, Matthias Erdmann, Frank Wuensch, Martin Weinke, Guillaume Wahli
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Patent number: 9006021Abstract: The amorphous silicon film formation method includes forming a seed layer on the surface of a base by heating the base and flowing aminosilane-based gas onto the heated base; and forming an amorphous silicon film on the seed layer by heating the base, supplying silane-based gas containing no amino group onto the seed layer on the surface of the heated base, and thermally decomposing the silane-based gas containing no amino group.Type: GrantFiled: April 26, 2011Date of Patent: April 14, 2015Assignee: Tokyo Electron LimitedInventors: Kazuhide Hasebe, Hiroki Murakami, Akinobu Kakimoto
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Patent number: 8993373Abstract: Methods of doping a solar cell, particularly a point contact solar cell, are disclosed. One surface of a solar cell may require portions to be n-doped, while other portions are p-doped. At least one lithography step can be eliminated by the use of a blanket doping of species having one conductivity and a patterned counterdoping process of species having the opposite conductivity. The areas doped during the patterned implant receive a sufficient dose so as to completely reverse the effect of the blanket doping and achieve a conductivity that is opposite the blanket doping. In some embodiments, counterdoped lines are also used to reduce lateral series resistance of the majority carriers.Type: GrantFiled: May 4, 2012Date of Patent: March 31, 2015Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nicholas Bateman, John Graff
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Patent number: 8993371Abstract: The method of manufacturing a light absorbing layer for a solar cell by performing thermal treatment on a specimen configured to include thin films of one or more of copper, indium, and gallium on a substrate and element selenium, includes steps of: (a) heating a wall of a chamber up to a predefined thin film formation temperature in order to maintain a selenium vapor pressure; (b) mounting the specimen and the element selenium on the susceptor at the room temperature and loading the susceptor in the chamber; and (c) heating the specimen in the lower portion of the susceptor and, at the same time, heating the element selenium in the upper portion of the susceptor, wherein, in the step (c), in order for liquefied selenium not to be condensed on the specimen which is loaded at the room temperature and is not yet heated, the temperature of the element selenium and the specimen loaded in the chamber are individually controlled, so that the selenium vapor pressure of an inner space of the chamber does not exceed aType: GrantFiled: August 4, 2011Date of Patent: March 31, 2015Assignee: Semics Inc.Inventor: Seong Hoon Song
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Publication number: 20150087106Abstract: In various embodiments, photovoltaic devices incorporate discontinuous passivation layers (i) disposed between a thin-film absorber layer and a partner layer, (ii) disposed between the partner layer and a front contact layer, and/or (iii) disposed between a back contact layer and the thin-film absorber layer.Type: ApplicationFiled: September 22, 2014Publication date: March 26, 2015Inventors: Markus Eberhard Beck, Timothy J. Nagle, Sourav Roger Basu
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Publication number: 20150087108Abstract: This disclosure describes systems and methods for making at least a portion of a photovoltaic device. This may include a method of manufacturing, an optimization procedure and an apparatus for the PECVD (plasma enhanced chemical vapor deposition) of thin films over large area substrates. In particular, the system may be used to deposit thin film silicon material for photovoltaic (PV) applications. The photovoltaic device may be achieved by a combination of plasma chamber design (e.g., inter-electrode separation) and plasma process parameters (e.g., pressure, applied RF voltage, etc.) to optimize the doped and/or intrinsic layers of the solar cell (e.g., p-i-n junction).Type: ApplicationFiled: September 26, 2014Publication date: March 26, 2015Inventors: Elena Lorena Salabas, Eduard Kuegler, Chloe Prigent, Aurel Salabas
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Patent number: 8987738Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.Type: GrantFiled: September 27, 2012Date of Patent: March 24, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Hirose, Naoto Kusumoto
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Patent number: 8987856Abstract: A photodiode, a light sensor and a fabricating method thereof are disclosed. An n-type semiconductor layer and an intrinsic semiconductor layer of the photodiode respectively comprise n-type amorphous indium gallium zinc oxide (IGZO) and intrinsic IGZO. The oxygen content of the intrinsic amorphous IGZO is greater than the oxygen content of the n-type amorphous IGZO. A light sensor comprise the photodiode is also disclosed.Type: GrantFiled: March 29, 2012Date of Patent: March 24, 2015Assignee: E Ink Holdings Inc.Inventors: Fang-An Shu, Yao-Chou Tsai, Ted-Hong Shinn
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Patent number: 8987588Abstract: A solar cell and method of fabricating the same are provided. The substrate of the solar cell has heavily-doped regions and lightly-doped regions. The anode and the cathode are disposed on the back surface of the substrate, and thus the amount of incident light on the front surface of the substrate is increased. The anode and the cathode are in contact with the heavily doped regions to form selective emitter structure, and thus the contact resistance is reduced. The lightly-doped regions, which are not in contact with the anode and the cathode, have lower saturation current, and thus recombination of hole-electron pairs is reduced, and absorption of infrared light is increased.Type: GrantFiled: April 15, 2013Date of Patent: March 24, 2015Assignee: AU Optronics Corp.Inventors: Peng Chen, Shou-Wei Liang
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Patent number: 8980683Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.Type: GrantFiled: July 3, 2014Date of Patent: March 17, 2015Assignee: SK Hynix Inc.Inventors: Min Yong Lee, Young Ho Lee, Seung Beom Baek, Jong Chul Lee
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Patent number: 8980661Abstract: Provided is a method for manufacturing a light emitting device comprising a light emitting element and an optical part, the method comprising the steps of (i) forming a hydroxyl film on a bonding surface of each of the light emitting element and the optical part by an atomic layer deposition, and (ii) bonding the bonding surfaces of the light emitting element and the optical part with each other, each of the bonding surfaces having the hydroxyl film formed thereon, wherein a substep is repeated at least one time in the step (i), in which substep a first raw material gas and a second raw material gas are sequentially supplied onto the bonding surfaces of the light emitting element and the optical part, and wherein the bonding of the bonding surfaces in the step (ii) is performed without a heating treatment.Type: GrantFiled: April 28, 2014Date of Patent: March 17, 2015Assignee: Nichia CorporationInventors: Masatsugu Ichikawa, Masahiko Sano, Daisuke Sanga, Toru Takasone, Shunsuke Minato
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Patent number: 8981513Abstract: An electrical circuit includes a solar cell that has a photovoltaically active front side and a back side. An electronic or micromechanical component is arranged on the back side of the solar cell and is electrically connected to the photovoltaically active front side of the solar cell by a contact-making structure. The electrical circuit also includes a transparent first protective layer that is arranged on the photovoltaically active front side of the solar cell. The contact-making structure has a first contact-making section that is arranged on a front side of the first protective layer facing away from the solar cell.Type: GrantFiled: December 26, 2013Date of Patent: March 17, 2015Assignee: Robert Bosch GmbHInventors: Ricardo Ehrenpfordt, Mathias Bruendel, Daniel Pantel, Frederik Ante, Johannes Kenntner
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Patent number: 8975172Abstract: [Object] To provide a method for manufacturing a solar cell element including a semiconductor substrate that includes a high-concentration dopant layer located near the surface of the semiconductor substrate and a low-concentration dopant layer located more inside the semiconductor substrate than the high-concentration dopant layer. [Solving Means] A method includes heating a semiconductor substrate having a first conductivity type in a first atmosphere which contains a dopant having a second conductivity type and which has a first dopant concentration; heating in a second atmosphere the semiconductor substrate heated in the first atmosphere, the second atmosphere having a second dopant concentration less than the first dopant concentration; and heating in a third atmosphere the semiconductor substrate heated in the second atmosphere, the third atmosphere having a third dopant concentration greater than the second dopant concentration.Type: GrantFiled: September 27, 2007Date of Patent: March 10, 2015Assignee: KYOCERA CorporationInventors: Rui Yatabe, Kenichi Kurobe, Yosuke Inomata
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Publication number: 20150063543Abstract: A radiation detector may include: a first photoconductor layer including a plurality of photosensitive particles; and/or a second photoconductor layer on the first photoconductor layer, and including a plurality of crystals obtained by crystal-growing photosensitive material. At least some of the plurality of photosensitive particles of the first photoconductor layer may fill gaps between the plurality of crystals of the second photoconductor layer. A method of manufacturing a radiation detector may include: forming a first photoconductor layer by applying paste, including solvent mixed with a plurality of photosensitive particles, to a first substrate; forming a second photoconductor layer by crystal-growing photosensitive material on a second substrate; pressing the crystal-grown second photoconductor layer on the first photoconductor layer that is applied to the first substrate; and/or removing the solvent in the first photoconductor layer via a drying process.Type: ApplicationFiled: September 1, 2014Publication date: March 5, 2015Inventors: Seung-hyup LEE, Sun-il KIM, Young KIM, Chang-jung KIM
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Publication number: 20150062088Abstract: A method of forming a photo sensor includes the following steps. A substrate is provided, and a first electrode is formed on the substrate. A first silicon-rich dielectric layer is formed on the first electrode for sensing an infrared ray, wherein the first silicon-rich dielectric layer comprises a silicon-rich oxide layer, a silicon-rich nitride layer, or a silicon-rich oxynitride layer. A second silicon-rich dielectric layer is formed on the first silicon-rich dielectric layer for sensing visible light beams, wherein the second silicon-rich dielectric layer comprises a silicon-rich oxide layer, a silicon-rich nitride layer, or a silicon-rich oxynitride layer. A second electrode is formed on the second silicon-rich dielectric layer.Type: ApplicationFiled: November 7, 2014Publication date: March 5, 2015Inventors: An-Thung Cho, Chia-Tien Peng, Hung-Wei Tseng, Cheng-Chiu Pai, Yu-Hsuan Li, Chun-Hsiun Chen, Wei-Ming Huang
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Patent number: 8969121Abstract: A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductivity type dopant.Type: GrantFiled: May 11, 2012Date of Patent: March 3, 2015Assignee: LG Electronics Inc.Inventors: Kyoungsoo Lee, Seongeun Lee
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Patent number: 8963273Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.Type: GrantFiled: April 7, 2014Date of Patent: February 24, 2015Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Michel Marty, François Roy, Jens Prima
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Patent number: 8956906Abstract: The invention relates to a method and a device for producing a semiconductor layer. The problem addressed is that of increasing the deposition rate of the layer constituents and significantly improving the efficiency of a resulting solar cell. At the same time, the material costs are intended to be reduced. The problem is solved by virtue of the fact that, in a vacuum chamber, metal evaporator sources release Cu, In and/or Ga or the chalcogenide compounds, the latter are focused as metal vapor jets onto the substrate, and Se and/or S emerge(s) in an ionized fashion from a chalcogen low-energy wide-beam ion source and this beam is focused onto the surface of the substrate in such a way that it overlaps the metal vapor jets. A device for carrying out the method is described.Type: GrantFiled: February 22, 2010Date of Patent: February 17, 2015Assignee: Solarion AGInventors: Hendrik Zachmann, Karsten Otte, Horst Neumann, Frank Scholze, Lutz Pistol
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Publication number: 20150040974Abstract: The method of manufacturing a solar cell, which comprises a semiconductor substrate (1) with a first side (1a) and an opposed second side (1b), at which first side an active region doped with charge carriers of a first conductivity type is defined selectively. The method comprises introducing said charge carriers into the substrate (1) on said first side (1a) by ion implantation in an implantation step at a dose level that induces surface amorphization, therewith forming an amorphized region. Thereafter, material in part of the amorphized region is selectively recrystallized to define a first, recrystallized subregion (5), a remaining part of the amorphized region defining a second subregion (15). Subsequently, the recrystallized material of the first subregion (5) is at least partially removed, therewith creating the selectively defined active region and inducing a surface topology between the at least partially removed first subregion (5) and the second subregion (15).Type: ApplicationFiled: May 3, 2013Publication date: February 12, 2015Inventor: Ronald Cornelis Gerard Naber