Amorphous Semiconductor Patents (Class 438/96)
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Publication number: 20130196466Abstract: A method and apparatus for manufacturing a multi-layered structure includes forming a crystalline layer of a material by depositing an amorphous layer of the material on a heated substrate.Type: ApplicationFiled: January 30, 2013Publication date: August 1, 2013Applicant: FIRST SOLAR, INCInventor: FIRST SOLAR, INC
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Publication number: 20130186455Abstract: A method for forming single crystal or large-crystal-grain thin-film layers deposits a thin-film amorphous, nanocrystalline, microcrystalline, or polycrystalline layer, and laser-heats a seed spot having size on the order of a critical nucleation size of the thin-film layer. The single-crystal seed spot is extended into a single-crystal seed line by laser-heating one or more crystallization zones adjacent to the seed spot and drawing the zone across the thin-film layer. The single-crystal seed line is extended across the thin-film material layer into a single-crystal layer by laser-heating an adjacent linear crystallization zone and drawing the crystallization zone across the thin-film layer. Photovoltaic cells may be formed in or on the single-crystal layer. Tandem photovoltaic devices may be formed using one or several iterations of the method. The method may also be used to form single-crystal semiconductor thin-film transistors, such as for display devices, or to form single-crystal superconductor layers.Type: ApplicationFiled: February 21, 2012Publication date: July 25, 2013Inventors: Jifeng Liu, Xiaoxin Wang
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Publication number: 20130174899Abstract: In order to improve a thin film solar cell with an amorphous silicon absorber layer being in single or in tandem configuration, the addressed absorber layer of a-Si:H is manufactured by plasma enhanced vapor deposition in an RF-SiH4 plasma, wherein the deposition is performed at at least one of at the process pressure below 0.5 mbar and of at an RF power density below 370 W/14000 cm2.Type: ApplicationFiled: September 2, 2011Publication date: July 11, 2013Applicant: TEL SOLAR AGInventor: Marian Fecioru-Morariu
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Patent number: 8476097Abstract: A method for manufacturing a thin-film solar cell includes providing a first conducting layer on a substrate that has an area at least 0.75 m2. The first conducting layer is located in a deposition portion of the area. An ultraviolet laser beam is applied through a lens to the first conducting layer. Portions of the first conducting layer are scribed form a trench through the layer. The lens focuses the beam and has a focal length at least 100 mm. The focused beam includes an effective portion effective for the scribing and an ineffective portion ineffective for the scribing. The substrate sags and the first conducting layer remains in the effective portion of the focused beam across the area during the step of applying. One or more active layers are provided on the first conducting layer. A second conducting layer is provided on the one or more active layers.Type: GrantFiled: August 28, 2008Date of Patent: July 2, 2013Assignee: Oerlikon Solar AG, TrubbachInventor: Jiri Springer
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Patent number: 8476100Abstract: A method of forming thin film solar cell includes the following steps. A substrate is provided, and a plurality of first electrodes are formed on the substrate. A printing process is performed to print a light-absorbing material on the substrate and the first electrodes to form a plurality of light-absorbing patterns. Each of the light-absorbing patterns corresponds to two adjacent first electrodes, partially covers the two adjacent first electrodes, and partially exposes the two adjacent first electrodes. A plurality of second electrodes are formed on the light-absorbing patterns.Type: GrantFiled: March 25, 2010Date of Patent: July 2, 2013Assignee: AU Optronics Corp.Inventors: Kuang-Ting Chou, Han-Tang Chou, Ming-Yuan Huang, Han-Tu Lin
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Publication number: 20130160847Abstract: A solar cell includes a solar cell substrate including a principal surface on which a p-type surface and an n-type surface are exposed, a p-side electrode formed on the p-type surface and including a first linear portion linearly extending in a first direction, and an n-side electrode formed on the n-type surface and including a second linear portion linearly extending in the first direction and arranged next to the first linear portion in a second direction orthogonal to the first direction. Corners of a tip end of at least one of the first and second linear portions are formed in a chamfered shape.Type: ApplicationFiled: February 21, 2013Publication date: June 27, 2013Applicant: SANYO ELECTRIC CO., LTD.Inventor: Sanyo Electric Co., Ltd.
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Publication number: 20130139875Abstract: The present invention discloses a thin-film solar cell and a method for forming the same. The thin-film solar cell includes a substrate and a semiconductor layer containing a P-type crystalline silicon layer over the substrate, a first I-type crystalline silicon layer on the P-type crystalline silicon layer, a first N-type crystalline silicon layer on the first I-type crystalline silicon layer, a second I-type crystalline silicon layer on the first N-type crystalline silicon layer and a second N-type crystalline silicon layer on the second I-type crystalline silicon layer. Wherein, the semiconductor layer is formed with additional I-type and N-type crystalline silicon layers, thereby enhancing the photoelectric conversion efficiency of the thin-film solar cell.Type: ApplicationFiled: February 27, 2012Publication date: June 6, 2013Inventors: Chia-Ling LEE, Chien-Chung BI
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Publication number: 20130139884Abstract: A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductive type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductive type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductive type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductive type dopant.Type: ApplicationFiled: May 11, 2012Publication date: June 6, 2013Applicant: LG ELECTRONICS INC.Inventors: Kyoungsoo LEE, Seongeun LEE
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Patent number: 8455754Abstract: A solar cell element and method of manufacturing same is disclosed. A reverse-conductive-type layer is formed on at least one part of a first surface side of a one-conductive-type semiconductor substrate. A conductive layer is formed on the reverse-conductive-type layer. A contact region for electrically connecting the conductive layer and the one-conductive-type semiconductor substrate is formed by heating and melting at least one part of the conductive layer. The solar cell element can be manufactured without conducting complicated treatments, such as removal by etching and re-growing of a silicon thin layer.Type: GrantFiled: April 27, 2009Date of Patent: June 4, 2013Assignee: KYOCERA CorporationInventors: Koichiro Niira, Manabu Komoda
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Publication number: 20130137209Abstract: A method of manufacturing a solar cell includes: forming an electrode on a first main surface of a photoelectric conversion body through screen printing; and then forming an electrode on a second main surface of the photoelectric conversion body, located on the opposite side from the first main surface, through screen printing, the photoelectric conversion body including a p- type or n-type semiconductor substrate and an amorphous silicon layer stacked on one surface of the semiconductor substrate on the first main surface side and having the opposite conductivity from the semiconductor substrate, such that the first main surface of the photoelectric conversion body comprises a pn junction.Type: ApplicationFiled: January 25, 2013Publication date: May 30, 2013Applicant: SANYO ELECTRIC CO., LTD.Inventor: SANYO ELECTRIC CO., LTD.
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Publication number: 20130126850Abstract: A radiation detector that includes a first scintillator layer, an organic photoelectric conversion layer and a substrate is provided. The first scintillator layer, the organic photoelectric conversion layer and the substrate are layered along a radiation incident direction. The first scintillator layer contains a blend of a first phosphor material that is mainly sensitive to low energy radiation in incident radiation and converts the radiation into light of a first wavelength, and a second phosphor material that is more sensitive to high energy than low energy radiation in the radiation and converts the radiation into light of a second wavelength different from the first wavelength. The organic photoelectric conversion layer is configured by disposing a plurality of first light detection sensors and a plurality of second light detection sensors in the same plane.Type: ApplicationFiled: January 18, 2013Publication date: May 23, 2013Applicant: FUJIFILM CORPORATIONInventor: FUJIFILM CORPORATION
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Publication number: 20130112250Abstract: A process for the formation of at least one aluminum p-doped surface region of a semiconductor substrate comprising the steps: (1) providing a semiconductor substrate, (2) applying and drying an aluminum paste on at least one surface area of the semiconductor substrate, (3) firing the dried aluminum paste, and (4) removing the fired aluminum paste with water, wherein the aluminum paste employed in step (2) includes particulate aluminum, an organic vehicle and 3 to 20 wt. % of glass frit, based on total aluminum paste composition.Type: ApplicationFiled: November 2, 2012Publication date: May 9, 2013Applicant: E I DU PONT DE NEMOURS AND COMPANYInventor: E I DU PONT DE NEMOURS AND COMPANY
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Publication number: 20130112264Abstract: Embodiments of the present invention relate to methods for forming a doped amorphous silicon oxide layer utilized in thin film solar cells. In one embodiment, a method for forming a doped p-type amorphous silicon containing layer on a substrate includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and a carbon and oxygen containing gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas between about 5 and about 15, wherein a volumetric flow ratio of the carbon and oxygen containing gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 10 percent and about 50 percent; and maintaining a process pressure of the gas mixture within the processing chamber at between about 1 Torr and about 10 Torr while forming a doped p-type amorphous silicon containing layer.Type: ApplicationFiled: November 8, 2011Publication date: May 9, 2013Applicant: APPLIED MATERIALS, INC.Inventors: Dapeng Wang, Yong Kee Chae
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Publication number: 20130113059Abstract: A photovoltaic device includes a semiconductor substrate; an amorphous first conductive semiconductor layer on a first region of a first surface of the semiconductor substrate and containing a first impurity; an amorphous second conductive semiconductor layer on a second region of the first surface of the semiconductor substrate and containing a second impurity; and a gap passivation layer located between the first region and the second region on the semiconductor substrate, wherein the first conductive semiconductor layer is also on the gap passivation layer.Type: ApplicationFiled: August 7, 2012Publication date: May 9, 2013Inventors: Nam-Kyu Song, Min-Seok Oh, Yun-Seok Lee, Cho-Young Lee
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Patent number: 8435825Abstract: A photovoltaic device that includes a substrate and a nanowall structure disposed on the substrate surface. The device also includes at least one layer conformally deposited over the nanowall structure. The conformal layer(s) is at least a portion of a photoactive junction. A method for making a photovoltaic device includes generating a nanowall structure on a substrate surface and conformally depositing at least one layer over the nanowall structure thereby forming at least one photoactive junction. A solar panel includes at least one photovoltaic device based on a nanowall structure. The solar panel isolates such devices from its surrounding atmospheric environment and permits the generation of electrical power. Optoelectronic device may also incorporate a photovoltaic device based on a nanowall structure.Type: GrantFiled: July 14, 2011Date of Patent: May 7, 2013Assignee: General Electric CompanyInventors: Bastiaan Arie Korevaar, Loucas Tsakalakos, Joleyn Eileen Brewer
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Patent number: 8431928Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.Type: GrantFiled: December 15, 2011Date of Patent: April 30, 2013Assignee: The University of Utah Research FoundationInventors: Ashutosh Tiwari, Makarand Karmarkar, Nathan Wheeler Gray
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Publication number: 20130084675Abstract: A photovoltaic device capable of improving an output characteristic is provided. The photovoltaic device includes an n-type single-crystal silicon substrate, a p-type amorphous silicon substrate, and a substantially intrinsic i-type amorphous silicon layer disposed between the n-type single-crystal silicon substrate and the p-type amorphous silicon layer. The i-type amorphous silicon layer includes: a first section which is located on the n-type single-crystal silicon substrate side, and which has an oxygen concentration equal to or below 1020 cm?3; and a second section which is located on the p-type amorphous silicon layer side, and which has an oxygen concentration equal to or above 1020 cm?3.Type: ApplicationFiled: November 21, 2012Publication date: April 4, 2013Applicant: SANYO ELECTRIC CO., LTD.Inventor: Sanyo Electric Co., Ltd.
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Patent number: 8410354Abstract: Higher conversion efficiency and productivity of photoelectric conversion devices. A semiconductor layer including a first and second crystal regions grown in the layer-deposition direction is provided between an impurity semiconductor layer containing an impurity element imparting one conductivity type and an impurity semiconductor layer containing an impurity element imparting a conductivity type opposite to the one conductivity type. The first crystal region is grown from the interface between one of the impurity semiconductor layers and the semiconductor layer. The second crystal region is grown toward the interface between the semiconductor layer and the other of the impurity semiconductor layers from a position which is away from the interface between the one of the impurity semiconductor layers and the semiconductor layer. The semiconductor layer including the first and second crystal regions which exist in an amorphous structure forms the main part of a region for photoelectric conversion.Type: GrantFiled: May 4, 2009Date of Patent: April 2, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8409887Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.Type: GrantFiled: February 26, 2010Date of Patent: April 2, 2013Assignee: Samsung Display Co., Ltd.Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
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Patent number: 8398873Abstract: There is provided a thin-sheet glass substrate laminate which is approximately 100% impermeable to gas or vapor and has a high transparency and a thin thickness, and a method of manufacturing the same. A support is temporarily attached to one surface of a glass substrate after forming a pattern P on the one surface, the glass substrate is thinned by etching another surface of the glass substrate, a film base is temporarily attached to the etched another surface, the temporarily attached support is peeled off from the one surface of the glass substrate, the one surface from which the support is peeled off is laminated to a surface of a cover glass, and the temporarily attached film base is peeled off from the another surface.Type: GrantFiled: February 1, 2011Date of Patent: March 19, 2013Assignee: Micro Technology Co., Ltd.Inventors: Minoru Yoshikawa, Tomohiro Yachida
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Publication number: 20130065356Abstract: Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus avoids deposition on windows that couple microwave energy to deposition species. The apparatus includes a microwave applicator with one or more conduits that carry deposition species. The applicator transfers microwave energy to the deposition species to energize them to a reactive state. The conduits physically isolate deposition species that would react or otherwise combine to form a thin film material at the point of microwave power transfer and deliver the microwave-excited species to a deposition chamber. Supplemental material streams may be delivered to the deposition chamber without passing through the microwave applicator and may combine with deposition species exiting the conduits to form a thin film material. Precursors for the microwave-excited deposition species include fluorinated forms of silicon.Type: ApplicationFiled: September 24, 2012Publication date: March 14, 2013Applicant: Ovshinsky Innovation LLCInventor: Stanford R. Ovshinsky
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Patent number: 8395043Abstract: A solar cell includes a photoactive, semiconductive absorber layer configured to generate excess charge carriers of opposed polarity by light incident on a front of the absorber layer during operation. The absorber layer is configured to separate and move, via at least one electric field formed in the absorber layer, the photogenerated excess charge carriers of opposed polarity over a minimal effective diffusion length Leff,min. The absorber layer has a thickness Lx of 0<Lx?Leff,min. First contact elements are configured to remove the excess charge carriers of a first polarity on a rear of the absorber layer. Second contact elements are configured remove the excess charge carriers of a second polarity on the rear of the absorber layer. At least one undoped, electrically insulating second passivation region is disposed in an alternating, neighboring arrangement with a first passivation region on the rear of the absorber layer.Type: GrantFiled: June 1, 2010Date of Patent: March 12, 2013Assignee: Helmholtz-Zentrum Berlin fuer Materialien und Energie GmbHInventors: Rolf Stangl, Bernd Rech
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Publication number: 20130048071Abstract: A thin film amorphous silicon solar cell may have front contact between a hydrogenated amorphous silicon layer and a transparent conductive oxide layer. The cell may include a layer of a refractory metal, chosen among the group composed of molybdenum, tungsten, tantalum and titanium, of thickness adapted to ensure a light transmittance of at least 80%, interposed therebetween, before growing by PECVD a hydrogenated amorphous silicon p-i-n light absorption layer over it. A refractory metal layer of just about 1 nm thickness may effectively shield the oxide from the reactive plasma, thereby preventing a diffused defect when forming the p.i.n. layer that would favor recombination of light-generated charge carriers.Type: ApplicationFiled: August 29, 2012Publication date: February 28, 2013Applicant: STMicroelectronics S.r.I.Inventors: Salvatore LOMBARDO, Cosimo GERARDI, Sebastiano RAVESI, Marina FOTI, Cristina TRINGALI, Stella LOVERSO, Nicola COSTA
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Patent number: 8383434Abstract: A method for manufacturing a thin film transistor having high electric characteristics with high productivity. In the method for forming a channel region of a dual-gate thin film transistor including a first gate electrode and a second gate electrode which faces the first gate electrode with the channel region provided therebetween, a first microcrystalline semiconductor film is formed under a first condition for forming a microcrystalline semiconductor film in which a space between crystal grains is filled with an amorphous semiconductor, and a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a second condition for promoting crystal growth.Type: GrantFiled: February 4, 2011Date of Patent: February 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Toshiyuki Isa
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Patent number: 8383452Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.Type: GrantFiled: January 31, 2011Date of Patent: February 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tomonori Aoyama, Kiyotaka Miyano, Yusuke Oshiki
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Patent number: 8367456Abstract: A method for the production of a tile containing a photovoltaic cell including the steps of: producing a ceramic base body having one or more through holes and a water absorption equal to or less than 0.5 wt %; depositing on a surface of that ceramic base body an electro-conductive layer made of Ag or Ag—Al; a plurality of active layers; and a layer of electro-conductive material with grid-like structure, wherein the plurality of active layers includes in succession an n-type layer, a photo-active layer and a p-type layer.Type: GrantFiled: March 30, 2007Date of Patent: February 5, 2013Assignee: Consorzio Universitario per la Gestione del Centro di Ricerca e Sperimentazione per l'Industria Ceramica-Centro CeramicoInventors: Arturo Salomoni, Ivan Stamenkovic, Sandra Fazio, Barbara Mazzanti, Giovanni Ridolfi, Emanuele Centurioni, Daniele Iencinella, Maria Grazia Busana
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Patent number: 8367924Abstract: The present invention relates to methods and apparatuses for providing a buried insulator isolation for solar cell contacts. According to certain aspects, the invention places a buried oxide under the emitter of a polysilicon emitter solar cell. The oxide provides an excellent passivation layer over most of the surface. Holes in the oxide provide contact areas, increasing the current density to enhance efficiency. The oxide isolates the contacts from the substrate, achieving the advantage of a selective emitter structure without requiring deep diffusions. The oxide further enables use of screen printing on advanced shallow emitter cells. Positioning of the grid lines close to the openings also enables use of a very thin emitter to maximize blue response.Type: GrantFiled: January 27, 2009Date of Patent: February 5, 2013Assignee: Applied Materials, Inc.Inventors: Peter Borden, Li Xu
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Publication number: 20130019944Abstract: A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.Type: ApplicationFiled: July 21, 2011Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bahman Hekmatshoar-Tabari, Marinus Hopstaken, Dae-Gyu Park, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
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Patent number: 8357562Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.Type: GrantFiled: January 28, 2011Date of Patent: January 22, 2013Assignee: Fairchild Semiconductor CorporationInventor: Jifa Hao
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Patent number: 8354585Abstract: A solar cell includes: a semiconductor substrate having a first surface and a second surface opposite the first surface; uneven patterns disposed on at least one of the first surface and the second surface of the semiconductor substrate; a first impurity layer disposed on the uneven patterns and which includes a first part having a first doping concentration and a second part having a second doping concentration greater than the first doping concentration; and a first electrode which contacts the second part of the first impurity layer and does not contact the first part of the first impurity layer.Type: GrantFiled: October 20, 2009Date of Patent: January 15, 2013Assignees: Samsung SDI Co., Ltd., Samsung Display Co., Ltd.Inventors: Min-Seok Oh, Byoung-Kyu Lee, Min Park, Czang-Ho Lee, Myung-Hun Shin, Yuk-Hyun Nam, Seung-Jae Jung, Mi-Hwa Lim, Joon-Young Seo
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Patent number: 8349644Abstract: A method for producing a backside contact of a single p-n junction photovoltaic solar cell is provided. The method includes the steps of: providing a p-type substrate having a back surface; providing a plurality of p+ diffusion regions at the back surface of the substrate; providing a plurality of n+ diffusion regions at the back surface of the substrate in an alternate pattern with the p+ diffusion regions; providing an oxide layer over the p+ and n+ regions; providing an insulating layer over the back surface of the substrate; providing at least one first metal contact at the back surface for the p+ diffusion regions; and providing at least one second metal contact at the back surface for the n+ diffusion regions.Type: GrantFiled: October 20, 2008Date of Patent: January 8, 2013Assignee: e-Cube Energy Technologies, Ltd.Inventors: Wei Shan, Xiao-Dong Xiang
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Patent number: 8349643Abstract: A photovoltaic device capable of improving an output characteristic is provided. The photovoltaic device includes an n-type single-crystal silicon substrate, a p-type amorphous silicon substrate, and a substantially intrinsic i-type amorphous silicon layer disposed between the n-type single-crystal silicon substrate and the p-type amorphous silicon layer. The i-type amorphous silicon layer includes: a first section which is located on the n-type single-crystal silicon substrate side, and which has an oxygen concentration equal to or below 1020 cm?3; and a second section which is located on the p-type amorphous silicon layer side, and which has an oxygen concentration equal to or above 1020 cm?3.Type: GrantFiled: January 10, 2011Date of Patent: January 8, 2013Assignee: Sanyo Electric Co., Ltd.Inventor: Akira Terakawa
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Patent number: 8343792Abstract: An improved method for manufacturing a lateral germanium detector is disclosed. A detector window is opened through an oxide layer to expose a doped single crystalline silicon layer situated on a substrate. Next, a single crystal germanium layer is grown within the detector window, and an amorphous germanium layer is grown on the oxide layer. The amorphous germanium layer is then polished to leave only a small portion around the single crystal germanium layer. A dielectric layer is deposited on the amorphous germanium layer and the single crystal germanium layer. Using resist masks and ion implants, multiple doped regions are formed on the single crystal germanium layer. After opening several oxide windows on the dielectric layer, a refractory metal layer is deposited on the doped regions to form multiple germanide layers.Type: GrantFiled: October 27, 2008Date of Patent: January 1, 2013Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Daniel N. Carothers, Craig M. Hill, Andrew T. S. Pomerene, Vu A. Vu, Robert Kamocsai, Timothy J. Conway
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Patent number: 8344241Abstract: Nanostructures and photovoltaic structures are disclosed. A nanostructure according to one embodiment includes an array of nanocables extending from a substrate, the nanocables in the array being characterized as having a spacing and surface texture defined by inner surfaces of voids of a template; an electrically insulating layer extending along the substrate; and at least one layer overlaying the nanocables. A nanostructure according to another embodiment includes a substrate; a portion of a template extending along the substrate, the template being electrically insulative; an array of nanocables extending from the template, portions of the nanocables protruding from the template being characterized as having a spacing, shape and surface texture defined by previously-present inner surfaces of voids of the template; and at least one layer overlaying the nanocables.Type: GrantFiled: August 22, 2006Date of Patent: January 1, 2013Assignees: Q1 Nanosystems Corporation, The Regents of the University of CaliforniaInventors: Ruxandra Vidu, Brian Argo, John Argo, Pieter Stroeve, Jie-Ren Ku
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Publication number: 20120325284Abstract: The photovoltaic cell comprises, deposited on a transparent substrate in the following order: a first conductive oxide layer; a first p-i-n junction; a second p-i-n junction; a second conductive oxide layer, wherein said first conductive oxide layer is substantially transparent and comprises a low-pressure chemical vapor deposited ZnO layer; and said second conductive oxide layer comprises an at least partially transparent low-pressure chemical vapor deposited ZnO layer; and wherein said first p-i-n junction comprises in the following order: a layer of p-doped a-Si:H deposited using PECVD and having at its end region facing toward said second p-i-n junction a higher band gap than at its end region facing toward said first conductive oxide layer; a buffer layer of a-Si:H deposited using PECVD without voluntary addition of a dopant; a layer of substantially intrinsic a-Si:H deposited using PECVD; a first layer of n-doped a-Si:H deposited using PECVD; and a layer of n-doped ?c-Si:H deposited using PECVD; and wheType: ApplicationFiled: October 28, 2010Publication date: December 27, 2012Applicant: OERLIKON SOLAR AG, TRUEBBACHInventors: Tobias Roschek, Hanno Goldbach
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Patent number: 8338221Abstract: A method for manufacturing a thin film type solar cell is disclosed, which is capable of reducing degradation of solar cell by decreasing the number of dangling bonding sites or SiH2 bonding sites existing in amorphous silicon owing to an optimal content ratio of ingredient gases, an optimal chamber pressure, or an optimal substrate temperature during a process for depositing an I-type semiconductor layer of amorphous silicon by a plasma CVD method, the method comprising forming a front electrode layer on a substrate; sequentially depositing P-type, I-type, and N-type semiconductor layers on the front electrode layer; and forming a rear electrode layer on the N-type semiconductor layer, wherein the process for forming the I-type semiconductor layer comprises forming an amorphous silicon layer by the plasma CVD method under such circumstances that at least one of the aforementioned conditions is satisfied, for example, a content ratio of silicon-containing gas to hydrogen-containing gas is within a range betweType: GrantFiled: December 1, 2009Date of Patent: December 25, 2012Assignee: Jusung Engineering Co., Ltd.Inventors: Chang Ho Lee, Hyung Dong Kang, Hyun Ho Lee, Yong Hyun Lee, Seon Myung Kim
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Patent number: 8335106Abstract: To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.Type: GrantFiled: May 3, 2010Date of Patent: December 18, 2012Assignee: Elpida Memory, Inc.Inventors: Kazuo Aizawa, Isamu Asano, Junji Tominaga, Alexander Kolobov, Paul Fons, Robert Simpson
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Electronic photosensitive body and manufacturing method for same, as well as image forming apparatus
Patent number: 8330161Abstract: Disclosed is an electrophotographic photoreceptor which comprises a base material and a photoconductive layer. The photoconductive layer is formed on the base material, and comprises a non-single-crystal material mainly composed of silicon. In the photoconductive layer, with regard to a characteristic energy E (eV) which has the relationship with a light absorption coefficient ?(cm?1) represented by the following formula (1), the characteristic energy E1 (eV) for an exposure wavelength in larger than the characteristic energy E2 (eV) for a neutralization wavelength. [Formula (1) a=C exp(h?/E) C: a constant h?: a photon energy h: a rationalized Planck's ?: the number of frequency.Type: GrantFiled: July 31, 2008Date of Patent: December 11, 2012Assignee: Kyocera CorporationInventor: Yoshinobu Ishii -
Patent number: 8330036Abstract: A method of fabricating a multi-junction solar cell on a separable substrate, and structure formed thereby are provided. The method comprises establishing a substrate having a semiconductive composition and forming a sacrificial layer upon the substrate. A solar cell portion is formed upon the sacrificial layer, such that the solar cell portion includes a plurality of multi junction layers. A stabilizing cell layer of semiconductor material is then formed on the solar cell portion, with the stabilizing cell layer having a predetermined thickness greater than a thickness of any individual one of the III-V multi junction layers. Etching is thereafter carried out to remove the sacrificial layer for releasing the solar cell portion from the substrate.Type: GrantFiled: August 31, 2009Date of Patent: December 11, 2012Inventor: Seoijin Park
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Patent number: 8329500Abstract: Provided is a method of manufacturing a photovoltaic device using a Joule heating-induced crystallization method. The method includes: forming a first conductive pattern on a substrate; forming a photoelectric conversion layer on the substrate having the first conductive pattern; and crystallizing at least part of the photoelectric conversion layer by applying an electric field to the photoelectric conversion layer, wherein the photoelectric conversion layer includes a first amorphous semiconductor layer containing first impurities, a second intrinsic, amorphous semiconductor layer, and a third amorphous semiconductor layer containing second impurities.Type: GrantFiled: December 18, 2009Date of Patent: December 11, 2012Assignees: Samsung Display Co., Ltd., Samsung SDI Co., Ltd.Inventors: Byoung-Kyu Lee, Se-Jin Chung, Byoung-June Kim, Czang-Ho Lee, Myung-Hun Shin, Min-Seok Oh, Ku-Hyun Kang, Yuk-Hyun Nam, Seung-Jae Jung, Min Park, Mi-Hwa Lim, Joon-Young Seo
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Patent number: 8324014Abstract: The present invention relates to a process for depositing films on a substrate by chemical vapour deposition (CVD) or physical vapour deposition (PVD), said process employing at least one boron compound. This process is particularly useful for fabricating photovoltaic solar cells. The invention also relates to the use of boron compounds for conferring optical and/or electrical properties on materials in a CVD or PVD deposition process. This process is also particularly useful for fabricating a photovoltaic solar cell.Type: GrantFiled: November 3, 2008Date of Patent: December 4, 2012Assignee: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges ClaudeInventors: Audrey Pinchart, Denis Jahan
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Patent number: 8318531Abstract: thermal management for large scale processing of CIS and/or CIGS based thin film is described. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure. The method also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5. The method further includes introducing a gaseous species including a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, to at least initiate formation of a copper indium diselenide film.Type: GrantFiled: November 9, 2011Date of Patent: November 27, 2012Assignee: Stion CorporationInventor: Robert D. Wieting
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Patent number: 8318589Abstract: Embodiments disclosed herein generally relate to a process of depositing a transparent conductive oxide layer over a substrate. The transparent oxide layer is sometimes deposited onto a substrate for later use in a solar cell device. The transparent conductive oxide layer may be deposited by a “cold” sputtering process. In other words, during the sputtering process, a plasma is ignited in the processing chamber which naturally heats the substrate. No additional heat is provided to the substrate during deposition such as from the susceptor. After the transparent conductive oxide layer is deposited, the substrate may be annealed and etched, in either order, to texture the transparent conductive oxide layer. In order to tailor the shape of the texturing, different wet etch chemistries may be utilized. The different etch chemistries may be used to shape the surface of the transparent conductive oxide and the etch rate.Type: GrantFiled: March 29, 2010Date of Patent: November 27, 2012Assignee: Applied Materials, Inc.Inventors: Valery V. Komin, Hien-Minh Huu Le, David Tanner, James S. Papanu, Philip A. Greene, Suresh M. Shrauti, Roman Gouk, Steven Verhaverbeke
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Publication number: 20120291861Abstract: A heterojunction photovoltaic cell includes at least one crystalline silicon oxide film directly placed onto one of the front or rear faces of a crystalline silicon substrate, between said substrate and a layer of amorphous or microcrystalline silicon. The thin film is intended to enable the passivation of said face of the substrate. The thin film is more particularly obtained by radically oxidizing a surface portion of the substrate, before depositing the layer of amorphous silicon. Moreover, a thin layer of intrinsic or microdoped amorphous silicon can be placed between said think film and the layer of amorphous or microcrystalline silicon.Type: ApplicationFiled: January 26, 2011Publication date: November 22, 2012Applicant: Commissariat A L'Energie Atomique Et Aux Energies AlternativesInventors: Pierre Mur, Hubert Moriceau, Pierre-Jean Ribeyron
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Publication number: 20120291844Abstract: The present invention is to grant a margin in the control of a depth of a groove when removing a transparent insulation layer after the transparent insulation layer is formed on the entire surface of the transparent conductive layer, thereby provide a solar cell which has superior productivity in mass manufacturing. A solar cell includes an n-type amorphous silicon layer formed on a front-surface side of an n-type monocrystalline silicon the substrate; a front-surface side transparent conductive layer formed on the n-type amorphous silicon layer; a p-type amorphous silicon layer formed on a rear-surface-side of the substrate; and a rear-surface-side transparent conductive layer formed on the p-type amorphous silicon layer. A front-surface side collector electrode is formed by plating on the front-surface side transparent conductive layer whereas a rear-surface-side collector electrode is formed on the rear-surface-side transparent conductive layer by printing.Type: ApplicationFiled: July 30, 2012Publication date: November 22, 2012Applicant: C/O SANYO ELECTRIC CO., LTD.Inventor: Sadaji TSUGE
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Patent number: 8314340Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a pad formed on the first interlayer resin insulation layer, a solder resist layer formed on the first interlayer resin insulation layer and the pad, a protective film formed on a portion of the pad exposed by an opening of the solder resist layer, and a coating layer formed between the pad and the solder resist layer. The pad mounts an electronic component. The coating layer has a metal layer and a coating film. The metal layer is formed on the surface of the pad and the coating film is formed on the metal layer.Type: GrantFiled: September 28, 2009Date of Patent: November 20, 2012Assignee: Ibiden Co., Ltd.Inventors: Sho Akai, Tatsuya Imai, Iku Tokihisa
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Publication number: 20120288985Abstract: A method for producing of at least one photovoltaic cell includes successively the anisotropic etching of a surface of a crystalline silicon substrate and the isotropic etching treatment of said surface. The isotropic etching treatment includes at least two successive operations respectively consisting in forming a silicon oxide thin film with a controlled average thickness, ranging between 10 nm and 500 nm and in removing said thin film thus-formed. The operation consisting in forming a silicon oxide thin film on the face of the substrate is carried out by a thermally activated dry oxidation. Such a method makes it possible to improve the surface quality of the surface of the substrate once said surface is etched in an anisotropic way.Type: ApplicationFiled: January 26, 2011Publication date: November 15, 2012Applicant: Commissariat A L'Energie Atomique Et Aux Energies AlternativesInventors: Hubert Moriceau, Pierre Mur, Pierre-Jean Ribeyron
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Patent number: 8304262Abstract: A method for etching features in an etch layer. A conditioning for a patterned pseudo-hardmask of amorphous carbon or polysilicon disposed over the etch layer is provided, where the conditioning comprises providing a fluorine free deposition gas comprising a hydrocarbon gas, forming a plasma from the fluorine free deposition gas, providing a bias less than 500 volts, and forming a deposition on top of the patterned pseudo-hardmask. The etch layer is etched through the patterned pseudo-hardmask.Type: GrantFiled: February 17, 2011Date of Patent: November 6, 2012Assignee: Lam Research CorporationInventors: Ben-Li Sheu, Rajinder Dhindsa, Vinay Pohray, Eric A. Hudson, Andrew D. Bailey, III
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Publication number: 20120273785Abstract: A photosensor element (6a) is provided with a gate electrode (11da) disposed on an insulating substrate (10), a gate insulating film (12) disposed so as to cover the gate electrode (11da), a semiconductor layer (15db) disposed on the gate insulating film (12) so as to overlap the gate electrode (11da), and a source electrode (16da) and a drain electrode (16db) provided on the semiconductor layer (15db) so as to overlap the gate electrode (11da) and so as to face each other. The photosensor element (6a) has the semiconductor layer (15db) provided with an intrinsic semiconductor layer (13db) in which a channel region (C) is defined and an extrinsic semiconductor layer (14db) that is laminated on the intrinsic semiconductor layer (13db) such that the channel region (C) is exposed. The extrinsic semiconductor layer (14db) protrudes from the drain electrode (16db) on the side close to the channel region (C).Type: ApplicationFiled: November 11, 2010Publication date: November 1, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Masao Moriguchi, Yohsuke Kanzaki, Tsuyoshi Inoue
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Publication number: 20120261670Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.Type: ApplicationFiled: April 12, 2012Publication date: October 18, 2012Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.Inventors: Michel Marty, François Roy, Jens Prima