Abstract: A user obtains a set of modules, inserts them into slots of a chassis, and interconnects the modules to form a modular instrument. A signal path extends through the modules. To support calibration of the signal path, a first of the modules (or the chassis or a calibration module) includes a calibration signal generator. A computer directs the first module to apply the calibration signal from the generator to the signal path, and measures the power (or amplitude) of the output of the signal path. The computer reads a factory-measured value A of the calibration signal amplitude from a memory of the first module (or the chassis or the calibration module). The value A and the measured output power of the signal path are used to determine a gain of the signal path. The system compensates for that gain when the signal path is used to measure live operational signals.

Abstract: A method of calibrating an oscillator within a Radio-Frequency Identification (RFID) tag includes storing a plurality of calibration values within a memory structure. Each of the calibration values corresponds to a respective oscillation frequency of the oscillator. A selected calibration value is selected from the plurality of calibration values stored, according to a first selection criterion. The oscillator is then calibrated in accordance with the selected calibration value.

Abstract: Described herein is a sensor assembly that can be calibrated after manufacture and a method for calibrating that assembly. The assembly comprises a sense element, microprocessor and a protection circuit. The assembly can use pins on the existing connector to input calibration data. The present invention also is a method of calibrating sensor outputs using an assembly that contains a protection circuit to prevent the sensor assembly from electrostatic discharge and high and reverse voltage.

Abstract: In the example embodiments, test signals sent from a transmitting system are received at a receiving system. The receiving system generates a determination signal indicating, in one embodiment, whether received signals have a desired relationship with respect to a clock signal at the receiving system. Timing of the clock signal or timing for transmitting signals may be adjusted based on the determination. In another embodiment, the receiving system generates a determination signal indicating whether the pulse width of a lone pulse signal equals a desired time interval. Equalization or pre-emphasis is controlled based on the determination signal.

Abstract: An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information.

Abstract: Embodiments of the present invention provide a method/apparatus to measure the jitter of a timing signal used in an integrated circuit chip. The method/apparatus is used to send data from a launch element using a synchronous data path of the timing signal, receive the data at a capture element using the synchronous data path, wherein the launch element and the capture element are disposed on the same integrated circuit chip upon which the timing signal is generated and/or used, and gather statistics about whether a timing violation has occurred by comparing the sent data with the received data over the course of multiple launch/capture events as the timing is adjusted. Other embodiments may be described and/or claimed.

Abstract: A calibration method for a two-port VNA includes presenting a high reflection calibration standard and measuring reflection data for each of the two ports, calculating a location of the high reflection calibration standard at each of the two ports, presenting a load calibration standard and measuring the reflection characteristic for each of the two ports to provide load data, converting the load data to the time domain to provide time domain impulse response load data, and gating the time domain impulse response load data based on the locations of the high reflection calibration standard at each of two ports. The method further includes reconstructing frequency domain load data from the gated time domain data, connecting the two ports together and determining forward and reverse transmission characteristics, and calculating systematic error coefficients for the VNA based on the reconstructed frequency domain data and the forward and reverse transmission characteristics.

Abstract: A method of calibrating a filter includes applying an input signal into the filter to generate an output signal, measuring a phase difference between the input signal and the output signal; determining a leading/lagging status of the phase difference; calculating a capacitor code (CAP_CODE) using the leading/lagging status; and calibrating the capacitor using the CAP_CODE.

Abstract: An improved calibration detection system for use in calibrating an electronic apparatus includes a processor apparatus, an evaluation apparatus, and a connection apparatus. The connection apparatus includes a plurality of leads and is operated by the processor apparatus to internally switch and connect the various leads with various elements of the evaluation apparatus. By enabling all of the leads to be connected at the outset with the electronic apparatus and by internally switching the connections between the leads and the various elements of the evaluation apparatus, the calibration detection system saves time and avoids error in performing a testing protocol.

Abstract: The invention concerns a method for determining a calibration value indicating the extent of loss of calibration of a group of three or more sensors in a sensor network, the method involving receiving a plurality of data values captured over a period of time by each of the sensors, determining by a processing unit (404) at least one correlation value associated with each sensor, each correlation value corresponding to the correlation between the data values captured by the associated sensor and the data values captured by at least one other sensor; extracting by a high pass filter (410) a noise component of the correlation values and outputting the calibration value determined based on the difference between the noise component and a reference noise value.

Abstract: Provided is a transfer characteristic measurement apparatus that measures a transfer characteristic of a circuit under test between input and output, comprising a test signal input section that generates a test signal by adding together a carrier signal having a prescribed frequency and an additional signal having a frequency that differs from the prescribed frequency, and inputs the test signal to the circuit under test; and a transfer characteristic measuring section that measures the transfer characteristic of the circuit under test at the frequency of the additional signal based on a result from a measurement of an output signal output by the circuit under test. The circuit under test may be formed on a semiconductor chip. The circuit under test may correct a signal input to the semiconductor chip, and outputs the corrected signal. The semiconductor chip may further include a sampling circuit that samples the output signal of the circuit under test at the frequency of the carrier signal.

Abstract: A method is provided for aligning a measurement instrument that includes a tunable filter. The method includes: (i) applying an output signal of an internal noise source of the measurement instrument to the input of the tunable filter, (ii) applying a control signal to the tunable filter to tune the tunable filter to a selected alignment frequency, (iii) measuring a value for a gain alignment parameter of the tunable filter while the output signal of the internal noise source is applied to the input of the tunable filter and the control signal is applied to the tunable filter, (iv) storing the measured gain alignment parameter value in an alignment table in the memory device, and (v) repeating steps (ii) through (iv) for a plurality of selected alignment frequencies in an operating frequency range of the tunable filter.

Abstract: A test and measurement instrument and a method of calibrating the test and measurement instrument including a reference signal generator; multiple input channels; and multiple input circuits. Each input channel is coupled to a corresponding input circuit; and one of the input circuits is coupled to the reference signal generator.

Abstract: A High Definition Multi-Media Interface (HDMI) cable may exhibit frequency dependent signal attenuation, inter symbol interference, and inter-pair skew. A boost device integrated with the cable can compensate for such impairments of the cable. A self calibrating cable with a boost device of the embodiment of the invention is described, in which parameters that control the response of the boost device are set optimally in a self-calibrating process comprising looping the boosted cable on itself through a calibration fixture that contains a calibration control device. The boost device includes pattern generators and a sampling circuit. Each high speed channel of the cable is separately tested and calibrated with the help of one of the other channels serving as a sampling channel. Additional embodiments provide for a selected replica boost device and a distinct pattern generator device in the calibration fixture.

Abstract: An AC/DC voltage measuring instrument is operable in a DC mode, an AC mode, or an automatic mode. In the DC mode, an input terminal is coupled directly to an analog-to-digital converter, which generates a digital output signal indicative of the amplitude of the received signal. In the AC mode, the input terminal is coupled to an RMS circuit through a capacitor. The RMS circuit generates an output signal having an amplitude indicative of the RMS amplitude of the received signal, and this output signal is coupled to the analog-to-digital converter. In the automatic mode, the input terminal is also coupled to the RMS circuit, but it is coupled to the RMS circuit without being coupled through the capacitor. The input terminal is coupled to the RMS circuit through an amplifier, and a calibration procedure is used to compensate for any offset of the amplifier.

Abstract: Embodiments of the present invention are directed to dynamically measuring the speed of a circuit and modifying the operating voltage of the circuit based on the measured speed, in order to minimize the power being used while still ensuring proper operation of the circuit. Consequently, circuits of higher inherent speeds may have their voltages decreased (thus decreasing their actual speeds), while circuits of lower speeds may have their voltages increased, or kept the same. Thus, the resulting speeds of all circuits may be kept within a limited range to ensure proper operation. In addition, the power dissipated of circuits of higher speeds may be decreased.

Abstract: Described embodiments provide a method for calibrating a continuous-time filter having at least one adjustable parameter. A square-wave signal is filtered by a continuous-time filter having a cutoff frequency less than fs. The filtered signal is quantized at the rate fs. An N-point Fourier transform is performed of the quantized signal into N real output values and N imaginary output values. At least one of the real output values are accumulated to form a real output signal and at least one of the imaginary output values are accumulated to form an imaginary output signal. The real and imaginary output signals are summed to form an output signal, which is then squared. The squared output signal is compared to a comparison value. At least one parameter of the continuous-time filter is adjusted based upon the comparison. The steps are repeated until the squared output signal is approximately the comparison value.

Abstract: Method and apparatus for automatically adjusting a parameter used in the display of a Doppler spectral image comprises acquiring a plurality of spectral lines of Doppler data. A subset of Doppler data is determined from the plurality of spectral lines of Doppler data. A noise characteristic of the subset of Doppler data is calculated, and a signal characteristic of the subset of Doppler data is identified. The noise and signal characteristics are compared, and a system parameter is adjusted based on a result of the comparing step.

Abstract: Adaptable self-powered sensor node and methods of operation providing real-time monitoring and management of node operation. The adaptable self-powered sensor node incorporates an adaptable generator and a radio transmitter to operate remotely without the need for power or communication wiring. Data analysis capabilities provide for maximizing information extracted from sensors and analysis and providing control or reporting information utilizing a strategy to minimize energy usage while reducing information entropy.

Abstract: A variable impedance sense (VIS) circuit (400) can detect a drift in the impedance of variable impedance circuits due to changes in operating conditions. Adjustments to binary impedance setting codes are made in response to a detected drift only when such changes do not increase a worst case variation from a target impedance. Adjustments can also be made in response to a detected input offset polarity.

Abstract: An HDMI cable may exhibit frequency dependent signal attenuation, inter symbol interference, and inter-pair skew. A boost device integrated with the cable can compensate for such impairments of the cable. A self calibrating cable with a boost device of the embodiment of the invention is described, in which parameters that control the response of the boost device are set optimally in a self-calibrating process comprising looping the boosted cable on itself through a calibration fixture that contains a calibration control device. The boost device includes pattern generators and a sampling circuit. Each high speed channel of the cable is separately tested and calibrated with the help of one of the other channels serving as a sampling channel.

Abstract: A method is provided for calibrating voltage values and current values detected by a high-frequency measuring device. In a first step, a first parameter is calculated based on impedances calculated when the measuring device is connected to a first set of three reference loads and impedances of the first set of three reference loads. In a second step, plasma processing is carried out with the measuring device connected to a load to be measured, and detected voltage and current values are calibrated using the first parameter, and impedances as viewed from a connection point towards the load side are calculated based on the calibrated voltage and current values. In a third step, three impedances that encompass, when displayed on a Smith chart, a narrower range than a range encompassed by the impedances of the first set of three reference loads are determined, where the narrower range includes the impedances calculated in the second step.

Abstract: A system or circuit for simulating a potentiometer, thermistor, or the like. A pulse stream, having a duty cycle which is varied as a changing pulse width or as a differing number of time slices per time period, may be input to the system. The pulse stream to a transistor or switch-like mechanism may allow a controlled connection of a fixed value resistor to a reference voltage or ground to provide various resultant values of impedance or resistance. A measuring circuit connected to the output of the system may determine a value which is of the fixed value resistor divided by the duty cycle of the pulse train effectively controlling the connection of the resistor to ground. One or more additional circuits may be connected in parallel to achieve greater accuracy.

Abstract: In a parameter correction circuit in an LSI, a reference resistor element with high precision having a resistance value set to a target value is connected to an external terminal of the LSI. A constant current from a mirror circuit connected to a current supply flows through the reference resistor element. A voltage value generated in the reference resistor element is measured by a voltage measuring circuit. The constant current also flows through a variable resistor element. The resistance value of the variable resistor element is adjusted so that a voltage generated in the variable resistor element corresponds to the voltage generated by the reference resistor element.

Abstract: A method for calibrating the loop bandwidth of a phase-locked loop (PLL) is described. At least one resistor in the PLL filter is tuned in accordance with the frequency of an input reference signal. One or more capacitors in the PLL filter are tuned in accordance with the frequency of the input reference signal. Output pulses of one or more voltage controlled oscillators (VCO) are counted. A first charge pump current associated with a target loop bandwidth is counted in accordance with the counted output pulses. A programmable charge pump current is tuned to the calculated first charge pump current.

Abstract: An RF power delivery diagnostic system is provided herein. The system comprises an RF power source (303), an impedance matching network (305), a plasma reactor (307) in electrical contact with the RF power source by way of the impedance matching network, a first RF sensor (309) adapted to measure at least one attribute of the RF power input to the impedance matching network, and a second RF sensor (311) adapted to measure at least one attribute of the RF power output by the impedance matching network.

Abstract: A system and method is disclosed for providing a plurality of hardware performance monitors for adaptive voltage scaling in an integrated circuit system that comprises a plurality of threshold voltage VT logic libraries. Each hardware performance monitor is associated with one of the plurality of threshold voltage VT logic libraries and provides a signal that measures a performance of its respective threshold voltage VT logic library die temperature, process corner and supply voltage. The difference between the measured performance and a nominal expected performance for each hardware performance monitor is determined. The largest of the plurality of difference signals is selected and provided to an advanced power controller for use in providing adaptive voltage scaling for the integrated circuit system.

Abstract: One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.

Abstract: A method of calibrating the frequency of a gm-C filter is provided. The method includes generating, by a frequency calibration circuit, a calibration code capable of tuning a cut-off frequency of the gm-C filter according to a frequency of an oscillation signal that is output from a gm-C oscillator and indicates a process distribution and a reference code, determining, by the frequency calibration circuit, whether the calibration code exists within a range of a reference code, and outputting, by the frequency calibration circuit, the calibration code to the gm-C filter or generating a variable current to simultaneously tune transconductance of the gm-C oscillator and transconductance of the gm-C filter, according to a result of the determination.

Abstract: An HDMI cable may exhibit frequency dependent signal attenuation, inter symbol interference, and inter-pair skew. A boost device integrated with the cable can compensate for such impairments of the cable. A self calibrating cable with a boost device of the embodiment of the invention is described, in which parameters that control the response of the boost device are set optimally in a self-calibrating process comprising looping the boosted cable on itself through a calibration fixture that contains a calibration control device. The boost device includes pattern generators and a sampling circuit. Each high speed channel of the cable is separately tested and calibrated with the help of one of the other channels serving as a sampling channel.

Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: A circuit testing apparatus for testing a device under test is disclosed. The device under test comprises a first output end and second output end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines a test result for the device under test according to the first output signal and the second output signal.

Abstract: A method of compensating a calibration for a vector network analyzer includes performing calibrations on at least a pair of ports to determine error terms associated with each port wherein at least one of the error terms is based upon selecting the reactance of the load standard from a set of potential values in a manner such that the reference reactance errors are reduced.

Abstract: An integrated circuit and method for monitoring and controlling power and for identifying an open circuit state at an output port is disclosed. A circuit is implemented to determine whether an open circuit state exists based on a comparison of data received from the output port and attached loads. The data received from the output port and attached loads is compared to a minimum open circuit current value of the output port, wherein the minimum open circuit current value is based on the hardware characteristics of the output port and attached loads. A possible open circuit state at the output port is reported based on the comparison.

Abstract: An optical fiber current transformer includes a broadband light source, a depolarizer, a beam splitter, a temperature acquisition unit, a current acquisition unit, a modulation waveform generating unit, a data processing unit and a calculating compensation unit. The broadband light source is connected with the beam splitter by the depolarizer. A first output of the beam splitter is connected with the calculating compensation unit by the temperature acquisition unit. A second output of the beam splitter is connected with the data processing unit by the current acquisition unit. The data processing unit is connected with the calculating compensation unit. The calculating compensation unit is connected with the current acquisition unit by the modulation waveform generating unit.

Abstract: A mechanism uses in-situ bidirectional cable wrapping for determining different cable lengths. A calibration mechanism calibrates the high speed transmitter/receiver pair characteristics, and, thus, optimizes the transmission performance between subsystems. The calibration mechanism mitigates the need for frequent error correction and does not incur the performance degradation associated with error correction techniques.

Abstract: A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Abstract: A measurement error correcting method and electronic component characteristic measuring device capable of accurately coping with an electronic component which includes nonsignal line ports and whose electrical characteristics are changed by a jig. The method includes the steps of measuring an electrical characteristic, with correcting-data-acquisition samples mounted on a test jig enabling measuring nonsignal line ports, and the samples mounted on a reference jig; measuring a through device in which a signal line port and a nonsignal line port are electrically connected to each other; determining a numerical expression for calculating, from results of measurement on the test jig, an estimated electrical characteristic value obtained on the reference jig; measuring an arbitrary electronic component, on the test jig; and calculating the estimated electrical characteristic value obtained on the reference jig.

Abstract: A method of extracting an optimized digital variable resistor (“DVR”) value of a display panel, the method including varying a DVR value, corresponding to a common voltage, and applying the varied DVR values to the display panel, measuring brightness values of the display panel for at least two frames, extracting flicker values corresponding to the varied DVR values using the brightness values, and extracting an optimized DVR value by generating first to third coordinate values in which coordinate values have x-coordinate values and y-coordinate values representing DVR values and flicker values, respectively, calculating a first linear function of a first straight line connecting two of the coordinate values, and a second linear function of a second straight line using the first linear function and the other of the coordinate values, and extracting an x-coordinate value at an intersection point of the first and second lines, as the optimized DVR value.

Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.

Abstract: An integrated circuit includes a first storage location, a first generator, a converter, and a second generator. The first storage location is operable to store a first adjustment value. The first generator is coupled to the first storage location, is operable to generate a first signal having a first characteristic, and includes a first adjuster operable to change the first characteristic in response to the first adjustment value. The converter is coupled to the first storage location and is operable to generate from the first adjustment value a modified adjustment value. The second generator is coupled to the converter, is operable to generate a second signal having a second characteristic, and includes a second adjuster operable to change the second characteristic in response to the modified adjustment value.

Abstract: To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer.

Abstract: A method for automated calibration of an avalanche photodiode receiver includes measuring two values of avalanche photodiode biases at two successive times, measuring and comparing a bit error rate corresponding to each value. When the bit error rate of the second value is equal to or greater than the bit error rate of the first value, then a third value and a fourth value of avalanche photodiode bias closer together are measured. When the bit error rate of the fourth value is smaller than the bit error rate of the third value, two subsequent values as third value and fourth value are measured, and an optimum avalanche photodiode bias when the bit error rate of the fourth value is equal to the bit error rate of the third value is measured.

Abstract: The present disclosure relates to off-chip supply of calibration data.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Abstract: A method for calibrating a hands-free system is provided. The hands-free system comprising a hands-free unit and a mobile phone, the method comprising the following steps of setting up a connection between the hands-free system and a distant terminal via a mobile telephony network of the mobile phone, transmitting a predetermined test signal from one of the hands-free system and the distant terminal to the other of the hands-free system and the distant terminal, the predetermined test signal being provided in both the hands-free system and the distant terminal as reference test signal, comparing the received test signal to the reference test signal stored in the other of the hands-free system and the distant terminal, and determining the calibration parameters of the hands-free system in accordance with the comparison.

Abstract: A microprocessor control circuit continuously monitors core logic operating temperature and detects it has risen above a first temperature and responsively iteratively controls a system voltage source to output a next lower one of its N output voltage levels and controls clock generation circuitry of the microprocessor to output a lower one of its M core clock signal frequencies as necessitated by a transition to the next lower output voltage level until the temperature drops below the first temperature. The control circuit detects that the temperature has dropped below a second temperature and responsively iteratively controls the voltage source to output a next higher output voltage level and controls the clock generation circuitry to output a higher core clock signal frequency as permitted by the next higher output voltage level until the operating temperature rises above the second temperature. The M frequencies comprise a highest, lowest, and plurality of intermediate frequencies.

Abstract: An exemplary liquid crystal display (LCD) panel includes scan lines, data lines, a scan driver connected to the scan lines, a data driver connected to the data lines, a controller connected to the scan driver and the data driver, and pixels formed by the scan lines and the data lines. The LCD panel is divided into five detecting regions, and the first detecting region is in a center of the LCD panel, and others surround the center portion of the LCD panel. Each detecting region includes a photo sensor. The controller is used to control the five detecting regions to have substantially the same flicker level.

Abstract: A semiconductor memory device for performing an OCD calibration control operation to adjust a data output impedance includes a decoder for decoding an address signal to generate an OCD default control signal, an OCD operation signal and plural data, a code generator for receiving plural-bit data to generate an OCD control code; a first circuit for receiving the OCD control code and the OCD operation signal to generate a plurality of impedance adjustment control signals; and a second circuit for receiving the plural data and adjusting the data output impedance in response to the plurality of impedance adjustment control signals.