Abstract: A meter device for measuring electrical energy is provided. The meter device includes circuitry for measuring at least one parameter of electrical energy provided to the meter device. A storage device is provided for storing at least one calibration factor for compensating for errors associated with at least one of at least one current transformer (CT) and at least one potential transformer (PT) that operates on the electrical energy provided to the meter device. At least one processor is provided for processing the at least one calibration factor for adjusting the measuring for compensating for the errors when measuring the electrical energy.

Abstract: A method of calibrating a circular portion of an object, such as to determine the center point of the object, is provided. The method includes determining spatial coordinates of at least two points on a circumferential edge of the circular portion of the object, and calculating the center point of the circular portion using the spatial coordinates of the two points and a geometric parameter representative of the diameter of the circular portion. A calibration device and system are also provided for use with a computer tracking system in order to calibrate such an object having a circular portion.

Abstract: A compensation signal, which derives the mechanical stress, which acts on an integrated semiconductor circuit, from two partial compensation signals, which are generated by semiconductor elements with different stress characteristics, can be determined in more detail when the temperature dependence of a ratio of the partial compensation signals is also considered, wherein particularly a deviation of the ratio of the partial compensation signal to an ideal ratio is considered. Thereby, the rise in accuracy of the stress determination results from determining a deviation of the partial compensation signals, on which the stress determination is based, from a nominal behavior in a stress-free state, so that the deviation of the nominal behavior, which can be based, for example, on a variation of the process parameters in a production process of a semiconductor circuit, can also be considered, in addition to the known temperature behavior.

Abstract: In some embodiments, an apparatus comprises a thermal sensor to detect a first temperature reading at a location proximate a buffer circuit at a first point in time and to detect a second temperature reading at a location proximate a buffer circuit at a second point in time, logic to generate a buffer compensation activation signal when the second temperature reading differs from the first temperature reading by an amount exceeding a threshold, and logic to transmit the buffer compensation activation signal to a buffer compensation module. Other embodiments are described.

Abstract: A semiconductor memory device for performing an OCD calibration control operation to adjust a data output impedance includes a decoder for decoding an address signal to generate an OCD default control signal, an OCD operation signal and plural data, a code generator for receiving plural-bit data to generate an OCD control code; a first circuit for receiving the OCD control code and the OCD operation signal to generate a plurality of impedance adjustment control signals; and a second circuit for receiving the plural data and adjusting the data output impedance in response to the plurality of impedance adjustment control signals.

Abstract: A system and method is disclosed for providing an improved voltage monitor that is capable of determining that a value of an adjustable supply voltage is suitable for a requested performance level in an adaptive voltage scaling system. An integrator circuit of the voltage monitor integrates a slack time error signal from a hardware performance monitor. Control circuitry evaluates a suitability of the integrated slack time error signal for the requested performance level for a number of voltage evaluation time periods. The adjustable supply voltage is deemed to be stable when the integrated slack time error signal is within a predetermined range of limits for at least two voltage evaluation time periods.

Abstract: A method for self-calibrating a sensor can be implemented in a system having a calibration circuit. The calibration circuit has differential circuitry which compares an output signal of the sensor with a predetermined reference signal associated with a reference property. A bias controller increments or decrements the sensor operating bias according to the deviation between the predetermined reference signals and sensor output signal such that the sensor output corresponds to the predetermined reference voltage. The calibration circuit can be embedded in the sensor to provide a self-calibrating sensor. Logic circuitry can be used to form the calibration circuit.

Abstract: A method for calibrating a parameter of an IC, using an external device so as to calibrate an analog control parameter of an internal analog circuit in the IC. The external device is used in a detecting mode so as to detect whether the analog control parameter is beyond a pre-determined range. If the analog control parameter is beyond the pre-determined range, the external device is used in a calibrating mode so as to obtain a calibrated value and the calibrated value is then written into the internal analog circuit in the IC. The external device is used for detection and calibration repeatedly until the analog control parameter is within the pre-determined range. When the analog control parameter is within the pre-determined range, the calibrated value is written into a non-volatile memory in the IC.

Abstract: A method for trimming reference voltage circuitry includes defining a desired target reference voltage for a set of at least one die. At least two reference voltages are measured for at least two different trim settings associated with a given die of the at least one die. A modified target reference voltage is determined for the given die based on the at least two measured reference voltages. A trim setting associated with the reference voltage circuitry of the given die is set according to the modified target reference voltage so as to compensate for an offset voltage and substantially achieve the desired target reference voltage.

Abstract: Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.

Abstract: Method and apparatus are described for compensating for a linear time scale change in a received signal, so as to correctly rescale the frame sequence of the received signal. Firstly, an initial estimate of the sequence of symbols is extracted from the received signal. Successive estimates of correctly time scaled sequences of the symbols are then generated by interpolating the values of the initial estimates.

Abstract: Disclosed is a multi-phase power regulator that accurately senses current at a load in a lossless manner and adjusts the power supplied to the load based on the sensed current. Also disclosed is a method of calibrating a multiphase voltage regulator by applying a known calibration current at the load and determining actual current values by the difference in measured values between when the known calibration current is applied and when it is not applied. The accurate current is determined at a known temperature and accurate temperature compensation is provided by a non-linear digital technique. Each phase of the multi-phase power regulator is individually calibrated so that balanced channels provide accurate power to the load. Also disclosed is a calibration method with minimal noise generation.

Abstract: A main signal path filter is calibrated by calibrating a replica filter that tracks parametric changes in the main signal path filter. Programmed values of the replica filter determined during calibration are used to set programmed values in the main signal path filter. The main signal path filter signal does not need to be interrupted while calibration occurs. Power on testing of the main signal path filter and the replica filter can be performed to determine the parametric tracking relationship between the two filters.

Abstract: An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.

Abstract: A delay line (DL) circuit used to generate test pattern waveforms has a pulse generating circuit that is used during calibration to generate a pulse signal upon receiving a signal edge. A delay line of the DL circuit receives the pulse signal and delays the pulse signal by a selected time delay. A feedback loop of the DL circuit feeds the delayed pulse signal output from the delay line back to the input of the pulse generating circuit. Receipt of an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate another pulse signal. The delayed pulse signal output from the delay line can be input to a counter that generates a counter value that is based on the period of oscillation of the delayed pulse signal.

Abstract: A circuit, system and method adjusts a reference voltage, such as an internal or external reference voltage VREF, in response to a first voltage at a first contact, such as a pin on a memory controller used for reading or writing data, and a second voltage at a second contact in embodiments. Logic is coupled to the first and second contacts to provide a control signal in response to the first and second voltages. A comparator provides an input signal to the logic in response to a target reference voltage and the reference voltage during a calibration or initialization mode of operation. In an alternate embodiment, a plurality of data values at a first contact are compared to a predetermined plurality of test data. An up/down signal is then provided to a counter and a register stores a counter value used to provide a reference voltage.

Abstract: A system and method for adaptively providing a power supply voltage. The system includes an input/output subsystem configured to receive a first voltage, an analog subsystem configured to receive a second voltage and coupled to the input/output subsystem, a first digital subsystem configured to receive a third voltage and coupled to the input/output subsystem, and a second digital subsystem configured to receive a fourth voltage and coupled to the input/output subsystem, the first digital subsystem, and the analog subsystem. Additionally, the system includes a first adaptive power supply configured to receive an input voltage and generate the third voltage, and a second adaptive power supply configured to receive the input voltage and generate the fourth voltage.

Abstract: Methods and apparatus are provided which generate an error signal if a sensor is either anticipated to fail or fails. At least two sensors provide input signals having magnitudes that approximately correspond to a sensed event. A processor calculates an actual correlation error for the two signals. A processor then further calculates an estimated new correlation value based on the difference of a stored initial correlation value and the actual correlation error. After a predetermined number of estimated correlation values are calculated, the error signal is generated if the difference between an estimated correlation value and the actual correlation error exceeds a predetermined threshold.

Abstract: In a first aspect, a first method is provided for adjusting memory system calibration. The first method includes the steps of (1) while in a first operating state, calibrating the memory system using a first amount of calibration data so that functional data may be read from and written to memory of the memory system; and (2) while in a second operating state, calibrating the memory system using a second amount of calibration data so that functional data may be read from and written to the memory, wherein the second amount of calibration data is smaller than the first amount of calibration data. Numerous other aspects are provided.

Abstract: A method of automatic gain control in both analog and digital domain is performed by receiving an incoming analog signal, determining an overall gain factor, determining a coarse analog gain control value and a fine digital gain control value, each of which, when taken together substantially equals the already determined overall gain factor, modifying the incoming analog signal using the coarse analog gain control value to form a coarsely adjusted digital signal, digitizing the coarsely adjusted digital signal, and using the fine digital gain control value to process the coarsely adjusted digital signal to form an outgoing digital signal, wherein the outgoing digital signal has been modified in both the analog domain and subsequently in the digital domain to achieve an appropriate signal to noise ratio.

Abstract: One embodiment is a method of calibrating current offsets from a direct current bus current circuit adapted to control a motor including the steps of initializing the direct current bus current circuit, disengaging pulse width modulated signals to the motor, sampling current values at a predetermined sampling rate, averaging the current values over a predetermined number of samples to establish an offset value, and calculating a calibration value that will nullify the offset value in any subsequent processing of current samples. Another embodiment, a method of filtering inaccurate data from a sequential calculation of power values based on repeatedly sampled voltage and current including the steps of establishing a moving window of a predetermined number of power values, calculating an average power over a sequence comprising the predetermined number of power values, calculating an error value for each time, and comparing each error value to a preset value.

Abstract: Systems and methods for pulse stretching architectures for phase alignment of multi-frequency clocks for high speed data acquisitions are disclosed. A high speed data acquisition system includes a transmitter and a receiver. The receiver includes a multi-frequency clock generator that generates a plurality of clock signals, a pattern check module that detects a test pattern received from the transmitter and outputs a stretch command signal, and a stretch pulse generator that receives the stretch command signal and provides a stretch pulse signal that aligns the phases of the plurality of clock signals generated by the multi-frequency clock generator. Methods for initializing and shifting multi-phase clock signals to optimize error performance of a high speed data acquisition system are also provided.

Abstract: In one embodiment, a request to perform a calibration process for automated test equipment (ATE) is received. The request is associated with a calibration parameter set. After receiving the request, one or more signatures for calibration data corresponding to the calibration parameter set are derived, and a determination is made as to whether calibration data corresponding to the signature(s) has already been generated. Thereafter, an incremental set of calibration data is generated, with the generated calibration data i) corresponding to the signature(s), but ii) not having already been generated. In another embodiment, a request to perform a calibration process for ATE is received, and the request is associated with specified test setups. An incremental set of calibration data corresponding to the specified test setups is then generated.

Abstract: Methods and devices for calibrating a driver on a slave device, using a master device driver as a load, are disclosed. A master reference driver is integrated on the same circuit as the master device driver, with both drivers having the same layout and geometry. The master reference driver is calibrated using a selected load impedance that includes the nominal slave device driver impedance and any other impedance elements. The same calibrated driver setting is concurrently applied to both the master driver and the master reference driver, while the slave device drives the master driver. The voltage at the master driver is compared to the voltage at the master reference driver, and the slave device driver impedance is adjusted until those voltages match. The resulting calibration of the slave device driver impedance is largely independent of the actual impedance of the master device driver.

Abstract: Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. An offline algorithm for calculating the parameters of data-dependent noise predictive filters 304A-D is presented which has two phases: a noise statistics estimation or training phase, and a filter calculation phase. During the training phase, products of pairs of noise samples are accumulated in order to estimate the noise correlations. Further, the results of the training phase are used to estimate how wide (in bits) the noise correlation accumulation registers need to be. The taps [t2[k], t1[k], t0[k]] of each FIR filter are calculated based on estimates of the entries of a 3-by-3 conditional noise correlation matrix C[k] defined by Cij[k]=E(ni-3nj-3|NRZ condition k).

Abstract: The disclosed embodiments may relate to vehicle (10) having a control system (12) located within the vehicle (10). The control system (12) may include a processor (26) and a wake-up circuit (46) coupled to the processor (26). The processor (26) may utilize a program (34) during a standby mode of operation. The program (34) is configured to provide a voltage to the wake-up circuit (46) for a first time period (T1) once an interrupt is received by the processor (26). Then, the program (34) may monitor the wake-up circuit (46) for a second time period (T2). If a response of the wake-up circuit (46) exceeds at least one of a plurality of predetermined limits, then the program (34) may recalibrate the wake-up circuit (46).

Abstract: A memory device with an apparatus for recalibrating an output signal of an internal circuit is disclosed. The memory device includes a plurality of signal modulators for simultaneously receiving the output signal of the internal circuit, and a control unit for outputting a control signal for selecting one of the plurality of signal modulators. The control signal output from the control unit includes OCD (Off Chip Driver) calibration information.

Abstract: There is provided a determination apparatus. The determination apparatus includes (a) a determination device having a plurality of determination terminals, (b) a controller for selecting at least one of the plurality of determination terminals, determining a calibration reference standard, and setting of a property value of the determined calibration reference standard, and (c) a memory for storing a parameter of the determined calibration reference standard and a determined value for the parameter as determined by the determination device. The determination device determines an error of the determined value of the parameter, the error being stored in the memory, the determination device outputting the determined value after removing an effect of the error therefrom, and obtaining and storing a re-determined value for the parameter while maintaining the determined value of the parameter of the calibration reference standard in the memory.

Abstract: A test system and method which utilizes a component data base that stores performance data for individual component of the system. The system and method can further provide for using data and information from one calibration procedure in connection with performing further calibration procedures. The system and method can further provide for utilizing data of from linear components of the system to determine performance characteristics of non-linear components.

Abstract: Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. An offline algorithm for calculating the parameters of data-dependent noise predictive filters 304A–D is presented which has two phases: a noise statistics estimation or training phase, and a filter calculation phase. During the training phase, products of pairs of noise samples are accumulated in order to estimate the noise correlations. Further, the results of the training phase are used to estimate how wide (in bits) the noise correlation accumulation registers need to be. The taps [t2[k],t1[k],t0[k]] of each FIR filter are calculated based on estimates of the entries of a 3-by-3 conditional noise correlation matrix C[k] defined by Cij[k]=E(ni?3nj?3|NRZ condition k).

Abstract: A system comprises a master device and a plurality of memory devices coupled to the master device by an interconnect in an embodiment. The master device obtains a plurality of values representing reference voltage values and selects a first value in the plurality of values representing reference voltage values to generate an internal reference voltage value when reading data from a selected memory device in the plurality of memory devices. A method comprises obtaining a plurality of values representing reference voltages for a plurality of memory devices in an embodiment. A first value is selected in the plurality of values representing reference voltages. A reference voltage value is adjusted in response to the first value to an adjusted reference voltage value. Data is transferred to a selected memory device in the plurality of memory devices using the adjusted reference voltage value.

Abstract: In a parameter correction circuit in an LSI, a reference resistor element with high precision having a resistance value set to a target value is connected to an external terminal of the LSI. A constant current from a mirror circuit connected to a current supply flows through the reference resistor element. A voltage value generated in the reference resistor element is measured by a voltage measuring circuit. The constant current also flows through a variable resistor element. The resistance value of the variable resistor element is adjusted so that a voltage generated in the variable resistor element corresponds to the voltage generated by the reference resistor element.

Abstract: A self-calibrating sigma-delta converter (SCADC) functions in a calibration mode and in an operational mode. In the calibration mode, a test circuit of the SCADC generates test signals that are periodic rectangular voltage waveforms. Each test signal has a dc component with a precise voltage amplitude, as well as harmonic components. A low-pass filter of a sigma-delta converter (SDC) within the SCADC filters out the harmonic components. A digital calibration processing circuit within the SCADC uses the precise voltage amplitudes to generate digital correction factors that compensate for dc offset error, gain error and INL error of the SDC. In the operational mode, the SDC receives an analog operational signal and outputs an operational digital data stream. The digital calibration processing circuit uses the correction factors to compensate for dc offset error, gain error and INL error in the operational digital data stream and outputs a corrected digital data stream.

Abstract: A calibration unit and technique for calibrating A/D systems (e.g., data acquisition devices) using a pulse-width modulation (PWM) circuit to reduce nonlinearity. The calibration unit may be coupled to an analog-to-digital module (ADM) of the A/D system. The PWM circuit may generate a calibration signal with intentional ripple, which may exercise a region of a transfer curve of the ADM to reduce local nonlinearities in measurements associated with the calibration of the system. Pulse trains of varying frequency and duty cycle may be generated to sweep the PWM circuit through an ADM range and to calculate an ADM linearity correction function, which may be used to perform gain and offset correction with respect to a best-fit line through an ADM transfer curve to reduce large signal nonlinearities. The PWM circuit may include a resistor divider circuit including a plurality of taps to calibrate small input ranges.

Abstract: A sensor system with variable sensor-signal processing comprises an integrated circuit sensor unit. The integrated circuit sensor unit includes a sensor element that provides a sensed signal in response to a measurement variable, and a memory device that stores adjustable coefficient values. The integrated circuit sensor units also includes a sensor signal processing unit that processes the sensed signal using adjustable coefficient values to provide a sensor output signal on a output line. The sensor system receives updated adjustable coefficient values via the output line and stores the updated adjustable coefficient values in the memory device.

Abstract: The invention relates to a method for calibrating a vectorial network analyzer having n measurement ports and at least 2n measurement locations (n>1) by successive measurement of the reflection and transmission parameters at different two-port calibration standards, which are connected between the measurement ports in any desired order and must all have a transmission path, and three different n-port calibration standards, which are connected between the measurement ports in any desired order and which are not permitted to show transmission and by calculation of error coefficient and scattering matrix [Sx] with the 10-term or 7-term multiport method. An object of the invention is to propagate a method for calibrating these vectorial network analyzer used for multiport measurement which permits a calibration with increased precision and considerable reproducibility of measurement.

Abstract: In one embodiment, a method comprises storing parameters that are related to switch error correction terms of a vector network analyzer (VNA), and applying a calibration process of a TRL group of calibration processes to the VNA to generate calibration measurements, wherein the calibration process generates calibration measurements, calculates a switch error correction matrix using the stored parameters and a subset of the calibration measurements, and applies the switch error correction matrix to calibration measurements before solving for eight-systematic error terms associated with the calibration process.

Abstract: According to one aspect of the present invention, there is provided a method of calibrating an oscillator within a radio-frequency identification (RFID) circuit for use in an RFID tag. A plurality of calibration values is stored within a memory structure associated with the RFID circuit. Each of the calibration values corresponds to a respective oscillation frequency of the oscillator. A selected calibration value is selected from the plurality of calibration values stored within the memory structure, according to a first selection criterion. The oscillator is then calibrated in accordance with the selected calibration value.

Abstract: A multiport vector network analyzer calibration employs measurements of an asymmetric reciprocal device to determine a value of a defining parameter of a calibration standard in a set of calibration standards. A method of determining a parameter value determines and reports the parameter value. A method of compensating a calibration determines the parameter value and employs the determined parameter value to optimize a set of error coefficients of an error model of the multiport vector network analyzer. A multiport vector network analyzer that includes a controller, a test set, and computer program executed by the controller, compensates a calibration using the determined parameter value and a set of optimized error coefficients. A calibration compensation system that includes a multiport vector network analyzer, a computer, and a computer program executed by the computer, determines and reports the parameter value.

Abstract: Disclosed is a phase calibration method for inserting a calibration signal (SC) into main signals (SM1 to SMn) of a plurality of branches in turn, estimating the phase characteristic of an analog circuit to which a respective one of the main signals is input and calibrating the phase of each main signal. The method includes steps of outputting a first combined signal obtained by combining output signals from the analog circuits (62a to 62n) in all branches, outputting a second combined signal obtained by combining the main signals in all branches, extracting the calibration signal by removing the second combined signal from the first combined signal in a calibration signal extracting unit (64), estimating the phase characteristics of the analog circuits, to which the main signals having the inserted calibration signal are input, based upon a change in phase of the calibration signal, and subjecting the main signals to phase adjustment having characteristics that are opposite the phase characteristics.

Abstract: An integrated circuit has a circuit for adjusting the time period of an output signal. The adjustment can compensate for semiconductor processing variations varying from wafer to wafer. The circuit adjusts the delay generated by an adjustable delay line, and adjusts the occurrence in time of the trailing edge of the output signal. A value which corresponds with a suitable delay to be generated by the adjustable delay line is stored in nonvolatile storage on the integrated circuit.

Abstract: In a method for determination and representation of adjustment steps for operation of an apparatus requiring adjustment, such as a diagnostic imaging apparatus, the implementation of manual adjustments by a user is supported. The method determines which adjustment steps are necessary for adjustment of the apparatus for a particular operation thereof and displays then in a list on a display medium. The adjustment steps are ordered corresponding to a sequence that is necessary for adjustment of the apparatus.

Abstract: An improved pipelined analog to digital converter that facilitates calibration for non-linearity errors and a method for obtaining calibration values. The analog to digital converter has a calibration mode in which the output bits for stages in the pipeline can be coupled to output pins of the device. Device pins that are used in normal operating mode to output the most significant bits of the ADC output are used in calibration mode to make available output bits of a pipeline stage being calibrated. A calibration method takes advantage of the outputs of the stages being directly observable to compute calibration values. The output bits of a pipeline stage are monitored as the analog input to the ADC is increased. A change in these bits identifies a subrange boundary. Errors are measured for values immediately above and immediately below each subrange boundary and used to compute correction factors.

Abstract: An analog-to-digital converter (ADC) exhibiting an uncorrected non-linear transfer function receives measured analog voltage amplitudes and outputs uncorrected digital values. A calibration circuit receives each uncorrected digital value and outputs a corrected digital value. The measured analog voltage amplitudes received by the ADC and the corresponding corrected digital values output by the calibration circuit define points approximating an ideal linear transfer function of the ADC. The calibration circuit performs piecewise-linear approximation of the uncorrected transfer function and associates each uncorrected digital value with the applicable linear segment that passes through a segment endpoint on the uncorrected transfer function. The calibration circuit calculates each corrected digital value using calibration coefficients associated with the applicable linear segment, such as the slope of the linear segment.

Abstract: A method and apparatus for calibrating a current source to a reference current through the use of 1-bit current comparisons. A temporary current source is first calibrated to the reference current, which allows an input offset current generated by the current comparator to be memorized. The current to be calibrated is then fine-tuned to the temporary current within specified limits, which effectively cancels comparison error that is generated by the input offset current.

Abstract: According to at least one embodiment, a method comprises measuring drive current of a reference memory cell of a circuit, and determining, based on the measured drive current of the reference memory cell, a drive current to be supplied to a calibration memory cell of the circuit to mimic a defective memory cell. The method further comprises supplying the determined drive current to the calibration memory cell, and using the calibration memory cell to determine strength of a weak write to be utilized by a weak write test for detecting defective memory cells.

Abstract: An Impedance standard substrate for adjusting a vector network analyzer mainly comprises a fixer and a flexible tape, wherein the vector network analyzer has a plurality of pairs of probes disposed at an underneath of the impedance standard substrate and an upside of the impedance standard substrate. There are thru-circuits formed at the flexible tape, wherein the flexible tape has electrically connecting contacts and the contacts are electrically connected to each other. The flexible tape is bent and fixed to a fixer such that the contacts are faced to the corresponding probes respectively. Furthermore, the impedance standard substrate also includes a plurality of pairs of open-circuits, short-circuits and load-circuits formed at the flexible tape.

Abstract: Memory circuits are calibrated by adjusting memory circuit output parameters based on data eye measurements. Data eye patterns of memory circuit outputs are measured by the memory controller for different settings of the memory circuit output parameters. Memory circuit output parameters can be adjusted to settings that correspond to widest average data eye widths, highest average data eye heights, or other suitable criteria.

Abstract: A method and apparatus are used to calibration a Vector Network Analyzer (VNA). The method includes providing a calibration module with a single port, providing within the calibration module a set of reflecting components with known scattering parameters, providing control signals to the calibration module through the single port, providing the known scattering parameters to the VNA through the single port, coupling one of reflecting components to the VNA, measuring scattering parameters, and comparing the measured scattering parameters with the known scattering parameters. The apparatus includes a calibration module and a controller module. In one embodiment, the calibration module includes a set of reflecting components, a memory that stores the characterization data, and a current source which sends characterization data in the form of current pulses to the controller module. The controller module includes a voltage source that generates the control signals used by the calibration module.

Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.