Abstract: A high-frequency measurement unit includes a signal detector for detecting a high-frequency signal, and a calibration coefficient storage for storing calibration coefficients Cmin and Cmax used to calibrate a value Amin detected at the lowest limit frequency fmin and a value Amax detected at the uppermost limit frequency fmax to a proper measurement value Asmin and to a proper measurement value Asmax, respectively. The high-frequency measurement unit further includes a frequency detection unit for detecting a frequency fm of the high-frequency signal, a calibration coefficient calculation unit for calculating a calibration coefficient Cm for the frequency fm, and a calibration unit for calibrating the value Am detected by the signal detector to a proper measurement value Asm by using the calibration coefficient Cm calculated by the calibration coefficient calculation unit.

Abstract: A method of adjusting a response of an energy measuring filter, such as an FIR filter, of a pulse processor based on a slope of a preamplifier signal having a plurality of step edges each corresponding to a respective photon is provided that includes receiving a digital version of the preamplifier signal comprising a plurality of successive digital samples each having a digital value, the preamplifier signal having a portion defined by a first one of the step edges and a second one of the step edges immediately following the first one of the step edges, using the digital values of each of the digital samples associated with the portion to determine an average slope of the portion normalized by a length of the portion, and using the average slope of the portion normalized by a length of the portion to correct the response of the energy measuring filter.

Abstract: A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.

Abstract: Calibrating automatic test equipment (ATE) includes adding jitter to a test signal to produce a jittered signal, sampling the jittered signal to produce digital values, generating a reconstructed jittered signal from the digital values, determining an amount of jitter in the reconstructed jittered signal, and calibrating the ATE based on the amount of jitter in the reconstructed jittered signal.

Abstract: A sensing system, including: a sensing assembly, the sensing assembly having: a trim resistor; and a controller removably secured to the sensing assembly, the controller being configured to determine a resistance value of the trim resistor; a database in operable communication with the controller, the database having a plurality of resistance values, each identifying a pair of compensation values; a microprocessor receiving the resistance value of the trim resistor, a first signal and a second signal, the resistance value of the trim resistor being used to define a selected pair of compensation values from the database, one of the selected pair of compensation values is used to adjust the first signal and the other one of the selected pair of compensation values is used to adjust the second signal.

Abstract: Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.

Abstract: A method and apparatus is provided for setting time positions of measurement gates on a signal under test. Signal transition data is calculated by a processor for multiple signal transitions. Measurement gate start and end positions are set relative to the multiple signal transitions based on the received signal transition data.

Abstract: A method for adjusting an electronic system is provided in which it is possible to predefine the n parameters of the system which correspond to an n-dimensional adjustment space, wherein at the start of the adjustment each parameter has predefined for it two limit values that delimit an appropriate initial range in the n-dimensional adjustment space, and wherein the following steps are repeated until a termination condition is achieved: evaluating a target function that quantifies the achievement of an adjustment target for the limit values that delimit the initial range, wherein the evaluation includes the measurement and/or evaluation of at least one physical quantity of the system that is a function of the specific parameter or its limit value, and wherein appropriate target function values associated with the limit values are obtained, defining a modified, in particular reduced, initial range for a subsequent iteration as a function of the target function values obtained.

Abstract: A method for calculating correction factors for reducing positional errors in resistance measurements using a probe having four probe arms includes: positioning the probe anus to contact a test sample; selecting a first set of first and second probe arms and a second set of third and fourth probe arms; applying a first current from the first to the second probe arms of the first set, through the sample; detecting a first voltage between the third and fourth probe arms of the second set; calculating a first resistance as a ratio of the first voltage and the first current; selecting a third set of first and second probe arms including no more than one of the probe arms of the first set, and a fourth set of third and fourth probe arms including no more than one of the probe arms of the second set; applying a second current from the first to the second probe arms of the third set, through the sample; detecting a second voltage at the third and fourth probe arms of the fourth set; calculating a second resistance a

Abstract: A method for calibrating a data processing apparatus to set a target firmware trim value is disclosed. The data processing apparatus is for converting a non-test pattern to a non-test output according to the target firmware trim value under a normal mode. The method includes: driving the data processing apparatus to convert a test pattern into a test output according to a test firmware trim value received under a calibration mode; and analyzing the test output to tune the test firmware trim value outputted to the data processing apparatus, and controlling the data processing apparatus to store a specific test firmware trim value as the target firmware trim value when an analysis result of the test output generated in reference to the specific test firmware trim value indicates that a predetermined criterion is met.

Abstract: The inventive circuitry on a semiconductor chip includes a first functional element having a first electronic functional-element parameter that exhibits a dependence relating to the mechanical stress present in the semiconductor circuit chip in accordance with a first functional-element stress influence function. The first functional element provides a first output signal based on the first electronic functional-element parameter and mechanical stress. A second functional element has a second electronic functional-element parameter that exhibits a dependence in relation to the mechanical stress present in the semiconductor circuit chip in accordance with a second functional-element stress influence function. The second functional element is configured to provide a second output signal based on the second electronic functional-element parameter and the mechanical stress.

Abstract: A semiconductor chip includes a first functional element having a first electronic functional-element parameter exhibiting a dependence relating to the mechanical stress present in the semiconductor circuit chip, and being configured to provide a first output signal, a second functional element having a second electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress present in the semiconductor circuit chip, and being configured to provide a second output signal in dependence on the second electronic functional-element parameter and the mechanical stress, and a combination means for combining the first and second output signals to obtain a resulting output signal exhibiting a predefined dependence on the mechanical stress present in the semiconductor circuit chip, the first and second functional elements being integrated on the semiconductor circuit chip and arranged, geometrically, such that that the first and second functional-element stress influence functions ar

Abstract: Systems and methods for Current Management of Digital Logic Devices are provided. In one embodiment a method for calibrating a digital logic circuit current management system is provided. The method comprises activating one or more synchronous logic paths of a plurality of synchronous logic paths within the digital logic integrated circuit; sampling a voltage powering the digital logic integrated circuit while activating the one or more synchronous logic paths; storing one or more data samples representative of the sampled voltage; and calculating a bypass current setpoint based on the one or more data samples, wherein the bypass current setpoint specifies one or more bypass current characteristic to prevent the voltage powering the digital logic integrated circuit from dropping below a reference voltage.

Abstract: A calibration circuit calibrates an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance. The calibration circuit outputs a calibration signal carrying information for calibrating the capacitor and includes a calibration loop.

Abstract: A method for automated calibration of an avalanche photodiode receiver includes measuring two values of avalanche photodiode biases at two successive times, measuring and comparing a bit error rate corresponding to each value. When the bit error rate of the second value is equal to or greater than the bit error rate of the first value, then a third value and a fourth value of avalanche photodiode bias closer together are measured. When the bit error rate of the fourth value is smaller than the bit error rate of the third value, two subsequent values as third value and fourth value are measured, and an optimum avalanche photodiode bias when the bit error rate of the fourth value is equal to the bit error rate of the third value is measured.

Abstract: The present invention provides a system and method for controlling one or more light-emitting elements which are driven by forward currents to generate mixed light for use, for example, through a luminaire. The system has one or more light sensors for acquiring feedback optical sensor data and a user interface for providing reference data representative of a desired mixed light. The system also has a controller for transforming either the sensor data or the reference data into the coordinate space of the other and to determine a difference between the sensor and the reference data in that coordinate space. The controller is configured to adjust the forward currents during operating conditions so that the sensor data matches the setpoint data. The present invention also provides a system and method that can at least partially compensate certain temperature induced effects when transforming the optical sensor or the reference data.

Abstract: A system and method for adaptively providing a power supply voltage. The system includes an oscillator configured to receive an output voltage and generate a firs signal. The first signal is associated with a first frequency and a first period. Additionally, the system includes a frequency comparator configured to receive the first signal associated with the first frequency and a second signal associated with a second frequency and to generate a third signal if the first frequency and the second frequency are not equal, and a voltage regulator coupled to the frequency comparator and configured to generate the output voltage based on at least information associated with the third signal. The output voltage is received by a powered system, and the powered system is configured to receive a clock signal associated with a clock frequency. The clock frequency is equal to the second frequency.

Abstract: In a method for determining measurement errors in scattering parameter measurements, in particular for giving the measurement accuracy of a scalar or vector network analyzer, which has n measurement ports (n?1), on the basis of the measurements of the scattering parameters of at least one reference line with defined characteristic impedance, the characteristic impedance of the reference line is calculated and the reflection values of a one-port or two-port, realized by way of the reference line, are measured. The reflection values are renormalized to the known characteristic impedance of the reference line and the source match is calculated therefrom.

Abstract: There is provided a jitter amplifier for amplifying or attenuating a jitter component contained in an input signal, having a jitter demodulating section for demodulating the jitter component from the input signal and an amplifying circuit for amplifying or attenuating the jitter component by controlling phase of the input signal based on the jitter component.

Abstract: There is provided a calibration apparatus for calibrating a jitter measuring circuit for outputting a jitter measuring signal corresponding to a value of jitter contained in an input signal, having a signal inputting section for sequentially inputting the first input signal having first period and the second input signal having second period to the jitter measuring circuit and a gain calculating section for calculating a gain in the jitter measuring circuit based on the jitter measuring signals to be outputted out of the jitter measuring circuit respectively with respect to the first and second input signals.

Abstract: A method and apparatus provides high-accuracy measurements of an electrical parameter across a broad range of parameter input values. In one embodiment, an intelligent electronic device (IED), e.g., a digital electrical power and energy meter, with a plurality of independently-adjustable gain factors measures a parameter, and calculates and stores calibration factors associated with known values of the measured parameter. The IED or meter applies the stored calibration factors when measuring unknown values of the measured parameter, to improve the accuracy of the measurement.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and tennination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be updated while signals (e.g, clock or data) are transmitted. Some embodiments identify elements in a high-impedance state by examining incoming signals.

Abstract: A variable reference voltage circuit controllable in closed loop, for calibrating off-chip and on-chip drivers, margining and optimizing a reference voltage, for interfaces such as DDR2 or any other suitable interface. In one example, the on-chip variable reference voltage circuit, coupled to external fixed reference voltage, includes control logic and an array of switchable resistor elements (pull-up and pull-down resistors) that may each be selectively switched in or out of the circuit to change the reference voltage being supplied to an on-chip receiver.

Abstract: According to embodiments of the present invention, an automatic trim or calibration for a temperature sensor of a chip or memory device is performed on that chip. An embodiment of the present invention includes a calibration unit that increments trim or calibration values provided to the chip temperature sensor and stored in a calibration register. The calibration unit retrieves status bits from the temperature sensor indicating a measured temperature for each calibration value and compares those bits to a reference or target value associated with a target temperature and stored in a reference register. When the status bits satisfy the comparison, the corresponding calibration value is identified as the proper calibration value for the temperature sensor and is subsequently used by the temperature sensor for temperature measurements.

Abstract: A meter device for measuring electrical energy is provided. The meter device includes circuitry for measuring at least one parameter of electrical energy provided to the meter device. A storage device is provided for storing at least one calibration factor for compensating for errors associated with at least one of at least one external current transformer (CT) and at least one external potential transformer (PT) that operates on the electrical energy provided to the meter device. At least one processor is provided for processing the at least one calibration factor for adjusting the measuring for compensating for the errors when measuring the at least one parameter of electrical energy.

Abstract: A calibration device is provided for use with automatic test equipment (ATE). The calibration device includes circuitry having a fanout circuit. The compare-side fanout circuit has an input connected to a first channel of the ATE and outputs connected to N (N>1) channels of the ATE, where the N channels do not include the first channel. The ATE propagates an edge on the first channel, and the fanout circuit transmits the edge to the N channels. Optionally, a calibration device for use with automatic test equipment includes a drive-side circuit. The drive-side circuit includes circuitry having multiple inputs connected to N (N>1) channels of the ATE and an output connected to a second channel of the ATE that is not one of the N channels. The ATE propagates an edge on each of the N-channels and the circuitry propagates each edge to the second channel of the ATE.

Abstract: A method is provided for calibration of a vectorial network analyzer, having n measurement ports (n>1) and at least m measurement sites with n+1<m<2n. Calibration includes measurement of three different n-port reflection standards connected between the measurement ports in any sequence, and measurement of different transmission standards connected between two measurement ports, and mathematical determination of the error coefficients of the network analyzer and the error-corrected scattering matrices [Sx] of the n-port calibration standards. The reflection standards, similar to shorts and opens, are unknown and the reflection standard implemented by wave terminations is known, but can be different at each n-fold one-port. The measurement of the transmission standards occurs on a transmission standard known in length and attenuation, which is implemented on each possible two-port by different combination of measurement ports.

Abstract: Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

Abstract: Provided are systems, methods and techniques for, inter alia, processing an input signal. In one representative embodiment, samples of an input signal that represents a physical quantity are obtained and then transformed from an original domain into a plurality of coefficients in a transform domain, using an over-complete transform, such that the plurality of coefficients is sufficient to redundantly reconstruct the input signal samples. The coefficients are then modified independently of each other by applying a correction function, thereby obtaining a set of corrected coefficients, and the set of corrected coefficients is transformed back to the original domain. According to this embodiment, the correction function was determined by using a set of training pairs, each training pair including an uncorrected signal and a corrected signal, and by reducing a specified aggregate measure of error between the uncorrected signal and the corrected signal in the original domain across the training pairs.

Abstract: Labeling asymmetric network cables for improved network clock synchronization. Time asymmetries between pairs in a network cable are identified and associated with individual cables. This time asymmetry information is used to improve clock synchronization according to the IEEE-1588 standard. The time asymmetry information may be stored in a database and associated with a serial number on the cable, or may be associated with the cable in human and/or machine readable form.

Abstract: An impedance matching circuit performs a ZQ calibration for a test on a wafer process of a semiconductor memory device. The impedance matching circuit of the semiconductor memory device includes a first pull-down resistance unit, a first pull-up resistance unit, a second pull-up resistance unit and a second pull-down resistance unit. The first pull-down resistance unit supplies a ground voltage to a first node in response to a calibration test signal. The first pull-up resistance unit calibrates its resistance to that of the first pull-down resistance unit to thereby generate a pull-up calibration code. The second pull-up resistance unit supplies a supply voltage to a second node in response to the pull-up calibration code. The second pull-down resistance unit calibrates its resistance to that of the second pull-up resistance unit to thereby generate a pull-down calibration code.

Abstract: The current drawn by a precision resistor that is selectively connected across a load is utilized to calibrate a current sensed by current sensing device that is connected in series with the load.

Abstract: A calibrator for field devices is provided. In one aspect, the calibrator has the ability to communicate in accordance with at least two process communication protocols, and tests an attached process connection before engaging communication. In another aspect, the calibrator includes isolation circuitry to facilitate compliance with at least one intrinsic safety requirement, while communicating with field devices using an all-digital process communication protocol. In another aspect, a method of calibrating field devices is provided which accesses device descriptions of the field devices to generate calibration tasks.

Abstract: A method for reducing an effect of a disturbance signal on an output of a dynamic system. The method includes generating an increment of the disturbance signal, and modifying an incremental signal input to the dynamic system based on the increment of the disturbance signal.

Abstract: A measure system for signal measurement is introduced. The measure system simplifies the effort for a signal measurement in many applications. The application for a signal measurement is, for example, computation of a signal average value. The measure system includes a digital computation circuit together with an analog to digital converter (ADC) to constitute a compact signal measurement component. With the proposed design, a general microcontroller can proceed with a signal level sense and control with very few CPU power. In addition, the proposed system can be integrated with other analog or digital signal processing circuitry to form a single silicon chip.

Abstract: An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.

Abstract: A method and apparatus are provided for implementing automatic-calibration of a Time Domain Reflectometer (TDR) probing apparatus. A calibration procedure is performed automatically each time a TDR probe is moved from a device under test (DUT). A current calibration TDR waveform is obtained and compared with a reference calibration TDR waveform, checking for deviations between the current and reference measurements. If a deviation is detected, then the user is notified and calibration is failed.

Abstract: An apparatus and method for internally calibrating a direct conversion receiver (DCR) through feeding a calibration signal via ESD protection circuitry is disclosed. The apparatus includes an internal signal generator for generating a calibration signal, a front-end input stage for receiving an RF signal at an input node, an ESD protection unit for protecting against electrostatic discharge, and a switch unit coupled to the ESD protection unit, for selectively passing a calibration signal to the front-end input stage, whereby the connection of the switch unit and the ESD protection unit means that when the DCR is operating in normal mode, the switch unit will not affect the noise performance and matching of the receiver.

Abstract: An averaging circuit includes an averaging unit and an offset compensation unit. The averaging unit generates an average signal from first and second input signals. The offset compensating unit is coupled to the averaging unit for conducting away bias currents from the averaging unit for preventing an offset in the average signal when any of the first and second input signals is too low or too high.

Abstract: A method and apparatus for fine tuning a memory interface includes receiver operative to receive an input signal. The method and apparatus includes a clock counter operative to calculate a time value based upon the timed sequence determined by the reception of the input signal. The method and apparatus further includes a comparator coupled to receive an input strength indicator signal from the receiver and operative to generate a comparative strength signal based on the comparison of the input signal strength indicator signal and a reference strength signal. Furthermore, the method and apparatus includes a tuner coupled to the clock counter so the tuner receives the time value from the counter, and coupled to the comparator to receive the comparative strength signal from the comparator, whereupon the tuner then generates a tuning signal utilized for an iterative tuning process to fine tune a memory interface.

Abstract: To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer.

Abstract: A system and methods for calibrating a memory device are provided. More specifically, a technique for internally generating a test pattern within a memory device and driving the test pattern to a memory controller for synchronization and calibration is provided. An internal test pattern may be generated along the write bus within a memory device, employing elements already present for high speed memory devices. The test data may be looped back from the write bus to the read bus and transmitted to the memory controller for calibration. The loop back function may be implemented without accessing the memory array.

Abstract: A method for calibrating a parameter of an IC, using an external device so as to calibrate an analog control parameter of an internal analog circuit in the IC. The external device is used in a detecting mode so as to detect whether the analog control parameter is beyond a pre-determined range. If the analog control parameter is beyond the pre-determined range, the external device is used in a calibrating mode so as to obtain a calibrated value and the calibrated value is then written into the internal analog circuit in the IC. The external device is used for detection and calibration repeatedly until the analog control parameter is within the pre-determined range. When the analog control parameter is within the pre-determined range, the calibrated value is written into a non-volatile memory in the IC.

Abstract: A method is presented for deriving gamma for a display monitor that does not involve color matching tasks. The method includes displaying a test pattern to a user on the display monitor. The test pattern includes at least one of a pattern of alternating light and dark regions displayed to the user at different gamma correction levels, or a grayscale character string displayed to the user at different digital gray levels against a background of two known luminance levels. Input is received from the user as to at least one of a gamma correction level that results in the pattern of alternating light and dark regions having light and dark regions of perceived equal size, or a digital gray level for the grayscale character string that results in maximum legibility of the text string against the two known background luminance levels. Gamma is derived for the display monitor based upon the user input.

Abstract: Calibration of a sensor circuit that includes a sensor, a temperature measurement circuit and a signal processing path. The sensor senses a physical parameter to be measured and generates an electrical sensor output signal representing the physical parameter. The temperature measurement circuit outputs a measured temperature. The signal processing path is coupled to the sensor so as to receive the electrical sensor output signal and use the measured temperature to compensate for temperature variations in the electrical sensor output signal. During calibration, the output voltage of the signal processing path is measured at multiple temperatures, and at multiple values of the physical parameter being measured at each temperature while the signal processing path is disconnected from using the measured temperature of the temperature measurement circuit.

Abstract: A method and apparatus for identifying echo sources in a communication path. A system that incorporates teachings of the present disclosure may include, for example, an echo measurement device (EMD) having a transmit module to transmit an echo canceller deactivation signal in a communication path of the communication system, wherein the echo canceller deactivation signal deactivates one or more echo cancellers in said communication path. The transmit module can also transmit a test signal in the communication path which is looped back at an end point identified as having an echo problem, wherein the test signal is transmitted at a remote location from the end point. The EMD can further include a detection module to detect one or more echo signals associated with the test signal. Additional embodiments are disclosed.

Abstract: A system, method and computer program product according to one embodiment are provided for calibrating an RFID interrogator. A signal is sent from an interrogator to a calibration device. A backscatter signal is received from the calibration device. The backscatter from the calibration device is analyzed. An outgoing signal strength of the interrogator is adjusted based on the analysis. In a system, method and computer program product according to another embodiment, the interrogator is set to selectively respond to tags returning a backscatter signal strength selected based on the analysis. In a system, method and computer program product according to another embodiment, comparison criteria is selected based on the analysis of the backscatter signal. An RF device is instructed to store the comparison criteria, which is then used by the RF device to selectively respond to an interrogator signal having at least a desired strength.

Abstract: A metal detector adapted to generate a transmit search signal and to receive a receive search signal, and to analyse such received search signal, wherein the detector is adapted to allow a selection of operating parameters for each of these functions, said selection being effected by the storage as data in a memory of such selection, characterised in that the detector is adapted to allow such stored data to be modified in accordance with data in an external store, further characterised in that there is a digital data communication transmission program, adapted to effect a transmission of some or all of the stored data through a data transmission means to enable a further metal detector to receive and store for use in such further detector the said data.

Abstract: A system and method are provided for determining a light output of a light emitting diode (LED) in a scanner. The system includes a processor circuit to execute current control logic to obtain an optimum light output from the LED. The current control logic repeatedly applies increasing or decreasing currents to the LED until a saturation point is identified. This may be accomplished, for example, by comparing two measures of the light output of the LED for two different currents applied to the LED. When a difference equaling a predetermined threshold between the two measures is detected, then the saturation point is identified.

Abstract: Circuits, methods and apparatus are provided to reduce skew among signals being received by a data interface. Signal path delays are varied such that data and strobe signals received at a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration circuitry provides skew adjustment of each data signal path by determining one or more delays in each data signal path and strobe signal path based on relative timings of test signals. The rising or falling edges may be used for this alignment.