Abstract: Reconfigurable sensor and method for selectively reconfiguring a sensor are provided. The reconfiguration of the sensor may be performed according to applicable requirements for sensing the position of an object. The method allows providing an array of sensing elements. The method further allows selecting at least one of the sensing elements of the array to supply a sensing element output signal. One or more operational parameters of the one sensing element may be adjusted to meet the applicable sensing requirements.

Abstract: In a method for optimizing an ion detector a control voltage, such as in a mass spectrometry system, an array of mass scan data is acquired. Based on the size of the largest peak in the array or part of the array, a determination is made as to whether the current detector gain should be changed to a new detector gain. If the current detector gain should be changed, the control voltage for the subsequent mass scan is adjusted to a new control voltage corresponding to the new detector gain. The data are scaled based on the current detector gain. In another method, a gain versus control voltage curve is generated for calibration. These methods may be implemented by hardware, software, analog or digital circuitry, and/or computer-readable or signal-bearing media.

Abstract: A high resolution potentiometer implemented using at least two digital potentiometers connected in parallel. Each digital potentiometer is controlled to provide a corresponding resistance value, and a desired resistance value is attained by such control. The resolution is high in some range of desired resistance values and low in other ranges. A high resolution in a desired range can be attained by connecting another resistor in series with the digital potentiometers connected in parallel.

Abstract: A method for conserving power begins by measuring processing speed of at least a portion of an integrated circuit (IC) to produce measured processing speed. The portion of the IC may be a test circuit, a critical path of the IC, and/or a replica of the critical path of the IC. The processing continues by comparing the measured processing speed with a critical processing speed for the at least a portion of the integrated circuit. The processing then continues by adjusting supply voltage to the integrated circuit to reduce power consumption of the integrated circuit when the measured processing speed compares favorably to the critical processing speed.

Abstract: An instrument which utilizes this invention is a pulse generator which has adjustable rise and fall time. The generation of timing of pulses is under control of a digital circuit, and the timing of the beginning and end of each pulse and thus duty cycle is precise. The pulse generator also has an analog-to-digital converter that is used to measure voltages internal to the instrument. Voltage measurements are used to calculate the rise and fall times of the pulses. The rise and fall time of the pulses are adjusted based upon mathematical calculations. Control of rise and fall times is implemented using circuitry internal to the pulse generator. Rise time and fall time circuitry adjusts the rate of change of voltage (dv/dt) on the pulses generated. Rise time and fall time are independently adjustable.

Abstract: A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element.

Abstract: Calibration is performed for the testing of a device under test. A first port of the device under test is connected to a port of a calibration module. A second port of the device under test is connected to a first port of a device tester. A third port of the device under test is connected to a second port of a device tester. The device tester performs measurements by the device tester to obtain calibration parameters. In response to commands from the device tester, the calibration module changes termination values at the port of the calibration module. The changing of the termination values is performed without physical disconnection of the port of the calibration module from the first port of the device under test.

Abstract: A sensor signal conditioner for temperature compensating, linearizing, and amplifying sensor signal output in electronic instrumentation circuits includes a programmable gain instrument amplifier having an input connected to a sensor; and a comparator for comparing an output voltage of the amplifier to a desired output voltage value. A micro-controller controls the instrument amplifier gain and offset. A mode switch converts an I/O pin to input the desired output voltage value in programming mode and connects the I/O pin to the amplifier output in user mode. A memory stores a programming protocol in the sensor signal conditioner so that in programming mode, the protocol stores programmed values and linearly fits the programmed values to set trim values for temperature compensating, linearizing, and amplifying the instrument amplifier output. The I/O pins and mode switches of several sensor signal conditioners can be controlled simultaneously to mass produce transducers using the sensor signal conditioner.

Abstract: A system for automatic calibration of instruments (S) having varying cross-sectional dimensions within a predetermined range and having detectable elements (110, 112, 113, 114) thereon for computer-aided surgery, comprising a calibration base (C) having detectable elements (43, 44, 46, 48) secured thereto for detecting a position and an orientation thereof in space by sensors (204) connected to a position calculator (202). The calibration base is adapted to receive and to releasably secure a working shaft (100) of any of the instruments (S) and provides an abutting surface (14) for a tip (102) thereof in such a way that a position and orientation of the tip (102) of the instrument (S) secured therein is calculable when working shaft cross-section dimensions thereof are known. The position calculator (202) receives instrument data (214) and calibration data (218) from an operator through a user interface (206) and stores the instrument data (214) and calibration data (218) for subsequent calibrations.

Abstract: An analog-to-digital converter (ADC) exhibiting an uncorrected non-linear transfer function receives measured analog voltage amplitudes and outputs uncorrected digital values. A calibration circuit receives each uncorrected digital value and outputs a corrected digital value. The measured analog voltage amplitudes received by the ADC and the corresponding corrected digital values output by the calibration circuit define points approximating an ideal linear transfer function of the ADC. The calibration circuit performs piecewise-linear approximation of the uncorrected transfer function and associates each uncorrected digital value with the applicable linear segment that passes through a segment endpoint on the uncorrected transfer function. The calibration circuit calculates each corrected digital value using calibration coefficients associated with the applicable linear segment, such as the slope of the linear segment.

Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.

Abstract: A calibration system and method determines magnitudes of traveling-waves at a non-coaxial plane of a scattering (S) parameter measurement device that includes an adapter link between the non-coaxial plane and a coaxial plane. A calibration is conducted at an interface between the adapter link and the coaxial plane to derive coaxial error terms for the S-parameter measurement device. In addition, a power meter measurement is conducted at the coaxial plane to obtain power wave measurements using the coaxial error terms. A calibration is also conducted at an interface between the adapter link and the non-coaxial plane to derive non-coaxial error terms for the S-parameter measurement device. The power wave measurements, coaxial error terms and non-coaxial error terms are used to calculate the magnitude of one of the traveling-waves at the non-coaxial plane.

Abstract: Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.

Abstract: Various methods, systems and apparatuses having an integrated circuit that contains a calibration circuit having a series of delay elements to receive a reference signal. The reference signal establishes a standard unit of time. The calibration circuit also generates one or more calibrated delay signals derived from the reference signal. The one or more calibrated delay signals are precise to a known fraction of the standard unit of time.

Abstract: Offset adjustments for both differential and single-ended measurements are accomplished in the same probe or system. Different variable offsets are provided for the positive and negative inputs of a differential amplifier, and a variable offset adjustment is provided to remove differential amplifier output offset. Common mode and reduced dynamic range problems for both differential and single-ended measurements are eliminated. All or desired portions of required functions may be implemented using discrete or DSP approaches.

Abstract: An on-signal calibration system I and Q signals of a transmitter to remove distortions in the RF output signal. The transmitter generates I and Q values and converts, modulates and combines the I and Q values into the RF output signal for transmission. The calibration system includes a detector, a sampler, a selector, an imbalance estimator, and an IQ corrector. The detector senses the RF output signal and provides a detection signal indicative thereof. The sampler samples the detection signal and provides digital samples. The selector selects from among the digital samples that correspond to predetermined ranges of the I and Q values, or otherwise predetermined selection boxes at predetermined phases. The imbalance estimator determines at least one imbalance estimate based on selected digital samples. The IQ corrector corrects the I and Q values using at least one imbalance estimate.

Abstract: A chip includes CPU (12), memories (13,14) for programs and data, peripheral units (18,19) for interacting with the outside world, and an internal RC oscillator (17) for providing clock signals. One of the peripheral units (18) includes a timer counter incremented at a frequency derived from the RC oscillator. The method does not try to change the frequency of the RC oscillator. Instead, an external calibration source (21) is connected to a capture input of the timer unit to provide a signal having a reference frequency, e.g. the mains frequency. The counter is sampled on active edges of that signal, and the sampled values are processed to derive a calibration ratio. After these calibration steps, a software correction is applied to parameters handled by programs stored in memory based on the calibration ratio to compensate for frequency variations of the RC oscillator.

Abstract: An improved apparatus and method for tuning a device under test uses a spider diagram-like chart that provides the operator with visual cues as to the tuning status of a device under test (DUT). The spider diagram may be displayed on a graphical user interface (GUI), along with various adjustment points or potentiometers. The spider diagram includes a unit circle that represents the acceptable bounds for each measured parameter. Overlaying the unit circle is a polygon of three or more sides, with a vertex of each angle of the polygon representing a measured parameter. The polygon changes shape as the various potentiometers are adjusted. When a measured parameter value is at the center of its allowable range, the vertex of the angle corresponding to that measurement lies near the center of the unit circle. When a measured parameter is at its upper or lower bound, the vertex lies on the unit circle.

Abstract: A method and apparatus are used to calibration a Vector Network Analyzer (VNA). The method includes providing a calibration module with a single port, providing within the calibration module a set of reflecting components with known scattering parameters, providing control signals to the calibration module through the single port, providing the known scattering parameters to the VNA through the single port, coupling one of reflecting components to the VNA, measuring scattering parameters, and comparing the measured scattering parameters with the known scattering parameters. The apparatus includes a calibration module and a controller module. In one embodiment, the calibration module includes a set of reflecting components, a memory that stores the characterization data, and a current source which sends characterization data in the form of current pulses to the controller module. The controller module includes a voltage source that generates the control signals used by the calibration module.

Abstract: A self-calibrating sigma-delta converter (SCADC) functions in a calibration mode and in an operational mode. In the calibration mode, a test circuit of the SCADC generates test signals that are periodic rectangular voltage waveforms. Each test signal has a dc component with a precise voltage amplitude, as well as harmonic components. A low-pass filter of a sigma-delta converter (SDC) within the SCADC filters out the harmonic components. A digital calibration processing circuit within the SCADC uses the precise voltage amplitudes to generate digital correction factors that compensate for dc offset error, gain error and INL error of the SDC. In the operational mode, the SDC receives an analog operational signal and outputs an operational digital data stream. The digital calibration processing circuit uses the correction factors to compensate for dc offset error, gain error and INL error in the operational digital data stream and outputs a corrected digital data stream.

Abstract: A method is disclosed for conditioning a periodic analog signal (SIN, COS) to predetermined, positive and negative desired peak values by adjusting the signal (SIN, COS) using multiplicative correcting steps, which increase or decrease the signal amplitude, and additive correcting steps, adding to the signal a constant which adjusts the signal level in a positive or negative direction, wherein the presence of a current actual peak value is detected said method providing that the difference between the actual peak value and the predetermined desired peak value is stepwise reduced by repeated adjustment of the signal (SIN, COS) using modifying steps within a part of a period of the signal (SIN, COS), each modifying step including exactly one multiplicative and exactly one additive correcting step.

Abstract: Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. An offline algorithm for calculating the parameters of data-dependent noise predictive filters 304A-D is presented which has two phases: a noise statistics estimation or training phase, and a filter calculation phase. During the training phase, products of pairs of noise samples are accumulated in order to estimate the noise correlations. Further, the results of the training phase are used to estimate how wide (in bits) the noise correlation accumulation registers need to be. The taps [t2[k], t1[k], t0[k]] of each FIR filter are calculated based on estimates of the entries of a 3-by-3 conditional noise correlation matrix C[k] defined by Cij[k]=E(ni?3nj?3|NRZ condition k).

Abstract: Embodiments of the present invention enable the matching of pull-up and pull-down driver strengths of a slave device (DDRII SDRAM), i.e., the P-channel/N-channel driver pull-up/pull-down Ron and also calibrates the P-channel/N-channel pull-up/pull-down drivers in their linear region of operation. Specifically, embodiments of the present invention may use the DDR-II Off Chip Driver (OCD) protocol for calibration, in addition to using circuit techniques to calibrate the slave driver pull-up Ron within 1 LSB of the pull-down Ron.

Abstract: The present invention relates to a current reference system comprising a selectively activatable high current reference circuit operable to generate a reference calibration circuit when activated and a low current calibrated reference current circuit operable to generate a reference current having a value based upon a control data. The system further comprises a control circuit operable to activate the selectively activatable high current reference circuit during a calibration period. The control circuit is further operable to vary a characteristic of the low current calibrated reference current circuit in a predetermined fashion while comparing another characteristic of the low current calibrated reference current circuit to a predetermined value. The control circuit then identifies a calibration condition based on the comparison, and generates the control data associated therewith.

Abstract: The present invention discloses wave frequency calibration method and device for remote controller, the device of the present invention comprises an oscillator for generating a base wave; a storage for storing a match value; a modifier for generating a modified signal; and a processor connected to the oscillator, the storage and the modifier, the processor change the match value until the modified signal disappear and store the most updated match value in the storage to assure the receiving end of the remote controller can receive the signal with correct frequency. Incorporating with a RC oscillator, the wave frequency calibration method and device for remote controller of the present invention will avoid the problem of the bias of wave, which enables the RC oscillator to be a oscillator that can be used commonly in a regular remote controller.

Abstract: A crystal-less keyless entry system includes a micro controller, a timing circuit, a memory, and a radio frequency circuit. The memory and timing circuit are a unitary part of the microprocessor. The memory is programmed with a compensation that adjusts an output frequency of the timing circuit such that the output frequency of the timing circuit does not coincide with a frequency discontinuity that occurs within an output of the timing circuit. A method of calibrating the crystal-less keyless entry system includes programming the temperature compensation and a voltage compensation in the memory.

Abstract: A method for calibration of memory circuits is provided that adjusts memory circuit output parameters based on data eye measurements. Data eye patterns from the memory circuit outputs are measured by the memory controller for different settings of the memory circuit output parameters. Memory circuit output parameters can be adjusted to settings that correspond to widest average data eye widths, highest average data eye heights, or other suitable criteria.

Abstract: The present invention provides a high precision, low cost laser power calibration system. First, the photo signals output from a standard photo diode are received by a photo calibration system; then a set of standards consisting of the corresponding current signals and the power signals are saved in an EEPROM. Finally, the photo diode to be calibrated can be calibrated using the present system in accordance with the calibration standards.

Abstract: A method and system for calibrating a time constant within an integrated circuit. A voltage storage element is charged, and the time required to achieve a reference voltage on the storage element is measured. The measured time is compared to a desired time. It necessary, an adjustable impedance is modified to change the charging time, and the cycle may be repeated until the charging time matches the desired time. In this novel manner, an actual RC time constant, as rendered in a particular integrated circuit, is measured and potentially adjusted to match a desired time constant. Advantageously, configuration information of the adjustable impedance may be communicated to other circuitry within the integrated circuit to enable such circuitry to implement the same RC time constant in analog signal processing. Consequently, embodiments of the present invention overcome incidences of wide tolerance in passive components implemented in integrated circuits. Beneficially, no external test equipment is required.

Abstract: A method and a vector network analyzer compensate for unequal source match and load match of a test port of the vector network analyzer. The method characterizes the source match and the load match, computes a delta-match factor from the characterized source match and load match, and uses the delta-match factor to compensate for the difference. The method compensates S-parameter data for a device under test measured by the vector network analyzer. The vector network analyzer comprises a computer program that, when executed by a controller, implements a calibration compensation.

Abstract: A calibration unit is designed to contain an oscillator circuit whose frequency is determined by the RC time constant of a resistor, which is of the same type as the resistor used in the filter circuit that is to be calibrated, and of a capacitor device which has been set to a fixed value. The oscillator frequency is converted into counting pulses, and the number of counting pulses which is counted in a modulo binary counter within a time interval is transmitted as a digital calibration signal for a calibratable capacitor device in the filter circuit in order to calibrate the latter.

Abstract: A method of addressing a memory device on a memory module includes determining whether a command has been issued to the memory module. An evaluation state is entered if the command has been issued. While in the evaluation state, it is determined whether an identification signal has been issued for the memory device to initiate action. Action is initiated if the identification signal indicates that the memory device is to respond to the command issued.

Abstract: Calibration of received signal strength indication (RSSI) within a radio frequency integrated circuit (RFIC) begins by concurrently enables a transmitter portion and receiver portion. With both the transmitter and receiver enabled, the RFIC provides a zero input to the transmitter portion, where the zero input is an effective zero input based on the input circuitry of the transmitter portion. The RFIC then measures, via the receiver portion, the received signal strength of the RF signal generated by the transmitter portion regarding the zero input signal. The RFIC then compares the measured received signal strength with a desired zero input signal strength value. If the measured received signal strength compares unfavorably with the desired zero input signal strength value (e.g.

Abstract: A method and an apparatus for controlling system parameters, in particular for controlling the voltage applied to piezoelectric elements (10, 20, 30, 40, 50, 60) within a circuit (A) for charging and discharging piezoelectric elements (10, 20, 30, 40, 50, 60) are described. The method is characterized by modifying at least one control parameter for the control of a system parameter, in particular a target voltage for the voltage applied to a piezoelectric element (10, 20, 30, 40, 50, 60), in view of at least one systematic error occurring during a first control procedure of the system parameter to obtain a corrected control parameter for a second and/or a further control of the system parameter. The apparatus is particularly eligible for use with the inventive method.

Abstract: The number of measurements needed to calibrate an electrical device is reduced. Apparatus and methods minimize output of one or more unwanted signals by determining a calibration setting, in a minimal number of measurements, from determined distances to a best setting. Each distance to a best setting can be determined as a function of the characteristic of the unwanted signal and the measured unwanted signal level. A calibration setting point can be determined by searching for a setting point having a lowest sum of distance errors determined from the calculated distances and from the measured and non measured setting points. The techniques and apparatus are useful for minimizing a number of measurements that would be needed for determining a setting that substantially prevents generation of unwanted output signals, such as carrier leakage (LO-leakage) and unwanted sidebands, and for quickly determining whether an acceptable calibration setting exists for a device.

Abstract: A distance detection apparatus cancels signal delay times of transmission and reception circuits (13, 15, 22, 25), which are causes of the errors of distance detection, by receiving a transmission signal turned back directly to measure the difference between the transmission timing and the reception timing at that time, and by setting the value obtained by the measurement as a correction value at the time of obtaining the measurement distance.

Abstract: The invention is directed to various calibration techniques for calibrating an imagining device such as a display device, a printer, or a scanner. The techniques may involve characterizing the imaging device with a device model such that an average error between expected outputs determined from the device model and measured outputs of the imaging device is on the order of an expected error, and adjusting image rendering on the imaging device to achieve a target behavior. The invention can achieve a balance between analytical behavior of the imaging device and measured output. In this manner, adjustments to image rendering may be more likely to improve color accuracy and less likely to overcompensate for errors that are expected.

Abstract: On-site, in-situ verification of production test equipment. Verification of production test equipment is performed using a mobile rack of electronic test equipment which may be moved through a production environment. Calibration tests are only performed on those measurements critical to the production environment, not over the operating range of the equipment. Calibration tests may be performed in parallel to reduce the time required.

Abstract: A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.

Abstract: A system and method are disclosed which provide for flexible and accurate test apparatus error value calculation. Error value calculation of a testing apparatus requires at least one unique measurement for each unknown error value using the equation that relates the measured response, the predicted response and the error value. When more equations than unknowns can be acquired, the system of equations is over-determined and an improvement of accuracy is possible, but accuracy may be lost when the predicted responses are not trusted to the same degree. The disclosed system and method provide the increased accuracy of an over-determined system, while accounting for predicted responses of varying degrees of trust.

Abstract: Combining signal images includes receiving signal images and performing the following to yield a weighted sum for at least one signal image. A phasor is generated from a signal image in accordance with a correlation reference, and a phase alignment of the signal image is adjusted to yield an adjusted signal image. A signal magnitude estimate is determined in accordance with the phasor, and a weight is determined in accordance with the signal magnitude estimate, where the weight reflects a signal-to-noise ratio of the signal image. The weight is applied to the adjusted signal image to yield a weighted sum for the signal image. The weighted sums are combined to yield a combined signal output.

Abstract: A signal conditioning amplifier receives an input signal from an input such as a transducer. The signal is amplified and processed through an analog to digital converter and sent to a processor. The processor estimates the input signal provided by the transducer to the amplifier via a multiplexer. The estimated input signal is provided as a calibration voltage to the amplifier immediately following the receipt of the amplified input signal. The calibration voltage is amplified by the amplifier and provided to the processor as an amplified calibration voltage. The amplified calibration voltage is compared to the amplified input signal, and if a significant error exists, the gain and/or offset of the amplifier may be adjusted as necessary.

Abstract: An integrated circuit has a loss of signal (LOS) system for detecting a loss of signal condition for an input data stream according to a LOS threshold. The LOS threshold specifies a minimum signal magnitude indicating the loss of signal condition. The integrated circuit includes a sampling circuit to sample a LOS signal, which receives a sampling threshold specifying a signal magnitude for a sampled signal above which the sampling circuit samples the sampled signal as a first digital value and below which the sampling circuit samples the sampled signal as a second digital value. A digital control circuit coupled to an output of the sampling circuit generates a calibrated digital representation of the sampling threshold according to a plurality of samples of the LOS signal. The calibrated sampling threshold is then used during loss of signal evaluation.

Abstract: An apparatus and method for calibrating a first sampling circuit with a second sampling circuit having a similar impulse response. The second sampling circuit includes a sample and hold circuit that provides an output indicative of the potential at the sampling circuit input of the second sampling circuit at a time determined by a signal at the trigger pulse input of the second sampling circuit. The apparatus includes a trigger pulse generating circuit for generating a sequence of trigger pulse pairs, each pair having a first pulse that is delayed relative to a second pulse. Each pulse is applied to a corresponding trigger input of the sampling circuits. The first sampling circuit is assumed to generate a kick-out pulse indicative of its impulse response when triggered by the first pulse. A controller measures the output of the second sampling circuit for each delay.

Abstract: An apparatus and method for independently adjusting or calibrating the characteristics of multiple drivers for output buffer circuits without significantly increasing the associated necessary circuitry is disclosed. A central control logic circuit initiates the calibration process of the drivers. A serial communication link is provided between the control logic and each of the output drivers. The serial link reduces the number of lines that are required to communicate between the central control logic and the multiple output drivers. The output drivers can be calibrated one at a time, and a handoff is made from one driver to the next to start the calibration of the subsequent driver.

Abstract: A pseudo noise generator is disclosed, in which a first arbitrary random number generator generates two groups of first random number signals respectively corresponding to divided Amplitude Probability Distribitions, which are obtained by dividing a specified Amplitude Probability Distribition into two parts at a specified level. A second arbitrary random number generator generates two groups of second random number signals respectively defined by a specified Pulse Duration Distribution and a specified Pulse Spacing Destribution at said specified level. Ones of said two groups of first random number signals are selected in accordance with said specified Pulse Duration Distribution and said specified Pulse Spacing-Destribution defined at said specified level.

Abstract: A programmable gain amplifier (PGA) controlled through a serial communications interface are fabricated on an integrated circuit (IC). A multiplexer (MUX) may also be included on the IC. The serial communications interface controls the gain of the PGA, MUX channel selection, and other functions of the PGA. Status of the PGA may also be obtained through the serial communications interface. By using a serial communications interface, the pin count of the PGA IC package may be kept to a minimum.

Abstract: A method for estimating the input power to a cable modem includes generating a look-up table containing AGC integrator accumulator values corresponding to selected frequencies and amplitudes. The look-up table is generated by first constructing a calibration matrix by inputting a plurality of calibration signals having known input frequencies and known input power levels into the cable modem's receiver, and recording AGC integrator accumulator values corresponding to several frequencies and power levels over a selected operating range as calibration points. Next, an interpolation and extrapolation process generates the look-up values corresponding to the frequencies and amplitudes in between the calibration points. During modem operation, the modem estimates the input power by checking the AGC integrator accumulator value corresponding to the input frequency and amplitude.

Abstract: A computer system measures bus signal distortion and then adjusts certain characteristics of the signal transmitted over the bus, or adjusts other characteristics of the bus or the load on the bus so that signal distortion is reduced. Distortion characteristics that may be measured include signal voltage overshoot and undershoot, and data setup and hold times. Characteristics of the signal and the system that may be adjusted include changing the slew rate of the signal, changing the data setup and hold times, and changing the load impedance on the bus.

Abstract: A method and a magnetic field and acceleration sensor for simultaneously sensing magnetism and acceleration are disclosed, the method comprising the steps of applying a current to first and second movable structures which are movable in a first direction, spaced from fixedly arranged first and second sensing electrodes, respectively, and arranged in a plane perpendicular to the first direction, applying magnetic field and/or acceleration signals to the first and second movable structures, detecting capacitance changes from the first and second sensing electrodes, the capacitance changes being caused by the distance change between the first and second movable structures and the first and second sensing electrodes, respectively, outputting a magnetic field signal by subtracting a signal detected from the second sensing electrode from a signal detected from the first sensing electrode, and outputting an acceleration signal by adding the signals detected from the first and second sensing electrodes.