Including Input/output Or Test Mode Selection Means Patents (Class 702/120)
  • Patent number: 10928885
    Abstract: Power reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method includes executing a voltage characterization service for a processing device of a computing apparatus to determine at least one supply voltage for the processing device, the voltage characterization service comprising a functional test that exercises the processing device at iteratively adjusted voltages in context with associated system elements of the computing apparatus. During execution of the voltage characterization service, the method includes monitoring for operational failures of at least the processing device, and responsive to the operational failures, determining at least one resultant supply voltage.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: February 23, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Patent number: 10694402
    Abstract: Image data of a node with which an orchestration module is associated is received. The node is an electronic device and the image data of the node is received in a language associated with the node. The image data of the node with which the orchestration module is associated is translated into a meta-language associated with an orchestrator network comprising the orchestration module and one or more other orchestration modules associated one or more corresponding nodes. A scope of information to provide from the orchestration module to the one or more other orchestration modules associated with one or more corresponding nodes is determined. The determined information is communicated to the one or more other orchestration modules in the meta-language understood by the orchestration module and the one or more other orchestration modules associated with one or more corresponding nodes.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: June 23, 2020
    Inventor: Mark Cummings
  • Patent number: 10671516
    Abstract: A method, device, and computer program product for testing code. The method includes identifying a plurality of test points in the code and a plurality of test values to be assigned to the plurality of test points. At least one of the plurality of test points is to be assigned with two or more test values. The method also includes comparing a target test case with a set of test cases. The target test case and the set of test cases are associated with the plurality of test points. The method further includes, in response to determining that each of combinations of the test values assigned to at least two of the plurality of test points in the target test case is present in the set of test cases, excluding the target test case from the set of test cases.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 2, 2020
    Assignee: EMP IP Holding Company LLC
    Inventors: Xiongfang Nie, Derek Quanhong Wang, Xiaoqiang Zhou
  • Patent number: 10673723
    Abstract: A dynamically reconfigurable interface for an automatic test equipment is disclosed where one or more synthetic instruments transmit the high speed signals as well as receive the high speed signals from a device under test so that testing can be performed at speeds higher than the ATE was originally designed to accommodate. Synthetic instruments are implemented on a field programmable gate array (FPGA) that operate at higher speeds than COTS instruments and can reach the frequencies that high speed I/O buses use. SIs can be created by configuring the FPGA, with different configurations creating different SIs. A single FPGA can house a number of SIs.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 2, 2020
    Assignee: A.T.E. SOLUTIONS, INC.
    Inventors: Louis Yehuda Ungar, Tak Ming Mak, Neil Glenn Jacobson
  • Patent number: 10651647
    Abstract: A bypass mechanism for a photovoltaic module which switches out the electronics and switches in a bypass mechanism.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 12, 2020
    Assignee: Solaredge Technologies Ltd.
    Inventors: Meir Gazit, Israel Gershman, Ehud Kirmayer, Leon Kupershmidt, Meir Adest
  • Patent number: 10592618
    Abstract: Parameters of a structure (900) are measured by reconstruction from observed diffracted radiation. The method includes the steps: (a) defining a structure model to represent the structure in a two- or three-dimensional model space; (b) using the structure model to simulate interaction of radiation with the structure; and (c) repeating step (b) while varying parameters of the structure model. The structure model is divided into a series of slices (a-f) along at least a first dimension (Z) of the model space. By the division into slices, a sloping face (904, 906) of at least one sub-structure is approximated by a series of steps (904?, 906?) along at least a second dimension of the model space (X). The number of slices may vary dynamically as the parameters vary. The number of steps approximating said sloping face is maintained constant. Additional cuts (1302, 1304) are introduced, without introducing corresponding steps.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: March 17, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Remco Dirks, Markus Gerardus Martinus Maria Van Kraaij, Maxim Pisarenco
  • Patent number: 10565059
    Abstract: A journal optimizer in a computer database system with an adaptive journal mechanism. The adaptive journal mechanism dynamically adjusts adaptive parameters of the journal optimizer to optimize the journal based on one or more journal conditions to more efficiently utilize system resources. The adaptive parameters used to adapt the optimization include aggressiveness parameters and the location of the optimizer, where the aggressiveness parameters specify the intensity of optimization of the journal by the journal optimizer. For example, the adaptive journal mechanism may dynamically adjust an adaptive parameter of the optimizer to increase optimization of the journal when the resource utilization indicates the resources are underutilized and decrease optimization of the journal when the resource utilization indicates resources are strained.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rafal P. Konik, Roger A. Mittelstadt, Brian R. Muras, Chad A. Olstad
  • Patent number: 10509073
    Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 17, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
  • Patent number: 10445763
    Abstract: Methods and apparatus for implementing forward looking optimizing promotions by administering, in large numbers and iteratively, test promotions formulated using highly granular test variables on purposefully segmented subpopulations. The plurality of test promotions are automatically proposed. The responses from individuals in the subpopulations are received and analyzed. The analysis result is employed to subsequently formulate a general public promotion.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 15, 2019
    Assignee: EVERSIGHT, INC.
    Inventors: David Moran, Michael Montero
  • Patent number: 10438230
    Abstract: Methods and apparatus for implementing forward looking optimizing promotions by administering, in large numbers and iteratively, test promotions automatically formulated using highly granular test variables on subpopulations. The responses from individuals in the subpopulations are received and analyzed. The analysis result is employed to subsequently formulate a general public promotion.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 8, 2019
    Assignee: EVERSIGHT, INC.
    Inventors: David Moran, Michael Montero
  • Patent number: 10438231
    Abstract: Methods and apparatus for implementing forward looking optimizing promotions by administering, in large numbers and iteratively, test promotions formulated using highly granular test variables on segmented subpopulations, whereby the test promotions are automatically generated. The responses from individuals in the subpopulations are received and analyzed. The analysis result is employed to subsequently formulate a general public promotion.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 8, 2019
    Assignee: EVERSIGHT, INC.
    Inventors: David Moran, Mark Wilson
  • Patent number: 10423808
    Abstract: An analog circuit design is described that solves Linear Programming (LP) or Quadratic Programming (QP) problems.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: September 24, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Sergey Vichik, Francesco Borrelli
  • Patent number: 10425273
    Abstract: A data processing system comprises: at least one each of a plurality of types of data processing module conducting different types of the data processing; data flows through which a series of different types of data processing is conducted on a message and a message subjected to the series of different types of data processing is sent to the destination; and a dispatcher distributes the message and a message subjected to the data processing by the data processing module to a subsequent data processing module, wherein the dispatcher conducts: detecting a specific data processing module in a specific status of being a bottleneck; determining the number of the specific data processing module to resolve the specific status by increasing the number of the specific data processing module; and setting the number of the specific data processing module to the number to resolve the specific status.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 24, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Masafumi Kinoshita, Tatsuhiko Miyata
  • Patent number: 10409629
    Abstract: A computer program product, system, and method for generating coded fragments comprises determining a set of available data protection plans; determining one or more parameters associated with a customer, a host, or a data protection system; generating a recommended host protection configuration for the host using the parameters, wherein the recommended host protection configuration includes one or more of the available data protection plans; and assigning the recommended host protection configuration to the host.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 10, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Assaf Natanzon, Saar Cohen, Matan Gilat, Amit Lieberman, Jehuda Shemer, Ravi V. Chitloor, Yossef Saad, Prasanna Malaiyandi, Naveen Rastogi
  • Patent number: 10393786
    Abstract: A test system for over the air (OTA) measurements of transceiver performance metrics of a device under test is provided. The test system comprises a device under test (DUT), at least one positioning device, at least one measurement antenna, and at least one measuring/control processor. The at least one measurement antenna is configured to establish a data link to the DUT and to transmit/receive test data to/from the DUT via the data link. The at least one positioning device is configured to adjust the position of the at least one measurement antenna around the DUT to specific measurement points, wherein the specific measurement points are distributed randomly around the DUT.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 27, 2019
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Heinz Mellein
  • Patent number: 10326434
    Abstract: In various embodiments, an electronic component is provided. The electronic component may include a supply bus configured to provide a supply voltage for an electronic circuit. The electronic component may further include a voltage-controlled oscillator, which is coupled to the supply bus and is configured to generate a clock signal with a clock frequency according to the supply voltage. The electronic component may further include at least one reference oscillator, which is configured to generate a reference clock signal with a reference clock frequency, and a comparator, which is coupled to the voltage-controlled oscillator and the at least one reference oscillator and is configured to compare the clock signal with the reference clock signal and, on the basis of the comparison, either to output the clock signal to the electronic circuit or to suppress it.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Walter Kargl, Albert Missoni
  • Patent number: 10243729
    Abstract: In a general aspect, a test method can include acquiring a plurality of value sets, each including values of a physical quantity or of logic signals, linked to the activity of a circuit to be tested when executing distinct cryptographic operations applied to a same secret data, for each value set, counting occurrence numbers of the values of the set, for each operation and each of the possible values of a part of the secret data, computing a partial result of operation, computing sums of occurrence numbers, each sum being obtained by adding the occurrence numbers corresponding to the operations which when applied to a same possible value of the part of the secret data, provide a partial operation result having a same value, and analyzing the sums of occurrence numbers to determine the part of the secret data.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 26, 2019
    Assignee: ESHARD
    Inventor: Hugues Thiebeauld De La Crouee
  • Patent number: 10140629
    Abstract: Methods and apparatus for implementing forward looking optimizing promotions by administering, in large numbers and iteratively, test promotions formulated using highly granular test variables on purposefully segmented subpopulations. The plurality of test promotions are associated with at least one behavioral economics principles. The responses from individuals in the subpopulations are received and analyzed. The analysis result is employed to subsequently formulate a general public promotion.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 27, 2018
    Assignee: Eversight, Inc.
    Inventors: David Moran, Michael Montero
  • Patent number: 10050618
    Abstract: A signal management circuit includes a first input terminal to receive a first signal. A first logic portion is coupled to the first input terminal and configured to provide a first output signal. A second logic portion is coupled to receive a second signal and configured to provide a second output signal. The second signal is based on the first output signal and the first signal. An output terminal is coupled to provide a third output signal based on the first output signal and the second output signal.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: August 14, 2018
    Assignee: NXP USA, INC.
    Inventor: Adam Jerome White
  • Patent number: 10037264
    Abstract: Disclosed is a method and system for classifying test cases. In one implementation, the method comprises creating a test step master list comprising a plurality of test case, one more test step associated with the plurality of test case, and a test step identification number associated with the one more test step. Further, the method comprises generating a sequence diagram for each of the plurality of test cases based on the test step master list. Furthermore, the method comprises classifying, by the processor, each of the plurality of test cases in to an independent test case or an asynchronous test case or a synchronous test case based on the sequence diagram.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 31, 2018
    Assignee: HCL TECHNOLOGIES LTD.
    Inventors: Simy Chacko, Satya Sai Prakash Kanakadandi, S U M Prasad Dhanyamraju
  • Patent number: 10037785
    Abstract: Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan chain operation on the scan vector.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 31, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Joshua E. Alzheimer, Debra M. Bell
  • Patent number: 9984387
    Abstract: Methods and apparatus for implementing forward looking optimizing promotions by administering, in large numbers and iteratively, test promotions formulated using highly granular test variables on purposefully segmented subpopulations. The responses from individuals in the subpopulations are received and analyzed. The analysis result is employed to subsequently formulate a general public promotion. The test promotions may be repeated continually and iteratively with different test promotions and/or different subpopulations to continue to uncover advantageous correlations between segmentation criteria, test promotion variables, and consumer response and/or to keep up with consumer changing taste.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: May 29, 2018
    Assignee: Eversight, Inc.
    Inventor: David Moran
  • Patent number: 9940639
    Abstract: Methods and apparatus for implementing forward looking optimizing promotions by administering, in large numbers and iteratively, test promotions formulated using highly granular test variables and automatically incorporating constraints on segmented subpopulations. The responses from individuals in the subpopulations are received and analyzed. The analysis result is employed to subsequently formulate a general public promotion.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 10, 2018
    Assignee: Eversight, Inc.
    Inventors: David Moran, Michael Montero
  • Patent number: 9940640
    Abstract: Methods and apparatus for implementing forward looking optimizing promotions by administering, in large numbers and iteratively, test promotions formulated using highly granular test variables on purposefully segmented subpopulations. The plurality of test promotions automatically account for covariates. The responses from individuals in the subpopulations are received and analyzed. The analysis result is employed to subsequently formulate general public promotion.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 10, 2018
    Assignee: Eversight, Inc.
    Inventors: David Moran, Michael Montero
  • Patent number: 9939463
    Abstract: A test circuit includes a pull-up device, a pull-down device, a switch circuit and a voltage-setting unit. The pull-up device is used to receive a first control signal and coupled to a first end of the device-under-test. The pull-down device is used to receive a second control signal and coupled to the first end of the device-under-test. The switch unit is controlled by a switch signal, used to receive a testing signal and coupled to a second end of the device-under-test. The voltage-setting unit is controlled by a third control signal, used to pull the second end of the device-under-test to a predetermined voltage.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 10, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Wei Tsou
  • Patent number: 9889270
    Abstract: A method of controlling relaxation equipment is a method of controlling relaxation equipment capable of changing a biological value of a user. The method includes: obtaining a user model including a transition in biological value within a period from a start time to an end time of a program being viewed by the user; obtaining a first biological value of the user viewing the program; and controlling the relaxation equipment such that the biological value of the user at the end time approximates a second biological value included in the user model, which is a value at the end time, based on the first biological value and the second biological value.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: February 13, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kentaro Nakai, Koichi Kusukame
  • Patent number: 9798629
    Abstract: Exemplary methods for predicting backup and restore failure include analyzing, at a management server, resource utilization statistics periodically collected during backup of data from a source storage system to a target storage system. In one embodiment, the methods include creating a predictive model based on the analysis of the collected resource utilization statistics. In one embodiment, the method includes predicting, using the predictive model, whether a backup time or a restore time of future backup will exceed a backup time threshold or restore time threshold, respectively.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: October 24, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Philip Shilane, Grant Wallace
  • Patent number: 9783138
    Abstract: In a vehicle control device in which a driver circuit which does not have a computing function and a computing device communicate with each other, there is provided a technology which can efficiently diagnose that both the driver circuit and the computing device normally communicate with each other by a simple technique. The vehicle control device according to the present invention transmits diagnosis data as a control command from a computing portion to the driver circuit, and the driver circuit sends inverted diagnosis data in which the diagnosis data is bit-inverted back to the computing portion. The computing portion diagnoses whether or not the communication between the computing portion and the driver circuit is normally performed, by using the diagnosis data and the inverted diagnosis data.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 10, 2017
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shinichiro Yoneoka, Yasuhiko Okada, Chihiro Sato, Koji Yuasa, Masahiro Toyohara, Yasushi Sugiyama
  • Patent number: 9772918
    Abstract: A method for connecting an input/output interface of a testing device equipped for testing a control unit to a model of a technical system present in the testing device. The interface connects the control unit to be tested or connects a technical system to be controlled; the model to be connected to the input/output interface is a model of the technical system to be controlled or a model of the control unit to be tested. The testing device has a plurality of input/output functions connected to the model and provides an interface hierarchy structure and a function hierarchy structure. The method has an automatic configuration of compatible connections between the interface hierarchy structure and the function hierarchy structure so that the model present in the testing device communicates through the compatible connections with the control unit to be tested or the technical system to be controlled.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: September 26, 2017
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Marc Tegethoff
  • Patent number: 9698799
    Abstract: A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: July 4, 2017
    Assignee: SHANGHAI EASTSOFT MICROELECTRONICS CO., LTD.
    Inventors: Ruijin Liu, Xu Zhang, Jingjing Tao, Jiejie Lv
  • Patent number: 9569204
    Abstract: Systems and methods of end-to-end continuous integration and verification of software are described. A system comprises, for example, a provisioning service module configure to automatically retrieve source code from a source code management system. The provisioning service module further generates one or more environments. A propagation management module is configured to package the retrieved source code into a deliverable and to automatically propagate the deliverable through a pipeline comprising the one or more environments.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 14, 2017
    Assignee: eBay Inc.
    Inventors: Steve Farris Mansour, Todd Paul
  • Patent number: 9483385
    Abstract: To provide a technique for generating, at a high speed, a smaller-sized set that satisfies an intended property such as, for example, being pair-wise, and includes many test cases that match a set of existing test cases given as an input, candidates to be used from a set of existing input test cases are determined in the following manner: for some parameters, values to be held by test case candidates are determined; test cases having the determined values, among those included in the set of input test cases, are selected as the candidates. A test case having the highest score among one or more test case candidates generated with the method of the related art and one or more test case candidates selected from the set of input test cases is added to a set of output test cases.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ken Mizuno, Taiga Nakamura, Hironori Takeuchi
  • Patent number: 9465896
    Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 11, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Paul A. Cunningham, Steev Wilcox, Vivek Chickermane
  • Patent number: 9465724
    Abstract: To provide a technique for generating, at a high speed, a smaller-sized set that satisfies an intended property such as, for example, being pair-wise, and includes many test cases that match a set of existing test cases given as an input, candidates to be used from a set of existing input test cases are determined in the following manner: for some parameters, values to be held by test case candidates are determined; test cases having the determined values, among those included in the set of input test cases, are selected as the candidates. A test case having the highest score among one or more test case candidates generated with the method of the related art and one or more test case candidates selected from the set of input test cases is added to a set of output test cases.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 11, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ken Mizuno, Taiga Nakamura, Hironori Takeuchi
  • Patent number: 9468124
    Abstract: An input/output module is commonly usable to a recorder and a data logger. The input/output module includes an input/output unit and a power unit. The input/output unit is configured to achieve at least one of a function of acquiring a measurement signal from a measurement target and a function of outputting data. The power unit is configured to supply an operation voltage to the input/output unit The power unit includes an insulated power device. The power unit is configured to use a voltage, which has been converted by the insulated power device from a power supply voltage, as an operation voltage when the input/output module is connected with a base of the data logger and the power unit receives a power voltage supply via the base. The power unit is configured to use a power supply voltage as the operation voltage, when the input/output module is connected with the recorder and the power unit receives the power voltage supply from the recorder.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: October 11, 2016
    Assignee: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Kouji Kitagawa, Yuusuke Fujitani
  • Patent number: 9459804
    Abstract: A method, system, and computer program product for replication comprising allowing a subset of sites, wherein the sites comprise a first site, a second site and a third site and further wherein each site has a volume, to have active/active VSL replication, which presents two volumes at two different sites as a single volume, and another set of the sites to have a volume which is a replications of the volume presented by the VSL, and enabling the system to transparently shift which subset of the sites are replicated by the VSL and which sites are replications of the volume presented by the VSL; where the replication of the VSL is performed by a second replication technique.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: October 4, 2016
    Assignee: EMC Corporation
    Inventors: Assaf Natanzon, Saar Cohen, Steven R Bromling
  • Patent number: 9448467
    Abstract: A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Chou, Te-Yu Liu, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Patent number: 9442821
    Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive a tool error output determined by a code inspection tool and select at least one defect classification mapping profile based on the code inspection tool. Additionally, the programming instructions are operable to map the tool error output to one or more output classifications using the selected at least one defect classification mapping profile and generate at least one report based on the one or more output classifications.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 13, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ian E. Baker, Kathryn A. Bassin, Steven Kagan, Susan E. Smith
  • Patent number: 9442784
    Abstract: A management device includes a node information storing unit which stores, for each of plural operation devices, an device state representing whether the operation device is in a working state or in a non-working state, the device state associated with an identifier of the operation device, a fault state acquiring unit which acquires a value representing whether or not a fault exists from each of the operation devices that are in the non-working state, and an instruction unit which sends, when a number of the operation devices is smaller than a predetermined value, a work instruction to the operation device from which the value representing that no fault exists is acquired and which is in the non-working state, among the plural operation devices which make a transition to the working state when receiving the work instruction while in the non-working state.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: September 13, 2016
    Assignee: NEC CORPORATION
    Inventor: Takamasa Ohtake
  • Patent number: 9436422
    Abstract: A system and method are provided for accurately emulating a printer on a computing device that is not connected to the printer. The computing device is provided with firmware and programming code that interfaces with the firmware for a customized printing operation. The firmware is provided with the printer and the computing device. The programming code is provided with the computing device, and the computing device runs the programming code. The programming code interfaces with the firmware provided with the computing device and causes the computing device to emulate the printer, when the printer runs the programming code. The computing device and the printer are not connected.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: September 6, 2016
    Assignee: SATO HOLDINGS KABUSHIKI KAISHA
    Inventors: Staffan Gribel, Peter Jonsson
  • Patent number: 9411014
    Abstract: A method for reordering a test pattern set for testing an integrated circuit is disclosed. A productivity index is computed for each test pattern in a test pattern set. The productivity index of a first test pattern and the productivity index of a second test pattern are compared. If the productivity index of the second test pattern is larger than the productivity index of the first test pattern, the location of the first test pattern and the second test pattern are swapped.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: August 9, 2016
    Assignee: Synopsys, Inc.
    Inventors: Sushovan Podder, Parthajit Bhattacharya, Rohit Kapur
  • Patent number: 9348719
    Abstract: An automated test system for a semiconductor device to concurrently perform multiple device tests is provided. The system may include at least one test client, at least one test site and a test server. The at least one test client is configured to receive a test request of at least one worker and to display a test response. The at least one test site is configured to test at least one device under test (DUT). The test server is configured to communicate with the at least one test client and the at least one test site, divide and/or drive the at least one test site in response to the test request of the at least one test client, and transmit a response of the at least one test site to the at least one test client.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deock-Kyum Kimm, Dae-Hwan Kim, Mi Jang
  • Patent number: 9270983
    Abstract: Methods, systems, and computer readable media can provide diagnosis of service-affecting issues in CPE devices. The diagnostic process can include retrieving a testing hierarchy associated with a received diagnostic command, executing the lowest-level diagnostic in the testing hierarchy, successively executing the remaining diagnostics in the testing hierarchy in the order implicated by the hierarchy until the commanded diagnostic is executed, and identifying the service-affecting issues found.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 23, 2016
    Assignee: ARRIS Enterprises, Inc.
    Inventor: William Charles Hare, Jr.
  • Patent number: 9262307
    Abstract: A method executable on one or more processors for modeling a test space is provided. The method may include defining a coverage model including a set of variables. The method may also include selecting one or more variables within at least one subset of a plurality of subsets of the set of variables. The selection may be according to an interaction level requirement defined for at least one or more of the subsets, whereby the interaction level corresponds to a coverage of the test space that covers a plurality of possible combinations of the one or more variables at multiple levels. Furthermore, respective values for the one or more selected variables within the subset of the set of variables may be assigned. The method may also include one or more definitions for value combinations for said variables with assigned values.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Itai Segall, Rachel Tzoref-Brill, Aviad Zlotnick
  • Patent number: 9176844
    Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive a tool error output determined by a code inspection tool and select at least one defect classification mapping profile based on the code inspection tool. Additionally, the programming instructions are operable to map the tool error output to one or more output classifications using the selected at least one defect classification mapping profile and generate at least one report based on the one or more output classifications.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: November 3, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ian E. Baker, Kathryn A. Bassin, Steven Kagan, Susan E. Smith
  • Patent number: 9104811
    Abstract: System, method, and non-transitory medium for generating a test scenario template based on a user profile, includes steps of identifying runs of test scenarios run by users belonging to different organizations on software systems of the different organizations; clustering the runs to clusters that include similar runs of test scenarios; receiving a profile of a user; selecting from the clusters a certain cluster that suits the profile; the certain cluster includes a first run of a first test scenario associated with a first organization, and a second run of a second test scenario associated with a second organization, in addition, the first run is not identical to the second run, and the first organization is not the second organization; removing from the first run proprietary data associated with the first organization; and generating a test scenario template based on the first and second runs.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 11, 2015
    Assignee: Panaya Ltd.
    Inventors: Yossi Cohen, Mati Cohen, Nurit Dor, Dror Weiss
  • Patent number: 9099951
    Abstract: A method for evaluating a gauge controller is disclosed. The method includes counting a number of high pulses for a plurality of signal types until either each of the control signals present low signals. After the number of high signals are counted, an angular offset of a gauged needle is calculated.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: August 4, 2015
    Assignee: Yazaki North America, Inc.
    Inventor: Kevin D. Russo
  • Patent number: 9064201
    Abstract: A document for variable printing and print settings including a conditional print setting that depends on metadata included in the document are received, information that is common between the conditional print setting and metadata included in the document is replaced with unique information, and printing is instructed using the conditional print setting and the document in which the common information is replaced with the unique information.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: June 23, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yosuke Ito
  • Patent number: 8983790
    Abstract: Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: March 17, 2015
    Assignee: Xilinx, Inc.
    Inventors: Ushasri Merugu, Siva V. N. Hemasunder Tallury, Sudheer Kumar Koppolu
  • Publication number: 20150066416
    Abstract: A traction battery connection simulator is disclosed comprising a plurality of power supplies connected to simulate a traction battery and a plurality of switching devices that selectively connect the power supplies to a controller under test. The simulator further comprises a controller programmed to selectively connect at least one of power supplies to the controller under test for a predetermined period of time before connecting remaining power supplies. The controller may also be programmed to disconnect at least one power supplies from the controller under test for a predetermined period of time before disconnecting remaining power supplies. Voltages associated with each power supply and currents through each switching device may be compared to corresponding predetermined ranges. An indicator may be set in response to at least one of the voltages and currents being outside of a corresponding predetermined range.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Michael Edward Loftus, James Lawrence Swoish