Abstract: A method, apparatus and software is disclosed, for use in a computerised storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode.

Abstract: The present invention relates to a system and a method for creating hardware and/or software test sequences and in particular, to such a system and method in which modular building blocks are used to create, sequence and schedule a large scale testing sequence using a matrix like platform.

Abstract: There are provided a method and system for testing software for an industrial machine with continuous test values reflecting actual environmental factors, using a simulator before the software for the industrial machine is embedded into an actual industrial machine. A method for testing software for an industrial machine, the method comprising the steps of: coding a program for a diagram through which the industrial machine is driven; compiling the program into an instruction with which the industrial machine is driven; downloading the compiled program onto a simulator for implementing a programming interface provided by the industrial machine; executing the compiled program in the simulator: generating a first data for testing the compiled program: transmitting the first test data to the simulator having the downloaded program from a testing tool; and outputting a result data obtained after executing the program having the transmitted first test data and then transmitting the result data to the testing tool.

Abstract: Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.

Abstract: In a method for testing device descriptions for field devices of automation technology, a finite state machine is produced from a device description to serve as a basis for a test script. For testing the device description, the test script is executed, with data being sent to and received from the device description. In such case, it is tested whether desired values set in the test script agree with actual values delivered e.g. from the field device.

Abstract: Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs.

Abstract: A system for testing the output of a digital gauge controller is disclosed. The system is configured to receive a multi-component digital signal and test if a plurality of thresholds are reached for individual components of the digital signal. If a first expected level is met, the system then determines if a second component of the multi-component signal meets a second expected level.

Abstract: An integrated circuit with a single-channel input/output (I/O) interface and a multi-channel I/O interface includes functional circuits that operate in different clock domains and a test circuit. For a single-channel I/O interface, the test circuit simulates read/write operations by bypassing the functional circuits and performs electrical characterization of the single-channel I/O interface. For a multi-channel I/O interface, the test circuit configures a plurality of channels of the multi-channel interface in a half-duplex mode and performs electrical characterization using data loop back by bypassing the functional circuits.

Abstract: Various exemplary embodiments relate to an integrated circuit device that includes a plurality of input/output pins, device circuitry, a first testing protocol interface connected to the device circuitry and to the plurality of input/output pins, and a second testing protocol interface connected to the device circuitry and to the same plurality of input/output pins as the first testing protocol interface. The first testing protocol interface is configured to test the device circuitry with a first testing protocol, and the second testing protocol interface is configured to test the device circuitry with a second testing protocol.

Abstract: A system for testing electronic circuits includes first, second, and third standard interfaces. A test port master and a test port slave are connected to an external testing apparatus. The first, second, and third standard interfaces are tested in first, second, and third test modes, respectively. The tests are initiated by asserting a test mode activate and first, second, and third test mode enable signals, respectively, which enable reuse of test patterns across different electronic circuits.

Abstract: A circuit board testing system and a circuit board testing system for testing a circuit board of keys. The circuit board testing system includes a computer and a test frame. The circuit board is placed on the test frame. The computer includes a script database with plural pin test scripts, a script generation program and a test program. The test program is used for searching a pin test script corresponding to the circuit board from the script database, and testing the circuit board according to the pin test script. If the pin test script is not searched from the script database by the test program, the script generation program is activated to create the pin test script.

Abstract: Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.

Abstract: A differential SR flip-flop 100 receives a set signal S and a reset signal R, and generates a differential output pair Q and #Q. A first flip-flop FF1 generates a non-inverted output signal Q1 and an inverted output signal #Q1. A second flip-flop FF2 generates a non-inverted output signal Q2 and an inverted output signal #Q2. An averaging circuit 10 averages one output signal (Q1) of the first flip-flop FF1 and one output signal (Q2) of the second flip-flop FF2 so as to generate a first output signal Q3, and averages the other output signal (#Q1) of the first flip-flop FF1 and the other output signal (#Q2) of the second flip-flop FF2 so as to generate a second output signal #Q3. As a differential output pair, the differential SR flip-flop 100 outputs a signal that corresponds to the first output signal Q3 and a signal that corresponds to the second output signal #Q3.

Abstract: A measuring system executable by a computer for measuring a PCB is provided. A layout information obtaining module obtains layout information of the PCB. A parameter setting interface display module display a parameter setting interface on a display screen. A measuring parameter setting module determines customized parameters in response to an operator's operation on a parameter setting button provided by the parameter setting interface. A measurement analyzing module obtains the customized parameters and measures the widths of the selected traces, determines whether the measured widths matches with the width parameters. A measuring result obtaining module obtains a measuring result provided by the measurement analyzing module, and identifying the traces of which the measured widths do not match with the width parameters associated therewith. A related method is also provided.

Abstract: A method for emulating and debugging a microcontroller is described. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed.

Abstract: A semiconductor device comprises a burn-in test circuit configured to receive a flag signal for a burn-in test, generate a toggled output enable signal, and drive a first input/output line to toggle a signal on the first input/output line, and a switching device connected between a bit line and a second input/output line for transferring a signal on the bit line to the second input/output line in response to the output enable signal.

Abstract: An electronic device tester is connected to an electronic device needed to be tested. A test program is stored in a data storage of the tester. The test program includes a number of test instructions. The tester encapsulates the test instructions of the test program to a number of script files, stores the script files to the data storage, and records a name of each script file to the test program. After the test instruction is encapsulated, the tester selects desired script files of the test program and calls the selected script files according to the names of the script files to implement the test program to test the electronic device.

Abstract: An integrated circuit (IC) including a warranty and enforcement system, and a related design structure and HDL design structure are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded.

Abstract: A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.

Abstract: A single ended to a differential signal converter. The single ended signal is passed through a high pass filter to block DC components. A positive and a negative version of the filtered signal are used collectively as the differential output of the converter. To allow accurate measurements on the input signal without waiting for the output of the high pass filter to settle, the differential outputs are offset by a dynamically generated signal representative of the midpoint of the filtered signal. That offset is generated by capturing a value representing the midpoint when a signal is first applied. This captured value is allowed to change with a time constant matching a time constant of the high pass filter. The converter may be used to connect a test instrument to a unit under test that generates test signals in a format that the test instrument is not specifically configured to measure.

Abstract: An appliance development toolkit includes an editor configured to create one or more test scripts having steps with each step being separated from its adjacent steps by a transition condition. The transition condition includes a logic expression resolvable to a boolean transition value, and one or more command statements that instruct what should happen so that a test engine can execute the command statement contemporaneous with the transition from one step to another. The toolkit also includes information associated with a message element in a message data payload. The message data payload is uniquely identifiable within a universe of pre-defined message data payloads for an appliance. The toolkit also includes a converter for placing the test script into a form for use in diagnosing an appliance.

Abstract: The digital integrated circuit testing and characterization system and method provides high-speed testing for digital IC prototypes. A stand-alone circuit, such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), implements a test and characterization processor (TACP). Supporting test circuitry is fabricated on board a prototyping chip to facilitate the test and characterization process. Test procedures and data may be downloaded to the TACP memory through a computer via a standard interface. The TACP administers the user-specified test procedures to one of several possible circuits on the prototyping chip. Test results are stored and collected via the on-board support test circuitry in communication with the TACP.

Abstract: Configuring at least one radio frequency (RF) instrument according to a plurality of RF measurement configurations for performing a plurality of tests on a device under test (DUT). A list of RF measurement configurations may be stored in a computer memory. The list of RF measurement configurations comprises a plurality of parameters for configuring operation of the at least one instrument. Information regarding the list of RF measurement configurations (e.g., a data stream) may be provided to the at least one RF instrument. The at least one RF instrument may perform the plurality of tests on the DUT, including the at least one RF instrument configuring itself according to the RF measurement configurations based on processing of the information. Configuring enables the at least one RF instrument to perform the plurality of tests on the DUT in a deterministic manner.

Abstract: A heterogeneous multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. A debug control circuit is connected between the first and second TAP controllers and the first and second debug ports. Based on external configuration signals, the debug control circuit configures the connections between the first and second TAP controllers and the first and second debug ports according to predetermined configuration modes, which allows flexibility in debugging the heterogeneous multi-core integrated circuit.

Abstract: There is disclosed a system and method for network test conflict checking. The method may be performed by a network testing system and may be implemented as software. The method may include receiving user selected test features and user selected hardware for a network test. When receiving user selected features, incompatible features are made unselectable by reference to a feature database. A compatibility check is performed by referring to a hardware database and a feature database. Suggestive corrective changes may be provided to a user or automatically made to the selected features and/or selected hardware. The network test is written to hardware when the compatibility test is successful.

Abstract: A tester for testing a device under test has a first channel unit and a second channel unit. The first channel unit has a corresponding first pin connection for a signal from a device under test, a corresponding first test processor adapted to process, at least partially, data obtained from the first pin connection, and a corresponding first memory coupled with the first test processor and adapted to store data provided by the first test processor. The first channel unit is adapted to transfer at least a part of the data obtained from the first pin connection to the second channel unit as transfer data. The second channel unit has a corresponding second test processor adapted to process, at least partly, the transfer data from the first channel unit.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment.

Abstract: A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

Abstract: A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port.

Abstract: A keyboard test program generating method includes the following steps. Firstly, a first key number is received. By pressing a first key, a first key identification code corresponding to the first key is generated. The first key number is assigned to the first key so as to generate a first key conditional expression. By pressing a next key, a next key identification code corresponding to the next key is generated. A second key number following the first key number is assigned to the next key so as to generate a next key conditional expression. Afterwards, these key conditional expressions, a keyboard test program header and a keyboard test program trailer are combined together, thereby generating the keyboard test program.

Abstract: The present invention certifies control modules of engineered safety feature instruments for a power plant automatically. The control modules can be tested before storing or operating. The test is done with enhanced testing speed and saved cost. Thus, safety of the control modules is confirmed.

Abstract: A test apparatus includes: test modules that communicate with the device under test to test the device under test; additional modules connected between the device under test and the test modules, each additional module performing a communication with the device under test, the communication being at least one of a communication performed at a higher speed and a communication performed with a lower latency, in comparison with a communication performed by the test modules; a test head having a plurality of connectors that connect the test modules and the additional modules, respectively, the test modules and the additional modules are mounted on the test head; a performance board placed on the test head that connects between at least a part of terminals of the plurality of connectors and the device under test. The test modules are connected to the additional modules without through the performance board.

Abstract: A storage device, a board, a liquid container, a system and the like are disclosed, which are capable of efficiently detecting a connection to a host device without an increase in the number of existing terminals. A storage device 100 includes: a storage section 130; a storage controller 120 that controls access to the storage section 130; a controller 110 that performs a communication process with the host device; a data terminal SDA; a reset terminal XRST; and a clock terminal SCK. The controller 110 determines that an operational mode is a normal communication/connection detection mode when a voltage level change of the reset terminal XRST indicates a change in a reset/reset-disabled state during a time period for the clock terminal SCK has specific voltage level(s).

Abstract: According to some embodiments, characterization data can be loaded onto a programmable device. The characterization data can be configured to cause the programmable device to perform one or more functions if executed on the programmable device. It can then be determined whether or not loading the characterization data onto the programmable device caused the programmable device to be successfully programmed. An indication can be transmitted for receipt by an external device, the indication indicating whether or not the programmable device was successfully programmed.

Abstract: A semiconductor device 100 including an internal circuit 4 that operates based on an input pattern includes a clock driver 25 that generates an internal clock 7 based on a generated clock 6, a counter 23 that generates count data 28 by counting the generated clock 6, a nonvolatile storage device 22 that stores storage data 27 used in an IDDQ test, a comparator 24 that stops the generation of the internal clock 7 by the clock driver 25 when the count data 28 and the storage data 27 match each other, and a pseudo random number generation circuit 3 that supplies a pseudo random number 8 to the internal circuit 4 in synchronization with the internal clock 7.

Abstract: In one embodiment, the invention is a method and apparatus for selecting paths for use in at-speed testing. One embodiment of a method for selecting a set of n paths with which to test an integrated circuit chip includes: organizing the set of n paths into a plurality of sub-sets, receiving a new candidate path, and adding the new candidate path to one of the sub-sets when the new candidate path improves the process coverage metric of the sub-sets.

Abstract: A network analyzer contains a processing device, at least one signal generator and at least four measuring points. The processing device controls the signal generator and processes measured values picked up from the measuring points. The network analyzer implements several calibration measurements on calibration standards, before it implements measurements on a device under test. The network analyzer implements the calibration measurements using the measuring points. The processing device determines error matrices on the basis of the results of the calibration measurements. The network analyzer implements measurements on the device using simultaneously, exactly three measuring points. The processing device determines measured values in each case of a fourth measuring point on the basis of the calibration measurements and the measured values of the three measuring points.

Abstract: An apparatus for multiplying a semiconductor test pattern signal, which firstly encodes a plurality of pattern signals to have different pattern types, and multiplies the encoded pattern signals according to an exclusive-OR (XOR) scheme in order to generate a single pattern signal, thereby recognizing a relationship between a pattern signal before the multiplication and the other pattern signal after the multiplication. A pattern-signal segmenting/outputting unit segments a semiconductor test pattern signal into a plurality of pattern signals, and simultaneously outputs the segmented pattern signals.

Abstract: In a system in which a plurality of modules have different operational rates and a common clock controlling data delivery to the modules, the rate at which data is delivered to the system can be maximized using a return clock signal to prevent the loss of synchronization of the modules. A clocking error signal may be produced when the clock signal makes a transition to a logic state that may cause loss of synchronization between the modules.

Abstract: A method of testing an integrated circuit (IC) having a plurality of dies can include receiving, within a master die of the plurality of dies of the IC, a configuration data set specifying a circuit design, wherein the circuit design is instantiated within the master die. The method can include broadcasting the configuration data set to at least one slave die, wherein the circuit design is instantiated within each slave die and receiving, within the master die, a test vector set. The method also can include broadcasting the test vector set to the at least one slave die and responsive to each die executing the test vector set, storing test output data generated by each die.

Abstract: A test pattern is sequentially selected from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit. Power consumption in each of regions obtained by substantially equally dividing a layout region of a semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit is estimated. A searching is conducted for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions. A new test pattern sequence constituted by a plurality of test patterns including no don't care bit is generated by defining the don't care value obtained by the searching as a don't care value of the selected test pattern.

Abstract: System and method for configuring a client system, e.g., a measurement system. First input is received from a client system over a network requesting access to a plurality of configuration diagrams comprising respective solutions to respective tasks. At least a subset of the plurality of configuration diagrams is displayed on a display device of the client system for viewing by a user. Second input is received from the client system selecting one of the displayed configuration diagrams indicating a solution for a task to be performed by the client system. The solution is provided to the client system over the network, and may include the selected configuration diagram and/or pricing information for proposed products. The configuration diagrams are stored in a configuration diagram database. The stored configuration diagrams may be pre-defined solutions for pre-defined tasks, generated in response to received user requirements, and/or received from client systems and/or vendors.

Abstract: A platform specific test for computing hardware and method using same, wherein the method supplies a plurality of test procedures, and provides a computing device to be evaluated, where the computing device comprises (M) physical objects. The method identifies, for each value of (i), an (i)th physical object disposed in the computing device. The method then determines, for each value of (i), if the plurality of test procedures comprises one or more test procedures associated with the (i)th physical object. If, for each value of (i), the plurality of test procedures comprises one or more (i)th test procedures associated with the (i)th physical object, then the method adds, as one or more (i)th test procedures, the one or more test procedures associated with the (i)th physical object to a test algorithm, and saves that test algorithm.

Abstract: Disclosed is an integrated circuit chip incorporating a test circuit having multiple logic blocks. Each logic block is a matrix of individually selectable, physically different, test devices in a specific class of devices. An embedded processor ensures that specific stress conditions are selectively applied to the test devices and further controls selective testing, by a sensor system, of the test devices to determine the impact of the applied stress conditions. In a laboratory or test system environment, accelerated stress conditions are selectively applied to the test devices and the testing results are used to model device performance degradation due to class-specific failure mechanisms. In the field, stress conditions are selectively applied to test devices so as to mimic stress conditions impacting active devices in use on the same chip and the testing results are used to indirectly monitor performance degradation of the active devices due to class-specific failure mechanisms.

Abstract: A method for creating workload model to test performance of a critical application in a data processing network (112) is disclosed. The method includes receiving (202), at one of the plurality of data processing units (114a), an activity log with a plurality of entities from the data processing network (112). The method further includes creating (204) a transaction log of all transactions conducted using the activity log. Further the method determines (206) a plurality of transaction metrics using the transaction log, wherein the plurality of transaction metrics comprises an average transaction response time, a transaction throughput etc. The method further creates a workload model to test the critical performance of an application in the data processing network (112) based on the plurality of transaction metrics and provide effective performance test strategies.

Abstract: A data driven test system for web service or other service dependent on message exchange between service points or other communicating entities is contemplated. The testing system may be configured as a multi-stage tester having capabilities to conduct sequence, structure, and content test in order to narrowly identify errors of service points while subjected to a test protocol.

Abstract: A semiconductor test system with self-inspection of an electrical channel is disclosed, which includes a tester head, a plurality of parameter detection units and a self-inspection controller. The tester head includes a plurality of pin electronics cards inserted therein, in which the plurality of pin electronics cards contain a plurality of power channels, a plurality of I/O channels and a plurality of drive channels. The self-inspection controller outputs different inspection signals respectively to each power channel, each I/O channel and each drive channel. Then, the plurality of parameter detection units detect response signals respectively produced by each power channel, each I/O channel and each drive channel in response to the inspection signals respectively received thereby, and the response signals are judged by the self-inspection controller.

Abstract: Provided is a test apparatus that tests a device under test, comprising: a plurality of modules that each include an output circuit that outputs a prescribed output signal to the device under test and a measurement circuit that measures a prescribed characteristic of the device under test; and a control section that, for each module, causes the measurement circuit to measure output of the output circuit and diagnoses the module based on a measurement result of the measurement circuit. Each measurement circuit measures the output of the corresponding output circuit in parallel, and the control section is provided in common to the plurality of modules and sequentially reads the measurement result of the measurement circuit of each module.

Abstract: In an example embodiment, the system obtains the mutual inductance (e.g., Mij) between a quiet I/O buffer and each switching I/O buffer on a PLD from an automatic SSN measurement system. The system calculates the corrected mutual inductance between the quiet I/O buffer and each switching I/O buffer by multiplying the mutual inductance by a correction factor (e.g., ?j). The system multiplies each corrected mutual inductance by the rate of current flowing through the switching I/O buffer to obtain an induced voltage resulting from the switching I/O buffer. The system sums the induced voltages for all the switching I/O buffers on the PLD to obtain an estimate of total induced voltage caused in the quiet I/O buffer by all switching I/O buffers. The correction factor is based on bench measurements and depends on the amplitude of the simultaneous switching noise affecting each switching I/O buffer.

Abstract: An apparatus and method for flexible visibility in an integrated circuit are disclosed. As one example, an apparatus for flexible visibility in an integrated circuit is disclosed. The apparatus includes a switch unit disposed in the integrated circuit, the switch unit configured to receive a plurality of signals associated with a plurality of visibility points in the integrated circuit, and output the received plurality of signals in a serial form. Also, the apparatus includes a formatter unit disposed in the integrated circuit and coupled to the switch unit, the formatter unit configured to receive the plurality of signals in the serial form, and output a plurality of formatted signals including the received plurality of signals.