Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.

Abstract: The systems and methods described herein allow for automatic identification experiments in a closed loop, where the old control strategy, already tuned and tested, is utilized. The strategy is modified to inject additional signal optimized for identification. The experimenting time may be reduced by performing only those system manipulations which explore model uncertainties important to potential degradation of controller performance by discrepancy between the system and the model. The disruptions are reduced by keeping the control loop closed, which eliminates waiting for steady state before applying steps to the inputs and reduces the risk of process limits crossing. The energy of additional signal can be set to meet the maximum allowable disruption requirements. The energy of additional signal is in a direct relation to the speed of identification related information gathering. It can be varied in time to follow the needs of system operators.

Abstract: A method and apparatus is disclosed that guides a user through a sequence of steps that will allow the user to complete a predefined task using the flow meter. The steps include: selecting a predefined task, displaying a sequence of steps that directs the user through a process for using the Coriolis flow meter to complete the predefined task, and operating the Coriolis flow meter in response to the sequence of steps to complete the predefined task.

Abstract: Various embodiments of a system and method for performing a measurement application are described herein. The system may include a host computer having a processor, and a measurement device having a programmable hardware element. The programmable hardware element may be configured to perform a loop to acquire measurement data from a physical system. The host computer may be configured to perform another loop to read the measurement data from the programmable hardware element and use the measurement data in a measurement and control algorithm. The host computer may be further configured to perform a synchronization algorithm to keep the measurement data acquisition loop performed by the programmable hardware element synchronized with the measurement and control loop performed by the host computer.

Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

Abstract: A semiconductor memory device having a test mode circuit is presented which includes: a mode setting unit, in response to an external command and a first address signal for a mode set, providing a mode register set signal corresponding to predetermined mode setting; and a test mode circuit, in response to the mode register set signal and a second address signal for test enable control in an initial operation, performing test mode enable; the test mode circuit, in response to the mode register set signal and a third address signal for test item selection in the test mode enable state, outputting a test mode item signal; and the test mode circuit, in a subsequent operation, receiving the fed-back test mode item signal to maintain the test mode enable state.

Abstract: According to exemplary methods and systems of the present principles, the location of defective field repairable units (FRUS) of a circuit that have varying sizes or varying numbers of scan cells may be identified by employing tiles including scan cells from different FRUS. A set of test patterns may be scanned through the scan cells such that cells belonging to FRUs within a tile may be concealed while analyzing the response of scan cells in the tile contributed by a different FRU. Further, defective tiles are discoverable at any tile location and in any quantity within a maximal capacity using a compressed signature. In addition, signature registers that process data at a rate that is faster than the scan shift rate of the circuit may be employed during compression to multiply a circuit response by a plurality of components of a compression matrix during one scan shift cycle.

Abstract: Test circuits and methods for detecting faults in integrated devices are disclosed. In an embodiment, a circuit may include an input node configured to receive a test signal, and a transition circuit configured to generate a transit on at least one voltage level indicator pin dependent on the test signal. The circuit may also include a data capture circuit configured to capture the output of the at least one voltage level indicator pin to test for stuck-at faults. In another embodiment, a method may include receiving a test signal, generating a transit on at least one voltage level indicator pin dependent on the test signal, and capturing the output of the at least one voltage level indicator pin to test for stuck-at faults.

Abstract: Disclosed are embodiments of a system and method for automatically selecting and generating test patterns for an at-speed structural test of an integrated circuit device. Specifically, a test pattern generation pass is started and proceeds until the “knee” of the simulated test coverage curve is observed. Next, the test patterns are optionally reordered and some are removed. Then, another test pattern generation pass is started. The process is repeated iteratively until some predetermined final stopping criterion is met. By performing multiple test pattern generation passes and reducing the number of available test patterns that can be generated with each pass, the method exploits the initial increase in the test coverage curve inherent in each pass and limits the overall test pattern count.

Abstract: A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.

Abstract: In a method of testing an object, a first test pattern for testing a first device in the object may be set in a tester. A second test pattern for testing a second device in the object may be set in a test head electrically connected between the tester and the object. The first test pattern may be provided to the first device through the test head and the second test pattern may be provided to the second device by the test head to simultaneously test the first device and the second device. Thus, the first device and the second device different from each other may be simultaneously tested without changing test conditions in the tester, so that a time for testing the object may be reduced.

Abstract: A driving circuit of a test access port is disclosed. The driving circuit includes an input terminal for receiving a first test data signal when the driving circuit is operating in an external test mode. The driving circuit is configured to receive a second test data signal (BS) carrying a test command to be executed on the test access port when the driving circuit is operating in an internal test mode. The driving circuit comprises a control logic circuit configured for processing the test command and generating therefrom an internal test data signal carrying the processed test command when the driving circuit is operating in the internal test mode. The driving circuit includes a selector configured for generating a selected test data signal, the selected test data signal being selected from the first test data signal when the driving circuit is operating in the external test mode.

Abstract: A low pin interface module is provided for testing an integrated circuit. The interface module includes an input-output module, a controlling module, a processing module and a storage module specific to the integrated circuit to be tested. The interface module reduces the required number of hardware pins in the integrated circuit for a standalone testing without limiting the integrated circuit testing features. A methodology and a control mechanism achieved with the interface module can be used for the standalone testing of any integrated circuit without using a Joint European Test Action Group test logic interface JTAG implemented following the IEEE Standard 1149.1-1990. The interface module is not limited by a particular debugging platform and allows access to all test features in the integrated circuit with a reduced number of hardware pins and thereby leading to enhanced testing speeds on a tester in parallel and a shorter time-to-a market cycle and a lower development cost.

Abstract: Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a predicting section that calculates a predicted value for each test vector by simulating an operation of the device under test, the predicted value indicating a prescribed characteristic value of the device under test to be measured while the device under test is supplied with a test signal corresponding to the test vector; a measuring section that obtains a measured value for each test vector by measuring the prescribed characteristic value of the device under test each time the device under test is supplied with a test vector; and a judging section that judges whether the device under test is defective based on a ratio between the predicted value and the measured value corresponding to each test vector.

Abstract: The testing method of the present invention for testing a plurality of devices under test connected to a test module includes (a) determining combinations of devices under test that can theoretically be measured simultaneously from among the combinations of the plurality of devices under test based on at least the connection relationship between the test module and the plurality of devices under test. The testing method further includes (b) testing the plurality of devices under test by sequentially selecting the combinations of devices under test to be actually measured simultaneously from the combinations determined in (a).

Abstract: In one of many possible embodiments, an exemplary system includes a test management subsystem configured to provide a user portal to a user of a circuit provided by a service provider, the user portal including a tool enabling the user to select a signal loop for testing at least a section of the circuit, the signal loop being selected from a plurality of signal loop options. The system also includes a network management subsystem communicatively coupled to the test management subsystem, the network management subsystem being configured to receive data representative of the selection from the test management subsystem and instruct, based on the selection, a network device along the circuit to execute a loop-back mode. In certain embodiments, the selected signal loop defines a test pattern signal flow for testing a subsection of the circuit.

Abstract: A chip testing circuit is disclosed. The chip testing circuit uses a judging circuit to switch the connection of the data compressing circuit between data compressing base units which compresses 4 XIOs, so as to obtain testing data by one single interface circuit and to increase the testing throughput.

Abstract: A system and method for antenna analysis and electromagnetic compatibility testing in a wireless device utilizes a “parent” device that undergoes rigorous conventional testing. A “child” device having similar components may thereafter undergo abbreviated testing. Because the Total Isotropic Sensitivity of the parent device is known, testing may be performed on the child device to infer equivalence to the parent's TIS performance using the abbreviated test techniques.

Abstract: An electric device includes a plurality of circuits that operate in synchronization with a clock signal, a plurality of flip-flops each of which acquires a data value of a signal from a corresponding one of the plurality of circuits in synchronization with the clock signal and stores the acquired data value therein until receiving a next clock signal, where each flip-flop enters into a clock-disabled state, when receiving a signal at a disable terminal thereof, in which the acquired data value continues to be stored in the flip-flop, a timing controller that outputs a hold signal to the disable terminal of each flip-flop at a timing at which a corresponding circuit is desired to be diagnosed, and a plurality of diagnosis lines that are respectively provided in correspondence with the plurality of flip-flops, each diagnosis line outputting as diagnosis data a data value stored in a corresponding flip-flop.

Abstract: A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.

Abstract: An electronic device tester is connected to an electronic device needed to be tested. A test program is stored in a data storage of the tester. The test program comprises a number of test instructions. The tester encapsulates the test instructions of the test program to a number of script files, stores the script files to the data storage, and records a name of each script file to the test program. After the test instruction is encapsulated, the tester selects desired script files of the test program and calls the selected script files according to the names of the script files to implement the test program to test the electronic device.

Abstract: A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: To increase the overall efficiency of a test apparatus, provided is a test module that includes an instruction information storage section that stores instruction information indicating an order in which basic patterns are expanded; a basic pattern data storage section that stores basic pattern data; a plurality of pattern generating sections that each include a temporary instruction information storage section, which temporarily stores a portion of the instruction information, and that each generate a test pattern supplied to a device under test by expanding the basic pattern data in the order indicated by the instruction information stored in the corresponding temporary instruction information storage section; and a plurality of position information storage sections that independently store position information indicating reading positions of the instruction information stored in the instruction information storage section that is common to the plurality of pattern generating sections, in association with e

Abstract: A system including an integrated circuit configured to transfer a mission mode signal between a mission mode circuit on the integrated circuit and a first input/output pin on the integrated circuit in mission mode and to transfer a development mode signal between a development mode circuit on the integrated circuit and the first input/output pin in debug mode. The integrated circuit is configured to transfer the mission mode signal between the mission mode circuit and a second input/output pin on the integrated circuit in debug mode.

Abstract: The present invention relates to a negative pulse transient signal analysis methods and negative pulse transient signal analysis module for a PC base simulation equivalent circuit capable of grasping and improving error causes through an abnormal signal analysis after configuring a simulation equivalent circuit for a 4˜20 mA instrument unsatisfied in a temperature environmental impact assessment.

Abstract: An apparatus for testing connections in a system has a plurality of inputs each adapted to couple to a test point in the system under test and a switching module. The switching module includes a first output selectively coupled to receive a first group of one or more of the inputs and a set of outputs corresponding in number to the plurality of inputs, each being selectively coupled to receive a corresponding one of the plurality of inputs. The apparatus may also include a meter coupled to the first switching module output and an array of nodes coupled to the set of switching module outputs, where each node couples a signal to a row sense line and a column sense line.

Abstract: A transceiver includes a receiver unit including a clock and data recovery unit. The transceiver includes a transmitter unit and a digital core coupled to the receiver unit and the transmitter unit. A switch circuit is positioned after the clock and data recovery unit, and is configured to route data from the receiver unit to the transmitter unit in a test mode of the transceiver.

Abstract: The disclosed device performs a control of generating a test pattern for the delay test of LSI. The input pattern control circuit counts a cycle number of an input pattern supplied to a test object circuit, and stops supply of the input pattern to the test object circuit when the cycle number of the input pattern coincides with a certain count number. The scan control circuit receives a control signal from the input pattern control circuit, and supplies a scan shift signal to the test object circuit to shift a scan chain in the test object circuit.

Abstract: A circuit arrangement includes a controller and an integrated driver arrangement coupled to the controller. The integrated driver circuit includes a driver unit having at least one operation parameter, and a diagnostic unit coupled to the driver unit. The diagnostic unit is adapted to retrieve the at least one operation parameter from the driver unit, and is coupled to the controller.

Abstract: A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.

Abstract: Provided is a test apparatus 10, which includes: a plurality of test modules 150, each of which is connected to any of the plurality of devices under test 100 to supply a test signal to the connected device under test 100; a plurality of site controllers 130 that control the plurality of test modules 150 to test the respective plurality of devices under test 100 simultaneously; a connection setting device 140 that sets a connection mode between the plurality of site controllers 130 and the plurality of test modules 150 so that each of the test modules 150 is connected to any of the plurality of site controllers 130; and a plurality of system controllers 110, each of which controls any of the plurality of site controllers 130, in which a predetermined system controller of the plurality of system controllers 110 assigns, in response to a request from another system controller of the system controllers, a site controller of the site controllers, which is to be controlled by the another system controller.

Abstract: A test apparatus for testing a device under test includes a control apparatus, a plurality of test modules, and a plurality of relay apparatuses that connect the control apparatus and the plurality of test modules, each relay apparatus including (1) an upper port section connected either to the control apparatus or to a relay apparatus nearer the control apparatus; and (2) at least one lower port section connected either to a relay apparatus nearer the plurality of test modules or to a corresponding test module, where each relay apparatus receives, at one of the at least one lower port section, a packet transmitted from the corresponding test module to the control apparatus, and transmits, from the upper port section, the received packet after adding thereto port identification information of the one of the at least one lower port section.

Abstract: Provided is a test apparatus that tests a device under test, including a pattern list storage section that stores a plurality of pattern lists that each designate, in a prescribed order, the test patterns to be output by the device under test, and a pattern list processing section that (i) sequentially outputs the test patterns by sequentially executing the pattern lists according to test results of the device under test and, (ii) when transitioning from a current pattern list to a subsequent pattern list, repeatedly outputs a prescribed idle pattern until execution of the subsequent pattern list is begun.

Abstract: A wireless electronic device may serve as a device under test in a test system. The test system may include an array of over-the-air antennas that can be used in performing over-the-air wireless tests on the device under test (DUT). A channel model may be used in modeling a multiple-input-multiple-output (MIMO) channel between a multi-antenna wireless base station and a multi-antenna DUT. The test system may be configured to perform over-the-air tests that emulate the channel model. A design and analysis tool may be used to identify an optimum over-the-air test system setup. The tool may be used in converting a geometric model to a stochastic model for performing conducted tests. The tool may be used in converting a stochastic model to a geometric model and then further convert the geometric model to an over-the-air emulated stochastic model. The over-the-air emulated stochastic model may be used in performing conducted tests.

Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.

Abstract: Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path.

Abstract: A burn-in test apparatus and a semiconductor device using the same are disclosed. The burn-in test apparatus includes a flag signal generating unit configured to receive an external input signal and an external address externally inputted for a burn-in test and generate a flag signal, and a burn-in test unit configured to receive the flag signal, generate a toggled output enable signal, and drive an input/output line to toggle a signal on the input/output line.

Abstract: A keyboard test program generating method includes the following steps. Firstly, a first key number is received. By pressing a first key, a first key identification code corresponding to the first key is generated. The first key number is assigned to the first key so as to generate a first key conditional expression. By pressing a next key, a next key identification code corresponding to the next key is generated. A second key number following the first key number is assigned to the next key so as to generate a next key conditional expression. Afterwards, these key conditional expressions, a keyboard test program header and a keyboard test program trailer are combined together, thereby generating the keyboard test program.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module.

Abstract: In a method of testing a semiconductor wafer, semiconductor chips of a predetermined number are selected from among a plurality of semiconductor chips formed on a semiconductor wafer, and a first test is performed on I/O pins of each of the selected semiconductor chips. Then, a second test is performed on a part of the I/O pins of each of non-selected semiconductor chips as ones of the plurality of semiconductor chips other than the selected semiconductor chips.

Abstract: A device with a plurality of elements separated into groups, each element including an activation terminal, an input terminal and an output terminal, a plurality of first signal lines, and a plurality of second signal lines, where the input terminals of each element in each group are commonly connected to one of the plurality of first signal lines, the input terminals of the different groups are connected to different first signal lines, and the output terminals of the each element in each group are independently connected to a different one of the plurality of second signal lines.

Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Abstract: A method for generating reliability tests for a telephone system is based upon sampling an orthogonal array which covers various combinations of test parameters. Field data is collected of actual telephone activity on a telephone system. The field data is evaluated so as to determine call-mix characteristics. Probabilistic weights for the different call-mix characteristics are obtained, and then the probabilistic weights are used to sample the test case scenarios generated in the orthogonal array which have the same call-mix characteristics. These test case scenarios are used to run tests on the telephone system. These tests are preferably performed using automated test scripts. After the test data is collected, reliability metrics are calculated from the test data.

Abstract: There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.

Abstract: A semiconductor device includes a plurality of chips comprising a plurality of I/O terminals connected in common via through electrodes. Each of the chips includes an I/O compression circuit operable to output a compression result obtained by compression of data of a plurality of internal data buses to a first I/O terminal of the plurality of I/O terminals. Each of the chips also includes a test control circuit having a register group that sets the number of the first I/O terminal. Setting information that assigns different first I/O terminals to different chips is set in the register group. Each of the chips inputs or outputs data with use of the number of the I/O terminal that is different from those in other chips. Thus, the I/O compression circuits can concurrently perform an I/O compression test in parallel in the plurality of chips without a bus fight.

Abstract: Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE includes a signal formatter with an SR latch having set an reset inputs each connected through or coupled to a number of signal channels. Each signal channel may receive a long pulse from a timing generator and generate a short pulse. Each signal channel has a current steering circuit that couples the short pulses to the set or reset ports of the latch. Because the outputs of each current steering circuit have a high impedance when not sending a pulse, multiplexing circuitry and/or circuitry to logically OR the outputs of separate signal channels are unnecessary. The hardware eliminated by this design simplifies and improves the ATE. Additionally, the latch can be set and reset in quick succession with good timing resolution.

Abstract: Whether interruption is present in the connections of automatic door constituting units is detected. A plurality of automatic door constituting units (4, 8, 10, 12, 20, 24 and 26) are interconnected in such a manner that they can communicate with each other via a bus (2). The automatic door constituting units include a door controller (4) for controlling opening and closing of a door. The door controller (4) successively calls the other automatic door constituting units one by one via the bus (2), and the other automatic door constituting units send a response to the calling via the bus (2). The door controller (4) judges that the automatic door constituting unit the door controller (4) called is disconnected from the bus (2), when said called automatic door constituting unit does not send a response within a predetermined time after the calling.