Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.

Abstract: To provide a technique for generating, at a high speed, a smaller-sized set that satisfies an intended property such as, for example, being pair-wise, and includes many test cases that match a set of existing test cases given as an input, candidates to be used from a set of existing input test cases are determined in the following manner: for some parameters, values to be held by test case candidates are determined; test cases having the determined values, among those included in the set of input test cases, are selected as the candidates. A test case having the highest score among one or more test case candidates generated with the method of the related art and one or more test case candidates selected from the set of input test cases is added to a set of output test cases.

Abstract: An input/output module is commonly usable to a recorder and a data logger. The input/output module includes an input/output unit and a power unit. The input/output unit is configured to achieve at least one of a function of acquiring a measurement signal from a measurement target and a function of outputting data. The power unit is configured to supply an operation voltage to the input/output unit The power unit includes an insulated power device. The power unit is configured to use a voltage, which has been converted by the insulated power device from a power supply voltage, as an operation voltage when the input/output module is connected with a base of the data logger and the power unit receives a power voltage supply via the base. The power unit is configured to use a power supply voltage as the operation voltage, when the input/output module is connected with the recorder and the power unit receives the power voltage supply from the recorder.

Abstract: A method, system, and computer program product for replication comprising allowing a subset of sites, wherein the sites comprise a first site, a second site and a third site and further wherein each site has a volume, to have active/active VSL replication, which presents two volumes at two different sites as a single volume, and another set of the sites to have a volume which is a replications of the volume presented by the VSL, and enabling the system to transparently shift which subset of the sites are replicated by the VSL and which sites are replications of the volume presented by the VSL; where the replication of the VSL is performed by a second replication technique.

Abstract: A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.

Abstract: A management device includes a node information storing unit which stores, for each of plural operation devices, an device state representing whether the operation device is in a working state or in a non-working state, the device state associated with an identifier of the operation device, a fault state acquiring unit which acquires a value representing whether or not a fault exists from each of the operation devices that are in the non-working state, and an instruction unit which sends, when a number of the operation devices is smaller than a predetermined value, a work instruction to the operation device from which the value representing that no fault exists is acquired and which is in the non-working state, among the plural operation devices which make a transition to the working state when receiving the work instruction while in the non-working state.

Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive a tool error output determined by a code inspection tool and select at least one defect classification mapping profile based on the code inspection tool. Additionally, the programming instructions are operable to map the tool error output to one or more output classifications using the selected at least one defect classification mapping profile and generate at least one report based on the one or more output classifications.

Abstract: A system and method are provided for accurately emulating a printer on a computing device that is not connected to the printer. The computing device is provided with firmware and programming code that interfaces with the firmware for a customized printing operation. The firmware is provided with the printer and the computing device. The programming code is provided with the computing device, and the computing device runs the programming code. The programming code interfaces with the firmware provided with the computing device and causes the computing device to emulate the printer, when the printer runs the programming code. The computing device and the printer are not connected.

Abstract: A method for reordering a test pattern set for testing an integrated circuit is disclosed. A productivity index is computed for each test pattern in a test pattern set. The productivity index of a first test pattern and the productivity index of a second test pattern are compared. If the productivity index of the second test pattern is larger than the productivity index of the first test pattern, the location of the first test pattern and the second test pattern are swapped.

Abstract: An automated test system for a semiconductor device to concurrently perform multiple device tests is provided. The system may include at least one test client, at least one test site and a test server. The at least one test client is configured to receive a test request of at least one worker and to display a test response. The at least one test site is configured to test at least one device under test (DUT). The test server is configured to communicate with the at least one test client and the at least one test site, divide and/or drive the at least one test site in response to the test request of the at least one test client, and transmit a response of the at least one test site to the at least one test client.

Abstract: Methods, systems, and computer readable media can provide diagnosis of service-affecting issues in CPE devices. The diagnostic process can include retrieving a testing hierarchy associated with a received diagnostic command, executing the lowest-level diagnostic in the testing hierarchy, successively executing the remaining diagnostics in the testing hierarchy in the order implicated by the hierarchy until the commanded diagnostic is executed, and identifying the service-affecting issues found.

Abstract: A method executable on one or more processors for modeling a test space is provided. The method may include defining a coverage model including a set of variables. The method may also include selecting one or more variables within at least one subset of a plurality of subsets of the set of variables. The selection may be according to an interaction level requirement defined for at least one or more of the subsets, whereby the interaction level corresponds to a coverage of the test space that covers a plurality of possible combinations of the one or more variables at multiple levels. Furthermore, respective values for the one or more selected variables within the subset of the set of variables may be assigned. The method may also include one or more definitions for value combinations for said variables with assigned values.

Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive a tool error output determined by a code inspection tool and select at least one defect classification mapping profile based on the code inspection tool. Additionally, the programming instructions are operable to map the tool error output to one or more output classifications using the selected at least one defect classification mapping profile and generate at least one report based on the one or more output classifications.

Abstract: System, method, and non-transitory medium for generating a test scenario template based on a user profile, includes steps of identifying runs of test scenarios run by users belonging to different organizations on software systems of the different organizations; clustering the runs to clusters that include similar runs of test scenarios; receiving a profile of a user; selecting from the clusters a certain cluster that suits the profile; the certain cluster includes a first run of a first test scenario associated with a first organization, and a second run of a second test scenario associated with a second organization, in addition, the first run is not identical to the second run, and the first organization is not the second organization; removing from the first run proprietary data associated with the first organization; and generating a test scenario template based on the first and second runs.

Abstract: A method for evaluating a gauge controller is disclosed. The method includes counting a number of high pulses for a plurality of signal types until either each of the control signals present low signals. After the number of high signals are counted, an angular offset of a gauged needle is calculated.

Abstract: A document for variable printing and print settings including a conditional print setting that depends on metadata included in the document are received, information that is common between the conditional print setting and metadata included in the document is replaced with unique information, and printing is instructed using the conditional print setting and the document in which the common information is replaced with the unique information.

Abstract: Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.

Abstract: A traction battery connection simulator is disclosed comprising a plurality of power supplies connected to simulate a traction battery and a plurality of switching devices that selectively connect the power supplies to a controller under test. The simulator further comprises a controller programmed to selectively connect at least one of power supplies to the controller under test for a predetermined period of time before connecting remaining power supplies. The controller may also be programmed to disconnect at least one power supplies from the controller under test for a predetermined period of time before disconnecting remaining power supplies. Voltages associated with each power supply and currents through each switching device may be compared to corresponding predetermined ranges. An indicator may be set in response to at least one of the voltages and currents being outside of a corresponding predetermined range.

Abstract: A test pattern is sequentially selected from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit. Power consumption in each of regions obtained by substantially equally dividing a layout region of a semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit is estimated. A searching is conducted for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions. A new test pattern sequence constituted by a plurality of test patterns including no don't care bit is generated by defining the don't care value obtained by the searching as a don't care value of the selected test pattern.

Abstract: A digitizer system (DS) may include one or more input channels to receive sample data, and an acquisition state machine (ASM) to organize the sample data into one or more acquisition records according to events of interest, and generate framing information corresponding to the one or more acquisition records. The events of interest may be identified by a trigger circuit in the DS, and relayed to the ASM for organizing the sample data. The DS may further include a data interface capable of receiving the one or more acquisition records and the framing information, encoding the one or more acquisition records and the framing information into encoded data, and transmitting the encoded data to an expansion module. The expansion module may receive the encoded data, decode the encoded data, and recover the sample data from the decoded data according to the framing information and the one or more acquisition records.

Abstract: Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement ent circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.

Abstract: A test pattern generation device for generating a new test pattern keeping the feature of original test patterns. The test pattern generation device includes a logic value generation unit for generating a new logic value by referring given logic values of a first bit, a second bit and a third bit and by keeping or reversing a logic value of the second bit, wherein a logic value of the first bit is the same with a logic value of a given initial test pattern or a new test pattern generated by the test pattern generation device based on the initial test pattern, wherein a logic value of the second bit is the same with a logic value of the initial test pattern, and wherein a logic value of the third bit is the same with a logic value of the initial test pattern or the new test pattern.

Abstract: A distributed reflectometry device for diagnosing a network is disclosed. According to one aspect, the device includes at least one transmission line and several reflectometers connected to the network. A transmission portion of the device includes a first memory configured to store at least one test signal and a second memory configured to store weighting coefficients. The transmission portion may also include a first multiplier of a test signal (s) with a coefficient ?m, for producing a measurement m and a digital-to-analog converter connected to the line. A reception portion of the device includes an analog-to-digital converter configured to receive a signal from the line and provide a vector for the measurement m, a second multiplier of configured to multiply the vector with the coefficient ?m, an averaging module, and a post-processing and analysis module.

Abstract: A driving circuit of a test access port is disclosed. The driving circuit includes an input terminal for receiving a first test data signal when the driving circuit is operating in an external test mode. The driving circuit is configured to receive a second test data signal (BS) carrying a test command to be executed on the test access port when the driving circuit is operating in an internal test mode. The driving circuit comprises a control logic circuit configured for processing the test command and generating therefrom an internal test data signal carrying the processed test command when the driving circuit is operating in the internal test mode. The driving circuit includes a selector configured for generating a selected test data signal, the selected test data signal being selected from the first test data signal when the driving circuit is operating in the external test mode.

Abstract: A highly flexible, compact, lightweight, and portable testing system for use with radiation testing activities. The testing system is coupled to a device under test (DUT), which can be positioned in such a way that the top of the die package is exposed to the direct ion beam during radiation testing. A variety of sensors, onboard memory systems, programmable interfaces, onboard control systems, data output devices, and different types of interfaces are also provided which provide an ability to perform testing procedures while having a maximum ability to orient the DUT and perform a wide variety of testing currently unavailable.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Abstract: This invention has an object of providing a semiconductor integrated circuit enabling further reduction of the number of test terminals without depending on a compression/expansion technique alone. The semiconductor integrated circuit of the invention is connected to a terminal group used to exchange test information of a circuit to be tested, and comprises a utilization device which utilizes, when reading a test result, a terminal subgroup of the terminal group, which is not used to transmit information required to read the test result, to receive the test result from the circuit to be tested.

Abstract: A system for testing electronic circuits includes first, second, and third standard interfaces. A test port master and a test port slave are connected to an external testing apparatus. The first, second, and third standard interfaces are tested in first, second, and third test modes, respectively. The tests are initiated by asserting a test mode activate and first, second, and third test mode enable signals, respectively, which enable reuse of test patterns across different electronic circuits.

Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: A display method and apparatus provides an easy to interpret presentation of multiple channel data, in the form of columns where the height of the column represents the relative measurement. A threshold line provides an indication of whether the measurement is above or below the threshold. Greater detail and numeric measurement values can be displayed for individual channels while the multiple channel display is in view.

Abstract: Provided is a method for determining the urgency for repairing a diagnostic condition in a vehicle. Upon determining the repair urgency, a driver may decide to continue driving (in the case of a “low” urgency determination), or cease driving (in the case of a “high” urgency determination). The urgency status may also enable a driver to shop around for the repair (in the event of a “low” urgency status), or to seek immediate assistance (in the event of a “high” urgency status).

Abstract: A device with a plurality of elements separated into groups, each element including an activation terminal, an input terminal and an output terminal, a plurality of first signal lines, and a plurality of second signal lines, where the input terminals of each element in each group are commonly connected to one of the plurality of first signal lines, the input terminals of the different groups are connected to different first signal lines, and the output terminals of the each element in each group are independently connected to a different one of the plurality of second signal lines.

Abstract: A monitoring system includes a testing apparatus and a display control apparatus connected to the testing apparatus. The testing apparatus includes a plurality of testing locations and a collection module connected to the plurality of testing locations. Each of the plurality of testing locations receives a tested product, which is tested by the testing apparatus. The collection module collects testing states of the tested products. A display apparatus is connected to the display control apparatus. The display control apparatus controls the display apparatus to show a plurality of indicating blocks corresponding to the plurality of testing locations. The display apparatus is adapted to display the plurality of indicating blocks to match the plurality of testing locations. The display control apparatus controls each of the plurality of indicating blocks to show the testing state of the tested product in each the plurality of testing locations.

Abstract: A method for creating workload model to test performance of a critical application in a data processing network (112) is disclosed. The method includes receiving (202), at one of the plurality of data processing units (114a), an activity log with a plurality of entities from the data processing network (112). The method further includes creating (204) a transaction log of all transactions conducted using the activity log. Further the method determines (206) a plurality of transaction metrics using the transaction log, wherein the plurality of transaction metrics comprises an average transaction response time, a transaction throughput etc. The method further creates a workload model to test the critical performance of an application in the data processing network (112) based on the plurality of transaction metrics and provide effective performance test strategies.

Abstract: Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The data I/O unit selectively drives a first global I/O line and first/second global I/O lines according to the first or second test modes. The data transmitter selectively transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line, and the data on the first and second global I/O lines onto the first and second local I/O lines according to the first or second test modes.

Abstract: A test system and a test method thereof. The test system includes an electronic device and a test device. The electronic device includes a plurality of output interfaces and provides a corresponding test signal via the output interfaces according to a group of operation commands. The test device includes a transforming unit, a multiplexer unit, a processor unit and a plurality of test interfaces which are respectively coupled to the output interfaces. The transforming unit transforms the test signals received via the test interfaces. The multiplexer unit selects the transformed test signals. The processor unit controls the multiplexer unit to select one of the transformed test signals, and determines whether the transformed test signal being selected conforms a predetermine condition for generating a test result signal. The processor unit controls the communication unit to transmit the test result signal to the electronic device according to the test result signal.

Abstract: A testing method and an apparatus applied to an IP phone system for testing an electronic device is provided. The electronic device has a true table and signal ports. The electronic device is connected to a power generating jig and an IP phone simulator via a cable. A power generated by the power generating jig is provided. A first value power command issued by the IP phone simulator is provided. Whether the electronic device is able to correctly control the signal ports in response to the first value power command and the true table is determined. A second value power command issued by the IP phone simulator is provided. Whether the electronic device is able to correctly control the signal ports in response to the second value power command and the true table is determined. If so, it is concluded that the electronic device passes the test.

Abstract: A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmable to provide test patterns for use in automated test equipment. The configurable IC includes a configurable interface core that is programmable to provide functionality of one or more protocol based interfaces for a device under test (DUT) and is programmable to interface with the DUT. The system also includes a connection configurable to couple the configurable IC to the DUT.

Abstract: A card interface direction detection system includes a card. A power pin is mounted to the card and connected to a power source. A ground pin is mounted to the card and connected to a ground. A direction pin is mounted to the card. A controller is coupled to an information handling system (IHS) and that includes an in node and an out node that are each connected to the direction pin. The in node is directly connected to the direction pin and a resistor is located between the out node and the direction pin such that a signal sent through out node results in a signal received through the in node that allows the controller to detect whether the mode of operation of the card is supported by the IHS.

Abstract: Decompressor circuitry includes a first segment and a second segment each comprising memory elements (MEs) and (i) said first segment receives the plurality of static variables originating from the tester, and (ii) and said second segment, receives the plurality of dynamic variables originating from the tester.

Abstract: Disclosed is an integrated circuit (IC) chip with a built-in self-test (BIST) architecture that allows for in the field accelerated stress testing. The IC chip can comprise an embedded processor, which selectively alternates operation of an on-chip test block between a stress mode and a test mode whenever the IC chip is powered-on such that, during the stress mode, the test block operates at a higher voltage level than an on-chip functional block and such that, during the test mode, the test block operates at a same voltage level as the functional block and is subjected to testing. Also disclosed are a system, method and computer program product which access the results of such testing from IC chips in a variety of different types of products in order model IC chip performance degradation and to generate IC chip end of life predictions specific to the different types of products.

Abstract: A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.

Abstract: A computer implemented system for testing electronic equipment where a plurality of types of systems can be tested using a single test specification.

Abstract: A burn-in method for an embedded Multi Media Card (eMMC), and a test board using the same, and an eMMC tested by the same. The disclosed burn-in method comprises the steps as below: writing a test pattern to a flash memory of the eMMC; electrically connecting a command line of the eMMC to ground to operate the eMMC in a boot state; performing a burn-in procedure on the flash memory when the eMMC is in the boot state and the test pattern is recognized as being contained in the flash memory; and collecting a test report during the burn-in procedure, wherein the test report is stored in the flash memory.

Abstract: A heterogeneous multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. A debug control circuit is connected between the first and second TAP controllers and the first and second debug ports. Based on external configuration signals, the debug control circuit configures the connections between the first and second TAP controllers and the first and second debug ports according to predetermined configuration modes, which allows flexibility in debugging the heterogeneous multi-core integrated circuit.

Abstract: Methods and structure are disclosed for analyzing different signaling pathways through a test signal selection hierarchy utilizing test patterns. One embodiment comprises an integrated circuit that includes a block of circuitry, a test signal generator, and a test signal selection hierarchy. The block of circuitry generates internal operational (TOP) signals for performing functions. The test signal generator generates test patterns that correspond with the IOP signals. The test signal selection hierarchy receives IOP signals and the test patterns, and selectively routes received signals to test pads. The test signal selection hierarchy routes the test patterns via signaling pathways through the test signal selection hierarchy to provide outputs signals on the test pads. The output signals are usable by an external test system to determine two or more of: a crosstalk, inter-symbol interference, a signal skew, and a threshold voltage for detecting bit transition on signaling pathways.

Abstract: Method for validating a single waveform or series of waveforms that are intended for evaluating signals within an automated testing environment. Test signal data is supplied by an external source. The method creates a golden template from a known, good instance of the waveform under test and algorithmically applies it to other waveforms under test to determine compliance. In the application to video waveforms, timing parameters, deflection parameters and image content parameters are simultaneously tested resulting in efficient concrete and tangible results. Instead of providing the known, good instance of the waveform under test to a processor that implements the method, descriptive parameters of the known, good instance of the waveform may be provided to the processor that calculates data points of the expected video waveforms and then determines rules for the waveform based on the calculated data points.

Abstract: A circuit test system including a circuit test apparatus and a circuit to be tested is provided. The circuit test apparatus provides a first clock signal. The circuit to be tested includes a plurality of input/output pads and at least one clock pad. At least two input/output pads of the input/output pads are connected to each other to form a test loop during a test mode. The clock pad receives the first clock signal. The circuit to be tested multiplies a frequency of the first clock signal to generate a second clock signal, and the test loop of the circuit to be tested is tested based on the second clock signal during the test mode. The frequency of the second clock signal is higher than that of the first clock signal. Furthermore, a circuit test method of the foregoing circuit test system is also provided.