Abstract: A method and circuit for testing phase detectors in a delay locked loop is provided. The method includes storing output from a first phase detector and from a second phase detector when the counter is at the +0, +1, and ?1 counter positions, and comparing the results to determine whether a phase detector is faulty. The circuit implementing this technique uses a second phase detector configured to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.

Abstract: The invention relates to a device (10), for the preparation, execution and evaluation of a non-destructive analysis with one or more suitable analysis devices (20) of any type. The device (10) includes an input device (12), an output device (14), a data store, a data processing unit (16), an interface (18) for connection of the analysis device (14), by means of which data may be transmitted in both directions and a standardised data processing programme. It is possible to generate an analysis flow scheme, by means of the data processing programme, whereby an analysis object (26) can be defined, various analysis regions (28) of the analysis object (26) can be determined, a particular analysis device (20) can be selected, analytically-relevant parameters can be selected and determined for the selected analytical device (20), the type of visualisation and the analysis of the measured analytical values can be determined and the obtained analytical results can be archived and stored.

Abstract: An efficient automated test system and method are presented. In one embodiment, an automated test system is implemented in a routed event distribution architecture. In one exemplary implementation, an automated test system includes a plurality of test instruments, a switched event bus, and a test controller component. The plurality of test instruments perform testing. The switched event bus communicatively couples the plurality of instruments. The switched event bus comprises an event distribution switch that flexibly routes event information across event lines of the switched event bus. The test controller controls the testing and the switched event bus.

Abstract: A storage battery includes a battery housing and a plurality of electrochemical cells in the battery housing electrically connected to terminals of the battery. A battery test module is mounted to the battery housing and electrically coupled to the terminals through Kelvin connections. A display or other output is configured to output battery condition information from the battery test module. The battery test module is configured to automatically carry out a battery test when a voltage across the battery falls below a predetermined threshold.

Abstract: Disclosed are systems and methods for testing a network service. In one embodiment, a system and a method pertain to intercepting a message sent by a network service under test and directed another network service, determining whether the message should be redirected to a mock network service that emulates operation of the other network service, and redirecting the message to the mock network service if it is determined that the message should be so redirected.

Abstract: A technique for controlling instrumentation in an automatic test system includes providing a group of hardware resources that can be configured in a variety of ways to realize different instrument configurations, which generally correspond to different traditional instrument types. An instrument driver is provided for each of the different instrument configurations, and calls to each instrument driver may be inserted into a test program for controlling the respective instrument configuration. The instrument drivers direct control of the hardware resources via a support driver. The support driver thus provides a central location through which control of the various hardware configurations is processed. From the user's point of view, the instrumentation is programmed as if it consists of a collection of traditional instrument types. But at the hardware level the instrumentation is highly integrated and efficiently realized.

Abstract: An integrated circuit (IC) with a self-proofreading function includes a micro control unit (MCU) and a one-time programmable (OTP) memory connected with the MCU. The OTP memory includes an instruction memory region for storing instructions and a parameter memory region for storing standard parameters for proofreading. The MCU computes a measured result according to the standard parameters. The IC can operate without an external memory, therefore, the proofreading procedure using the IC is simplified, and the cost of the terminal product using the IC can be reduced.

Abstract: A method for testing a connection between an audio receiving device and a motherboard is disclosed. The method includes the steps of: preparing a data storage medium containing an original audio data file; playing the data storage medium on an audio playing device with audio signals generated thereof, the audio playing device being connected to the audio receiving device; receiving the audio signals by the audio receiving device; transmitting the audio signals to the motherboard via the connection between the audio receiving device and the motherboard; outputting the audio signals from an output port; receiving the audio signals by an input port; recording the audio signals as a recorded audio data file; comparing the two audio data file; and reporting a test result indicating that the connection is in good condition if the two audio data files are identical.

Abstract: To determine one or more features of an in-die structure on a semiconductor wafer, a correlation is determined between one or more features of a test structure to be formed on a test pad and one or more features of a corresponding in-die structure. A measured diffraction signal measured off the test structure is obtained. One or more features of the test structure are determined using the measured diffraction signal. The one or more features of the in-die structure are determined based on the one or more determined features of the test structure and the determined correlation.

Abstract: A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.

Abstract: A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

Abstract: The present invention extends to methods, systems, and computer program products for enhanced Universal Plug and Play (“UPnP™”) compliance testing. A control point (e.g., a computer system) and one or more devices (e.g., printers, wireless gateways, etc.) are network connectable (or are connected) to a common network. The control point includes a test tool that can execute scripts to simulate UPnP™ functionality. Using scripts allows more flexible and programmatic UPnP™ compliance testing. Multiple devices can be selected for testing thereby reducing the burden associated with individually testing devices on an isolated network. Test logs can be secured using digital signatures to reduce the likelihood of test logs being intentionally or inadvertently altered prior to being received at a certification authority.

Abstract: The present invention discloses a system for synchronously controlling the testing of pluralities of devices, comprising a server, a switch coupled to the server, and a testing instrument coupled to the server. Pluralities of computers are coupled to the server respectively, wherein the pluralities of devices are respectively connected to the pluralities of computers and the switch under testing. The parameters of the pluralities of devices include a first type test item that is testable by the pluralities of computers, and a second type test item that is testable by the testing instrument. The switch includes a RF switch. The server is connected to the testing instrument by a GPIB cable (or other instrument control interface and the server is connected to the pluralities of computers via local area network (LAN) such as Ethernet.

Abstract: A system, method and apparatus for triggering a plurality of test and measurement instruments in a substantially simultaneous manner logically combines a trigger enable signal provided by each of a plurality of signal processing devices to produce a combined trigger signal. The combined trigger signal then triggers each of the plurality of signal Processing devices.

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.

Abstract: An automatic safety test system, which comprises a control interface of a control unit for controlling the switching of a switch in a server unit and automatically switching to a specified testing point of an electronic product, and connects a bus interface of the control unit to a plurality of testing instruments for sending the values measured by the testing instrument at the specified testing point to a communication interface record of the control unit through the bus interface. Therefore, the automatic safety test system of the invention can automatically test every specific safety testing item at each testing point of the electronic product, and thus further achieves the objectives of saving time, manpower and resources.

Abstract: A method and apparatus for synchronizing plural test devices coupled to a host. A counter of each of the devices is initialized, and each of the counters is incremented, such as by a periodic signal indicating a start of a data stream. An action, typically either a source signal or a measurement signal, is triggered when a respective counter reaches a programmed counter value.

Abstract: A device and method for testing the functionality of various electronic device components. The device is portable and is capable of being upgraded with changes in technology. The device is enclosed within a housing, which comprises a power supply and a display. The disclosed device incorporates a tester for computer components, including but not limited to, power supply, microprocessor, motherboard, system memory, video subsystem, mass storage devices, and cables.

Abstract: A network including a bus through which data is transmitted and a plurality of network devices connected to the bus to form the network. In the network, at least one of the network devices performs measurement at timings in a predetermined cycle T and outputs data concerning the measurement result on the bus. Another network device detects the cycle T in which the data concerning the measurement result is output, performs measurement at the timings in the predetermined cycle T, and outputs the measurement result on the bus.

Abstract: An instrument having a set of data acquisition capabilities recognizes an operand in an equation as a data reference when the operand refers to data which the instrument is capable of acquiring. The instrument automatically configures itself to acquire the data to which the operand refers.

Abstract: An apparatus and method of operating automated test equipment (ATE) in a networked environment of multiple external test controllers. The system resources responsible for coordinating the shared uses of the ATE by the multiple external test controllers are centralized within the ATE. As a result, programming of the respective test controllers is simplified since the test controllers no longer need be responsible for communicating among themselves to coordinate or otherwise determine how and when access to the ATE is granted to any particular test controller.

Abstract: A test apparatus that tests a device under test is provided. The test apparatus includes: a control processor that executes a test program to test the device under test; a test unit connected to the device under test that tests the device under test according to an instruction by the control processor; and a relay section connected to the control processor and the test unit that relays a control instruction transmitted from the control processor to the test unit. The relay section includes: a buffer section that buffers the control instruction to be written to the address assigned from the control processor to the test unit; a timing storage section that stores a timing at which the control instruction received from the control processor should be transmitted to the test unit; and a buffer control unit that transmits the control instruction buffered in the buffer section to the test unit in response to that the timing stored in the timing storage section comes.

Abstract: Disclosed are a method, information processing system and computer readable medium for performing a system test on a program. The method comprises creating a test plan associated with a system test. The system test is for testing a program within an environment. At least one test trigger to be monitored for during the system test is defined within the test plan. Execution of the system test on a system under test for the at least one test trigger is monitored. An occurrence of the at least one test trigger is determined. The test plan is modified to take into account the occurrence of the at least one test trigger in response to determining the occurrence. Execution of the system test is continued based on the modified test plan.

Abstract: There is provided a semiconductor test apparatus including: a first waveform generating means that generates a common pattern waveform corresponding to common information common to each of a plurality of semiconductor devices; a plurality of second waveform generating means that generates individual pattern waveforms corresponding to a plurality of individual information individually prepared in response to each of the plurality of semiconductor devices; and a waveform switching unit that selectively performs an operation of inputting the common pattern waveform generated from the first waveform generating means in common and an operation of inputting the individual pattern waveforms respectively generated from the plurality of second waveform generating means individually, into each of the plurality of semiconductor devices.

Abstract: Methods, systems and program products are disclosed for determining whether a measurement system under test (MSUT) matches a fleet including at least one other measurement system. The invention implements realistic parameters for analyzing a matching problem including single tool precision, tool-to-tool non-linearities and tool-to-tool offsets. A bottom-line tool matching precision metric that combines these parameters into a single value is then implemented. The invention also includes methods for determining a root cause of a matching problem, and for determining a fleet measurement precision metric.

Abstract: In a method for verifying the operation of a plurality of test system instruments, a harness cable is electrically coupled to a plurality of test signal ports on the plurality of test system instruments. A first plurality of test measurements are then initiated via the harness cable, with the first plurality of test measurements being made between two or more sets of test ports that are on three or more of the instruments. The plurality of test measurements are captured from the test system instruments using a computer. The computer then indicates to a user whether ones of the plurality of test measurements are within defined ranges. A second plurality of test measurements, between ones of the plurality of test instruments and a test module, may also be initiated via the harness cable. Exemplary harness cable embodiments are also disclosed.

Abstract: Various apparatuses, methods, computer programs, and other systems are disclosed for facilitating testing of a module. In embodiment, a method is provided that comprises the steps of creating a plurality of tasks in a computer system, each of the tasks comprising a list of commands that are sent to a plurality of test devices, the test devices comprising the module to be tested and at least one controlled device interfacing with the module during a test of an operation of the module. In addition, the tasks are organized according to a multi-level hierarchy. The tasks are executed according to an order inherent in the multi-level hierarchy, wherein the execution of each task entails communicating the commands of each task to a respective one of the test devices.

Abstract: A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.

Abstract: A test system and method for scheduling and running multiple tests on a single system residing in a single test environment. The test system comprises a processor operable to receive a request to run a selected test on the system at a selected start time, and determine a time slot for the selected test. The test system is also operable to identify any scheduled tests to be run on the system within the time slot, and identify any conflicts between the selected test and any scheduled tests. If no scheduled tests are identified or if no conflicts are identified, the processor is operable to schedule the selected test to run on the system at the selected start time. If conflicts are identified, the processor is preferably operable to determine an alternative start time for the selected test that avoids any conflicts. Various exemplary embodiments of the test system and associated method are provided.

Abstract: A method for use with a test system having sites that hold devices under test (DUTs) includes executing a first site loop to iterate through the sites, where the first site loop includes an instruction to program hardware associated with at least one of the sites, and executing a second site loop to process data received from the DUTs, where the second site loop and the first site loop have a same syntax.

Abstract: A method for managing a pattern object file in a modular test system is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, and where the at least one site controller controls at least one test module and its corresponding device under test (DUT). The method further includes creating an object file management framework for establishing a standard interface between vendor-supplied pattern compilers and the modular test system, receiving a pattern source file, creating a pattern object metafile based on the pattern source file using the object file management framework, and testing the device under test through the test module using the pattern object metafile.

Abstract: A system for automatically comparing test points of a PCB includes an application server (1) and a database (6). The application server includes: a PCB file selecting module (10) for selecting a target file and a source file from the database; a test point data extracting module (12) for extracting test point data from the target file and the source file; a table generating module (14) for generating a target table according to the extracted test point data from the target file and generating a source table according to the extracted test point data from the source file; a comparing module (16) for comparing the test point data of the target table and the source table one by one and storing comparison results on those test points which have been modified; and a report generating module (18) for generating a comparison report. A related method is also disclosed.

Abstract: A method for developing a test program for a semiconductor test system is disclosed. The method includes describing a test plan file in a test program language (TPL), where the test plan file describes at least one test of the test program, describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, where the test class file describes an implementation of the at least one test of the test program, and generating the test program using the test plan file, the test class file, and the pre-header file.

Abstract: A system and method for online configuration of a measurement device for a measurement system. The user accesses a server with a client computer over a network and specifies a desired measurement task. If the user lacks the hardware required to perform the task, hardware specifications and configuration software and/or data specific to the user's application, i.e., to perform the task, are sent to a manufacturer, who pre-configures the hardware with the configuration software and/or data to perform the task and sends the pre-configured hardware to the user. The hardware may be re-configurable hardware, such as a programmable hardware element or processor/memory based device. Configuration software and/or data for configuring the user's measurement system hardware (and/or software) to perform the desired task may also be sent to the user. The configuration software sent to the user may comprise a graphical program usable by the measurement system to perform the task.

Abstract: The present invention is directed to a system and method for establishing communication between a flight simulator and a secondary control system, such as a Flight Management System (“FMS”). Information can be transmitted between the flight simulator and the secondary control system via a socket in a TCP/IP connection between the two systems. In the event that the secondary control system does not natively communicate in TCP/IP format, the information must be translated to and from the TCP/IP format. In this manner, an actual deliverable version of the secondary control system, possibly operating on can be used.

Abstract: An integrated circuit test method is provided that utilizes shared tester resources physically located at different geographical sites throughout the world to test specific integrated circuits, thereby maximizing utilization of all tester resources and, thereby, dramatically reducing the overall cost to test.

Abstract: A measurement device operable to communicate with a computer system via files. The computer system may receive one or more files created by the measurement device, where the files include measurement data generated by the measurement device and may utilize the files to perform a measurement application. The measurement device may also be operable to receive a configuration file from the computer system and configure or control itself according to commands or settings therein. In one embodiment the measurement device may appear to the computer system as a USB Mass Storage device, and the files created by the measurement device may appear as files stored on a USB Mass Storage device. Thus, the computer system may communicate with the measurement device to obtain the measurement data files in the same standard manner in which it would obtain files stored on any other USB Mass Storage device.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: System and method for performing dynamic routing in a measurement system to perform a measurement task. The system includes a computer and one or more measurement devices. One or more topography descriptions (TD) representing connectivity between devices and/or device components in the measurement system are received and preprocessed to generate corresponding graphs. A routing expert receives and analyzes a routing specification indicating source and destination terminals in the measurement system. The system dynamically computes a plurality of routes from the source terminal to the destination terminal by traversing the graphs and selecting the plurality of routes based on a metric. The computed routes are stored in a run-time specification for use at runtime to perform the measurement task. At runtime, a route is selected from the plurality of routes, and the system configures the one or more measurement devices with the selected route for performing the measurement task.

Abstract: An automated system and method for conducting a usability test. The system conducts the usability test and records events that occur on the computer screen in sync with both the video and audio of the user and creates a complete chronicle of events that occur behind the scenes in the applications and the operating system. The system, depending upon the settings specified in the configuration, also captures other input streams and then saves the complete recording of the usability test, along with all the desired events and captures, in a file format. The system allows a remote viewer to observe, in real time, the recording of the usability test and to set markers at critical moments during the recording which are to be recorded. The system also allows the manager or administrator to configure the preferences, import and analyze the usability test and recording files, and prepare presentation videos of the usability test based upon the analyzed criteria.

Abstract: A method for integrating test modules in a modular test system is disclosed. The method includes controlling at least one test module and its corresponding device under test (DUT) with a controller, establishing a standard module control interface between a vendor-supplied test module and the modular test system with a module control framework, installing the vendor-supplied test module and a corresponding vendor-supplied control software module, where the vendor-supplied control software module is organized into a plurality of vendor-supplied module control components, configuring the modular test system based on the module control framework and the plurality of vendor-supplied module control components, and accessing the vendor-supplied test module in accordance with the plurality of vendor-supplied module control components using the module control framework.

Abstract: A test apparatus has multiple instruments that are synchronized with respect to one another so that a trigger signal may be generated in response to events occurring at different instruments. The events may correspond to events defined within a test program or events detected at a device under test. A partial trigger signal is generated by each of the different instruments, and the partial trigger signals are used in generating the trigger signal. Different offset delays are applied to the partial trigger signals so that the partial trigger signals generated by the different instruments are synchronized with respect to each other.

Abstract: An automatic test system, such as might be used to test semiconductor devices as part of their manufacture. The test system uses instruments to generate and measure test signals. The automatic test system has a hardware and software architecture that allows instruments to be added to the test system after it is manufactured. The software is segregated into instrument specific and instrument independent software. Predefined interfaces to the software components allow for easy integration of instruments into the test system and also easy reuse of the software as the physical implementation of the test system or the instruments changes from tester to tester in a product family.

Abstract: In a test system, a test method, and a program for use in verifying states in a target, a predetermined state is previously defined as an intermediate state among states which can be taken by the target. On causing a transition to occur in the target from a previous state to a next following state, the transition is caused to occur in the target from a previous state to the intermediate state. Then, the target makes the transition from the intermediate state to the next following state. For this purpose, the test system stores intermediate state transition procedures from the previous state to the intermediate one and a self-state transition procedure from the intermediate state to the next following state.

Abstract: There is provided a test apparatus having a plurality of test modules. The test apparatus stores object diagnosing programs for controlling diagnosis of the object test module to be diagnosed of a certain type per type of the test module to be diagnosed and stores, separately from it, a set of identification information of diagnostic performance board to be mounted on a test head to diagnose the object test module to be diagnosed by the respective object diagnosing programs per type of the object test modules to be diagnosed. When the diagnostic performance board is mounted on the test head, the test apparatus obtains identification information of the diagnostic performance board and executes the object diagnosing program corresponding to that type under the condition that the identification information coincides with the identification information stored correlatively with the type of the designated object test module to be diagnosed.

Abstract: Methods and apparatus are provided for standardizing an interface infrastructure between sensor devices and client applications. The apparatus comprises a Sensor Application Integration Framework (SAIF) in the form of an application program interface (API) transport layer between sensor devices and client applications. Sensor services are registered in the SAIF API as interface definitions, and the client applications search the interface definitions corresponding to desired sensor services. An interactive handshake of messages and data between client applications and sensor services is implemented via the SAIF API by means of standard communication protocols such as XML. The SAIF API abstracts the details of the underlying sensor hardware from the client application, and can therefore function as a standard interface for sensor simulation, for sensor emulation, and for an active sensor device.

Abstract: An apparatus and method for automatically testing circuit boards, such as computer system boards and the like. The circuit board device under test (DUT) is loaded into an automated test apparatus (tester), which includes a mechanism for automatically connecting test electronics to various DUT circuitry and I/O ports via corresponding connectors on the DUT. A type of DUT is identified, and a corresponding set of tests are performed to verify the operation of the DUT. Appropriate power signals and sequencing are also applied to the DUT, as defined by it type. Data logging is performed to log the results of the testing. The apparatus includes replaceable probe/connector plates that are DUT-type specific and corresponding universal electronics and cabling to enable a variety of different board types to be tested with the same apparatus.

Abstract: A test apparatus has multiple instruments that are synchronized with respect to one another so that test data generated by them arrive at the pins of a device under test at the time specified in a test program. The synchronization of the multiple instruments is carried out by introducing delays to triggers that are generated and used by the multiple instruments. The amount of delay that is introduced varies from instrument to instrument and is based on differences in the actual transmission and processing delays and clock rates.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A system for managing and reporting laboratory data wherein the data is obtained at remote data-taking stations, transferred instantaneously by wireless communication to a main data-storing/manipulating station for recording therein without being recorded at the remote data-taking stations, and reported only from the data-storing/manipulating.