Including Multiple Test Instruments Patents (Class 702/121)
  • Patent number: 7082376
    Abstract: A test method executor is an object designed to execute a test method. The test method executor typically implements a simple state engine that is used to process the data presented by each smart test attribute. The test method executor invokes particular test methods in response to the processed data. The test method executor then condenses the results from all the attributes typically into a simple return value, which is designed to be interpreted by the test harness. The return value indicates, for example, whether the executed test method was a success, failure, or if the test method was “skipped.” Additionally, the test method executor is used to gather data about the method being invoked (such as the method name, which attributes are present, and the like.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: July 25, 2006
    Assignee: Microsoft Corporation
    Inventors: Michael Paul Robinson, Peter Gerber
  • Patent number: 7072787
    Abstract: A method for testing each one of the CPUs on each one of the plurality of director printed circuit. Results from such test are collected in a memory of a computer. The results are collected in a predetermined format. The method processes the collected data to present the results of the tests on a display of the computer in a different format. The different format comprises lines of information on the computer display. Each one of the lines of information identifies a corresponding one of the CPUs and indicates whether such corresponding one of the CPUs passed or failed the testing thereof.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 4, 2006
    Assignee: EMC Corporation
    Inventor: Shay Harel
  • Patent number: 7072788
    Abstract: A computer system comprising an operating system, a first component that comprises a first test module, a second component that comprises a second test module, and an interconnect coupling the first component and the second component is provided. The first test module is configured to provide a first test pattern to the second test module on the interconnect in response to a first signal from the operating system.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: July 4, 2006
    Assignee: Hewlett-Packard Development Company
    Inventors: Ken G. Pomaranski, Andrew H. Barr, Dale J. Shidla
  • Patent number: 7050923
    Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: May 23, 2006
    Assignee: National Instruments Corporation
    Inventors: David W Fuller, III, Michael L. Santori, Brian Sierer, Ganesh Ranganathan, John Pasquarette
  • Patent number: 7043390
    Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: May 9, 2006
    Assignee: Credence Systems Corporation
    Inventors: Michael F. Jones, Frederic Giral, William A. Fritzsche
  • Patent number: 7039545
    Abstract: Test development tools, systems and/or methods which include providing access to a pre-established serial test program having a series of test code portions; providing for evaluating the series of test code portions and determining whether any respective test code portions of the series of test code portions are independently operable thereby allowing for combination in a new test program, the evaluating and determining steps providing at least one output result thereof; and providing for defining a new test program including a new test code portion for at least partially concurrently testing first and second sub-parts of a device under test using the at least one output result of the evaluating and determining steps.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: May 2, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Laura Marie Bundy, Julia Ann Keahey
  • Patent number: 7039533
    Abstract: A storage battery includes a battery housing and a plurality of electrochemical cells in the battery housing electrically connected to terminals of the battery. A battery test module is mounted to the battery housing and electrically coupled to the terminals through Kelvin connections. A display or other output is configured to output battery condition information from the battery test module. Battery post extensions couple the battery test module to terminals of the battery.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: May 2, 2006
    Assignee: Midtronics, Inc.
    Inventors: Kevin I. Bertness, Jamey L. Butteris, Michael J. Fritsch
  • Patent number: 7035755
    Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: April 25, 2006
    Assignee: Credence Systems Corporation
    Inventors: Michael F. Jones, Robert Whyte, Jamie S. Cullen, Naveed Zaman, Yann Gazounaud, Burnell G. West, William Fritzsche
  • Patent number: 7020573
    Abstract: The present invention extends to methods, systems, and computer program products for enhanced Universal Plug and Play (“UPnP™”) compliance testing. A control point (e.g., a computer system) and one or more devices (e.g., printers, wireless gateways, etc.) are network connectable (or are connected) to a common network. The control point includes a test tool that can execute scripts to simulate UPnP™ functionality. Using scripts allows more flexible and programmatic UPnP™ compliance testing. Multiple devices can be selected for testing thereby reducing the burden associated with individually testing devices on an isolated network. Test logs can be secured using digital signatures to reduce the likelihood of test logs being intentionally or inadvertently altered prior to being received at a certification authority.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: March 28, 2006
    Assignee: Microsoft Corporation
    Inventors: Jonathan T. Wheeler, James R. Boldman
  • Patent number: 7017138
    Abstract: A system and method for dynamically determining a route through one or more switch devices at program execution time. A program operable to perform a programmatic request to dynamically determine a route may be created. For example, the request may specify a first endpoint (e.g., channel) of a first switch device and a second endpoint (e.g., channel) of a second switch device. In response to the request, the system may dynamically determine a route from the first endpoint to the second endpoint during execution of the program. Information indicating the determined route may be returned to the program.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: March 21, 2006
    Assignee: National Instruments Corporation
    Inventors: Srdan Zirojevic, Jason White, Scott Rust, Jucao Liang
  • Patent number: 7013232
    Abstract: System and method for online configuration of a device for a measurement system. The user accesses a server with a client computer over a network and specifies a task. If the user lacks the hardware to perform the task, hardware specifications are sent to a manufacturer, who sends the hardware to the user. The hardware may be re-configurable hardware (a programmable hardware element or processor/memory based device). Software products (programs and/or data) for configuring measurement system hardware (and/or software) to perform the task may be sent to the user. The hardware may be configured automatically or by the user. The software products may include programs usable by the measurement system to perform the task, configuration information for configuring the client computer or other measurement device, and/or hardware configuration program(s) for configuring a programmable hardware element. Thus, hardware and/or software specific to the user's application are be provided to the user.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: March 14, 2006
    Assignee: National Insurance Corporation
    Inventors: David W Fuller, III, Michael L. Santori, Brian Sierer, Ganesh Ranganathan, John Pasquarette, Joseph E. Peck, Matthew Novacek, Hugo A. Andrade, Newton Petersen
  • Patent number: 6993448
    Abstract: A computer-implemented system, method and medium for assessing the risk of and/or determining the suitability of a system to comply with at least one predefined standard, regulation and/or requirement. In at least some embodiments of the present invention, the method comprises the steps of: 1) automatically or manually gathering information pertaining to the system, 2) selecting one or more requirements with which the system is to comply; 3) testing the system against the requirements; 4) performing risk assessment of the failed test procedures, and 5) generating certification documentation based on an assessment of the first four elements.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: January 31, 2006
    Assignee: Telos Corporation
    Inventors: Richard P. Tracy, Hugh Barrett, Lon J. Berman, Gary M. Catlin
  • Patent number: 6990423
    Abstract: Automatic test equipment for testing non-deterministic packet data from a device-under-test is disclosed. The automatic test equipment includes a memory for storing expected packet data and a receiver for receiving the packet data from the device-under-test. A data validation circuit is coupled to the receiver for validating non-deterministic packet data based on the expected packet data from the vector memory.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: January 24, 2006
    Assignee: Teradyne, Inc.
    Inventors: Benjamin Brown, Peter Huber, Mark Donahue, John Pane
  • Patent number: 6977494
    Abstract: An arrangement for generating a digital current measurement signal includes an analog-to-digital (A/D) converter and an impedance circuit. The A/D converter is operable to receive a voltage input signal and generate a digital output signal having a digital value representative of the magnitude of the voltage input signal. The impedance circuit includes at least first and second alternative impedance values and a switch operable to cause the impedance circuit to have a select one of the first impedance value and the second impedance value. The impedance circuit is configured to receive a current signal to be digitized, the impedance circuit generating an output voltage signal representative of the current signal and having a magnitude dependent on the select one of the first impedance value and the second impedance value. The output voltage signal of the impedance circuit is then provided as the voltage input signal of the A/D converter.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: December 20, 2005
    Assignee: Landis+Gyr, Inc.
    Inventor: Anibal Diego Ramirez
  • Patent number: 6978218
    Abstract: A system and method for testing application program code within the presentation layer of an application server. A user interface is provided for entering data and triggering one or more actions to process the data; the data and/or actions are translated to a presentation layer format; results of the data and/or actions are received in a presentation layer format; and the entered data, actions and/or results are stored in the presentation layer format within a test script, the test script usable to test an instance of an application at the presentation layer of the application.
    Type: Grant
    Filed: October 13, 2003
    Date of Patent: December 20, 2005
    Assignee: SAP AG
    Inventors: Martin Kolb, Stefan Beck
  • Patent number: 6975957
    Abstract: Alteration of a Standard Commands for Programmable Instrumentation (SCPI) command set for instrument control. In representative embodiments, each command of the command set includes a different combination of SCPI grammatical elements; the SCPI grammatical elements are organized hierarchically in a tree data structure; and the tree has nodes with each node comprising one of the SCPI grammatical elements. A node to alter is selected, and an alteration to the selected node is specified. Access to the selected node, as well as to any descendant nodes of the selected node is restricted; the selected node is altered in accordance with the specified alteration, wherein the alteration of the selected node is performed at runtime; and the access restriction to the selected node and to any descendant nodes of the selected node is removed, wherein the access restriction, node alteration, and access removal are performed while the instrument is operational.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: December 13, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Timothy Nephi Tillotson, Sara Ting, Nathan A. Berg
  • Patent number: 6973402
    Abstract: A system for testing integrated circuits by testing the change of integrated circuits under various temperatures comprises: at least one two-dimensional matrix testing module which includes a testing section having arrays for plugging integrated circuits to be tested, a heating section corresponding with the above testing section for heating integrated circuits respectively; a computer mainframe for connecting said two-dimensional matrix testing module and controlling the whole operations of the testing system, and a database. With the above-described structure, said database and said two-dimensional matrix testing module can be connected with the computer mainframe such that the temperature control information can be transmitted to provide each heater of said heating section to generate a suitable temperature, heat the integrated circuit to be tested, and store the test information.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: December 6, 2005
    Assignee: PROGenic Technology Co., Ltd.
    Inventor: Yih-Min Lin
  • Patent number: 6963815
    Abstract: A test support program to effectively and reliably check performance of functions which operate with other unspecified servers. A pair of a request message and a response message is stored as a message log. When a processing function based on a program under development being checked outputs a test request message, a computer selects a message log appropriate to the test request message as a template message under preset selection rules. The computer creates a test response message by editing the response message of the selected template message under preset editing rules. Then the computer sends the created test response message as a response to the test request message.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: November 8, 2005
    Assignee: Fujitsu Limited
    Inventors: Yuzuru Watanabe, Yuichi Takada, Yasuyuki Fujikawa, Kenichi Yamashita
  • Patent number: 6947854
    Abstract: The present invention comprises systems and methods related to monitoring of energy usage on a power line. In a preferred embodiment, this system comprises (a) an electronic microprocessor-controlled digital electricity metering device coupled to the power line and comprising a non-volatile non-battery-powered data-storage device, wherein the metering device is capable of interval metering and of receiving a data request and transmitting data in response to the request over the power line; and (b) a data collector (preferably, a transponder) coupled to the metering device via the power line. The data collector is preferably capable of (i) receiving data from and transmitting data to the metering device over the power line, (ii) storing data received from the metering device over the power line, and (iii) receiving data from and transmitting data to a remotely located computer (preferably, a billing computer).
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 20, 2005
    Assignee: Quadlogic Controls Corporation
    Inventors: Sayre A. Swarztrauber, Doron Shafrir, Stanley C. Lo, Michael Newsome, Eric Jacobson
  • Patent number: 6925407
    Abstract: A controller with attachments for controlling specific electronic circuits is disclosed. Each attachment has a connector connectable to the electronic circuit to be controlled, and a memory accessible by the controller that contains configuration data for accessing the electronic circuit, and operational software for operating the electronic circuit.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: August 2, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Charles M. Duppong
  • Patent number: 6925428
    Abstract: A printed wiring board includes an input conditioner having a plurality of analog dc inputs and a plurality of analog dc outputs; a switching circuit having an analog dc output, the switching circuit being connected to the plurality of analog dc outputs of the input conditioner; a sample and hold converter having an analog dc output, the sample and hold converter being connected to the analog dc output of the switching circuit; an A/D converter having a digital output, the A/D converter being connected to the analog dc output of the sample and hold converter; a microprocessor connected to the digital output of the A/D converter; a timer circuit connected to the microprocessor; a random access memory connected to the microprocessor; and a VME interface connected to the microprocessor.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: August 2, 2005
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Gregory R. Kaminski
  • Patent number: 6925404
    Abstract: An integrated circuit testing apparatus having at least two of a test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: August 2, 2005
    Assignee: Micron Technology, Inc.
    Inventor: William E. Corr
  • Patent number: 6922651
    Abstract: A controller obtains sensor information from sensors mounted on a vehicle running on a road, and an information offer selector allows the driver of the vehicle to select on a screen whether to provide the sensor information to a center apparatus. If the driver allows provision of the sensor information, then the sensor information is transmitted to the center apparatus via radio communications. Thus, only the sensor information that is allowed by the driver is provided to the other vehicles.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: July 26, 2005
    Assignee: Fujitsu Limited
    Inventor: Toshio Endoh
  • Patent number: 6914424
    Abstract: An automatic integrated circuit testing system, device and method using an integrative computer. The system includes a machine frame having at least one testing computer for holding and testing the integrated circuit. The machine frame also has at least one automatic plugging/unplugging machine for engaging the integrated circuits with the computer system and removing the integrated circuits after testing has been completed. The machine frame further includes at least one controller device electrically connected to the testing computer and the automatic plugging/unplugging machine for controlling the movements of the automatic plugging/unplugging machine and the testing computer. The testing computer and the integrated circuit together form an integrative computer system capable of executing various general application programs and special testing programs for integrative testing and analysis.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: July 5, 2005
    Assignee: VIA Technologies, Inc.
    Inventors: Ming-Ren Chi, Peng-Chia Kuo
  • Patent number: 6889150
    Abstract: The invention relates to a method for determining and presenting an optimized arrangement and assembly of a measurement system of process measurement technology, especially of a radiometric measurement system, at a container or pipe, in which measurement system at least one characterizing parameter of a medium contained in the container or pipe is to be measured. The method proceeds with the aid of at least a first electronic computer (10) and a second electronic computer (11) connected therewith and containing a display- (12), a processor-controlled, data processing- (15) and an input-device (13), wherein container- or pipe-specific data and information on medium and on expected measurement range are taken into consideration. The method establishes therefrom an optimized arrangement of the measurement system at or on the container or pipe and presents this arrangement in a sketch.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: May 3, 2005
    Assignee: Endress + Hauser GmbH + Co. KG
    Inventors: Joachim Neuhaus, Wolfgang Kämereit
  • Patent number: 6889172
    Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: May 3, 2005
    Assignee: National Instruments Corporation
    Inventors: Brian Sierer, Ganesh Ranganathan, John Pasquarette, David W Fuller, III, Joseph E. Peck, Matthew Novacek, Hugo A. Andrade
  • Patent number: 6889159
    Abstract: Embodiments of the present invention generally provide a system and method for testing integrity of data transmitted to and from a target device through a data connection. In one embodiment, the method generally includes creating one or more test threads. The method further includes, for each test thread, generating a data load on the data connection by repetitively writing test data patterns to the target device and reading data patterns from the target device using a synchronous I/O dispatch method, measuring data throughput to and from the target device while generating the data load, comparing the data patterns read from the target device to the test data patterns to detect data corruptions. The method may further include generating debug information if a data corruption is detected by one of the test threads.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: May 3, 2005
    Assignee: Finisar Corporation
    Inventors: Steve Klotz, Michael D. Connell, Mark J. Lanteigne
  • Patent number: 6882951
    Abstract: A system and method for testing information handling systems distributes test units across a network to communicate with a test server. The test server communicates test executables and runtimes to the test units according to scripts of a script package, test engines associated with the test server and a test unit profile. To load and execute an executable and runtime on a test unit, a test controller associated with the test server sends an execution identifier to a test unit process abstraction layer controller. A validator of the test unit controller responds to the execution identifier with test unit configuration profile information that the test server controller applies to one or more test engines and a script to generate an executable and runtime that is sent to the test unit controller. An activator of the test unit process abstraction layer controller activates the executable scripts through the runtime and tracks test results.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: April 19, 2005
    Assignee: Dell Products L.P.
    Inventors: Matthew Eden, Jeremy Campbell, Sherman Quick, Matthew Selman
  • Patent number: 6876942
    Abstract: Electrical and mechanical components and associated processes for enhancing automated test of a system by permitting automated generation and application (injection) of real-world stimuli applied to the system under test and sensing responses from the system under test without the need for manual intervention. Test components of the present invention may intercede in the exchange of signals and power over various signaling paths within a system under test. Under programmable control by methods of the invention, the electrical components of the present invention may simulate any desired real-world stimulus on any signal path associated with the system under test. Electromechanical manipulation test components and sensor components allow automation of testing of physical aspects of the system under test. Centralized test sequencing and logic enables simpler test components to permit improved scalability and flexibility of the automated test system and processes.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: April 5, 2005
    Assignee: LSI Logic Corporation
    Inventors: Steven G. Hagerott, John M Lara
  • Patent number: 6873927
    Abstract: A control method for an automatic integrated circuit full testing system. A control device is utilized to control the testing process of the automatic integrated circuit full testing system. The steps for controlling the control device include driving an automatic transport device to fetch test integrated circuits from an integrated circuit supply rack to various testing computer stations. An automatic plug/unplug tool is driven so that each integrated circuit is plugged into the connector of a corresponding testing computer. All the testing computers are triggered to carry out respective preset testing programs. An image sensor is driven to monitor the an output image of the testing computers so that any abnormality in the integrated circuits can be determined. Thereafter, the automatic plug/unplug tool is driven to unload the tested integrated circuit from the testing computer.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: March 29, 2005
    Assignee: VIA Technologies, Inc.
    Inventors: Ming-Ren Chi, Peng-Chia Kuo
  • Patent number: 6865517
    Abstract: A method, apparatus and computer product that enables a processor associated with a node in a computer system having various nodes, the nodes having sensors which provide data, and the nodes being connected by a communications facility acquiring local data from the sensor and remote data from other nodes via the data transfer facility. The nodes process data from a local sensor at the node and from remote sensors at other nodes; and analyze the local data, data from other nodes and local decisions made at and received from other nodes to make a local decision for action at the node. A local decision made at a node is in turn communicated to other nodes.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: March 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: David F. Bantz, John S. Davis, II, Rafah A. Hosn, Nicholas M. Mitchell, Veronique Perret, Daby M. Sow, Jeremy B. Sussman
  • Patent number: 6859760
    Abstract: A method and apparatus are described for remote semiconductor microscopy whereby video signals are broadcast from one or more microscopes to remote viewers. A live video signal is broadcast from the microscope over a network to remote personal computers located in the offices of process engineers. The office-based process engineers are provided real-time, or substantially real-time, views of a wafer, including peripheral views of the wafer outside cell array boundaries. The process engineer, in his office, can direct a technician, operating the microscope in the clean room complex, to display a desired cell region-of-interest with the microscope. As a result, the process engineers can more efficiently collaborate to solve process problems or even develop new process techniques.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: February 22, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Michael J. Dorough
  • Patent number: 6832174
    Abstract: A system comprising a plurality of digital storage oscilloscopes (DSOs) in which each DSO acquires a common signal under test (SUT) according to respective clock signals having common frequency parameters and respective phase parameters such that a plurality of acquisition records may be interleaved to produce a higher effective resolution acquisition record.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: December 14, 2004
    Assignee: Tektronix, Inc.
    Inventors: Que Thuy Tran, David L. Kelly, Douglas A. Blegen
  • Patent number: 6826512
    Abstract: In one embodiment, when a problem with a consumer electronic device owned by a user is identified, a diagnostic procedure is provided to control the diagnosis of the potentially faulty consumer electronic device by a testing consumer electronic device. The testing consumer electronic device is a local device owned by the user that is operable to diagnose problems associated with the potentially faulty consumer electronic device. In one embodiment, the testing consumer electronic device and the potentially faulty consumer electronic device are part of a home network enabling their communication during the diagnosis. In another embodiment, the testing consumer electronic device and the potentially faulty consumer electronic device can communicate only during the diagnosis using a special purpose connectivity means. In yet another embodiment, the testing consumer device and the potentially faulty consumer electronic device can communicate using their user interfaces.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: November 30, 2004
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Joseph Dara-Abrams, Klaus Hofrichter, Ravi Gauba, David G. Gaxiola, Jun Ouyang
  • Patent number: 6820027
    Abstract: A method of testing an electrical device to determine a range of combinations of values of N variable operating parameters for which the device functions properly is described. In one embodiment, The method comprises defining a plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N variable operating parameters, selecting an operating point within the plot region, testing the device using the combination of values of the N variable operating parameters corresponding to the selected operating point, and if the device functions in a first manner at the selected operating point, adding all operating points of the plot region having a first relationship with respect to the selected operating point to a list of operating points to be tested.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: November 16, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Christopher Todd Weller
  • Patent number: 6795782
    Abstract: A storage battery includes a battery housing and a plurality of electrochemical cells in the battery housing electrically connected to terminals of the battery. A battery test module is mounted to the battery housing and electrically coupled to the terminals through Kelvin connections. A display or other output is configured to output battery condition information from the battery test module.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: September 21, 2004
    Assignee: Midtronics, Inc.
    Inventors: Kevin I. Bertness, Jamey L. Butteris, Michael J. Fritsch
  • Patent number: 6792396
    Abstract: An interface device receives data from a plurality of sensors and transmits the data over a communication network to one or more of a plurality of monitors. The interface device is capable of operating in both a peripheral mode of operation and a stand-alone mode of operation for the plurality of monitors. In another embodiment, a monitor is connected to a plurality of interface devices by way of a communication network. A separate visible physical communication link or other identification link is used to visually identify which of the interface devices is serving as a peripheral device for the monitor.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: September 14, 2004
    Assignee: GE Medical Systems Information Technologies, Inc.
    Inventors: Allan G. Inda, Daniel J. Nowicki, Michael J. Horvath, Patrick A. Van Ryzin
  • Patent number: 6792374
    Abstract: The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: William E. Corr
  • Patent number: 6789032
    Abstract: A statistical method is described for reliability selection of dies on semiconductor wafers using critical wafer yield parameters. This is combined with other data from the wafer or module level reliability screens (such as voltage screen or burn-in) to obtain the relative latent defect density. Finally the modeled results are compared with actual results to demonstrate confidence in the model.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Tange N. Barbour, Thomas S. Barnett, Matthew S. Grady, Kathleen G. Purdy
  • Patent number: 6782331
    Abstract: A system that includes a graphical user interface (GUI) connected to an input/output device of a computer system and one or more test instruments producing a set of electrical signals. The system also includes a probe card that has a multiple probe needles used for measuring electronic characteristics of each of the devices on a semiconductor wafer. Each device has cells. Each cell has a set of bond pads. The system also has a matrix switch and an interface conduit electrically connecting the one or more test instruments, the computer, the probe card, and the matrix switch together. The semiconductor wafer is moved so that the probe needles measure the electrical characteristics of each cell for each device selected for testing.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: August 24, 2004
    Assignee: Infineon Technologies AG
    Inventor: Kamel Ayadi
  • Patent number: 6778934
    Abstract: When measurement information of a model is entered, a condition file is automatically selected corresponding to a measurement category selected for each measured object displayed on an initialization screen. Next, when test selection items are selected, the selection results are retained in memory. The measurement category of the measured object can be selected and set on a menu screen and condition value change can be set using a test condition registration screen, etc. Thus, the test data is set and changed and the measurement state and the measurement result are displayed by operating the screens.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: August 17, 2004
    Assignee: Clarion Co., Ltd.
    Inventors: Hideki Hori, Yoshishige Kakinuma, Toru Katsui
  • Patent number: 6768961
    Abstract: A system and method for analyzing error information from a semiconductor fabrication process. The system receives wafer map data describing a plurality of failing chips on a particular semiconductor wafer. The system utilizes the wafer map data to classify each of the failing chips into one of several error categories, such systematic errors, repeated or reticle errors, and random errors. The system further partitions the systematic errors into spatial clusters, which may be compared against a known library of spatial error patterns for identifying the origins of the systematic errors.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: July 27, 2004
    Assignee: Yield Dyamics, Inc.
    Inventors: Jonathan B. Buckheit, Weidong Wang
  • Publication number: 20040117143
    Abstract: A system comprising a plurality of digital storage oscilloscopes (DSOs) in which each DSO acquires a common signal under test (SUT) according to respective clock signals having common frequency parameters and respective phase parameters such that a plurality of acquisition records may be interleaved to produce a higher effective resolution acquisition record.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 17, 2004
    Inventors: Que Thuy Tran, David L. Kelly, Douglas A. Blegen
  • Patent number: 6751570
    Abstract: A system, designed to interact electronically with an RF device, is able to test many types of RF devices and is operable to apply a variety of test inputs to an RF device. The RF device, located within a nest inside an RF enclosure, interacts with the system via a nest electronics component. The nest electronics component, located within the RF enclosure and coupled to a nest interface component and a fixture interface component, supplies power and input test signals to the RF device. The nest electronics component may be configured to interact with a particular RF device, which allows the RF enclosure to used with different types of RF devices. The arrangement of these components allows control and measurement of the RF device to be located as close to it as possible and also allows functionality not required within the RF enclosure to be externally located.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: June 15, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Bryan D. Boswell, Richard E. Warren, Gregory E. Brandes, Terrence Jones
  • Patent number: 6745145
    Abstract: Electrical components and associated processes for enhancing automated test of a system by permitting automated generation and application (injection) of real-world stimuli applied to the system under test without the need for manual intervention. Electrical components of the present invention intercede in the exchange of signals and power over various signaling paths within a system under test. Under programmable control by methods of the invention, the electrical components of the present invention may simulate any desired real-world stimulus on any signal path associated with the system under test. Automated test procedures associated with the electrical components may then automate all phases of a test procedure including setup of the test environment, application of real-world stimuli, verification of operation of the system under test and cleanup and recovery following performance of the automated test sequence.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: June 1, 2004
    Assignee: LSI Logic Corporation
    Inventors: John M. Lara, Robin Huber
  • Patent number: 6744259
    Abstract: A safety compliance test instrument includes a display capable of displaying prompts, a menu display program, software for displaying a plurality of instrument verification menus, prompts, and messages concerning results of the verification tests, and software for enabling or preventing safety compliance tests from being performed depending on results of the verification. The safety compliance instrument includes at least two different safety compliance tests involving different connections to a device under test. The tests may be selected from the group consisting of a continuity test, a ground test, a dielectric withstand test, and an insulation resistance test, and more specifically from the group consisting of a continuity test, a ground bond test, AC and DC dielectric withstand tests, and an insulation test.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: June 1, 2004
    Assignee: Associated Research, Inc.
    Inventor: Roger A. Bald
  • Patent number: 6732053
    Abstract: In one aspect of the present invention, an apparatus is provided for testing a plurality of devices. The apparatus, in one embodiment, comprises a controller, a device identifier capable of identifying each one of a plurality of devices as one of a plurality of device types, and a plurality of test heads. Each test head is capable of testing each one of the devices independently of the rest of the plurality of test heads responsive to the identification of each device by the device identifier and under the control of the controller. In a second aspect of the invention, a method is provided for testing a plurality of devices.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventor: Daniel C. Aragona
  • Patent number: 6704691
    Abstract: A method and system for in-line monitoring process performance during wafer fabrication. First signals generated by a fabrication tool are collected and filtered to exclude abnormal signals while a model wafer is processed. The filtered first signals are regulated and normalized to generate model wafer data. After the fabrication process is completed, the model wafer is measured to generate a measured value representing the process quality thereof. The model wafer data and the measured value of the model wafer are used to build a correlation model by a correlation unit. Second signals generated by the fabrication tool are collected when a run wafer is processed, and then filtered to exclude abnormal signals. The filtered second signals are regulated and normalized to generate run wafer data. A predicted value representing the process quality of the run wafer is generated by inputting the run wafer data into the correlation model.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: March 9, 2004
    Assignee: Promos Technologies, Inc.
    Inventor: Hung-Wen Chiou
  • Patent number: 6697750
    Abstract: A method and apparatus for performing parallel asynchronous testing of a plurality of optical modules utilizes state machines that may be implemented in a common controller. Desired optical tests are selected by an operator. The invention determines if a testing process or instrument required for the selected optical tests is available. A COM port may also be locked for each of the selected optical tests from among a plurality of COM ports to prevent interference between different tests. By reserving resources such as COM ports and testing instruments in this fashion the invention may asynchronously initiate execution of the selected optical tests. If a resource such as a COM port, testing process or instrument is not currently available, the test is place in COM port and testing queues to await availability of that resource. Once a test is completed, the resource is unlocked so that one of the state machines may asynchronously initiate another test.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: February 24, 2004
    Assignee: Ciena Corporation
    Inventors: Bryan Coin, Michael J. Ransford, David A. Schwarten, Chao Jiang, Iqbal M. Dar, Andrei Csipkes
  • Publication number: 20040024557
    Abstract: A control method for an automatic integrated circuit full testing system. A control device is utilized to control the testing process of the automatic integrated circuit full testing system. The steps for controlling the control device include driving an automatic transport device to fetch test integrated circuits from an integrated circuit supply rack to various testing computer stations. An automatic plug/unplug tool is driven so that each integrated circuit is plugged into the connector of a corresponding testing computer. All the testing computers are triggered to carry out respective preset testing programs. An image sensor is driven to monitor the an output image of the testing computers so that any abnormality in the integrated circuits can be determined. Thereafter, the automatic plug/unplug tool is driven to unload the tested integrated circuit from the testing computer.
    Type: Application
    Filed: February 18, 2003
    Publication date: February 5, 2004
    Inventors: Ming-Ren Chi, Peng-Chia Kuo