Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes timestamp logic capable of providing clock cycle resolution of data entries using a relatively small number of bits. The timestamp logic includes a counter that is reset each time a store operation occurs. The counter counts the number of clock cycles since the previous store operation, and if enabled by the user, provides a binary signal to the memory that indicates the number of clock cycles since the previous store operation, which the memory stores with the state data. If the counter overflows before a store operation is requested, the timestamp logic may force a store operation so that the time between stores can be determined.

Abstract: A more time-efficient and area-efficient approach is provided to synchronize the transfer of data into programmable logic resources. A programmable logic resource core clock and a reset signal are routed to a reset register that controls the reset of a dynamic phase alignment circuit and a data realigner. The dynamic phase alignment circuit includes a phase-locked loop circuit, a J counter, and a deserializer. When the output signal of the reset register transitions from logic 1 to logic 0, the J counter begins to count and sets an enable signal accordingly. The enable signal, which controls the output of synchronized parallel data from the deserializer, is therefore phase associated with the programmable logic resource core clock. The synchronized parallel data is input to a data realigner which outputs the data based on the programmable logic resource core clock for input to the programmable logic resource core circuitry.

Abstract: In one representative embodiment, multiple ensembles of samples of a periodic or cylcostationary signal are processed in a time aligned manner. The sampling rate of the processing system is adjusted so that an integer number of sampling intervals equals the period of the signal. A cyclic counter is programmed to reset according to the integer number. Also, the cyclic counter may be initialized according to an external trigger. During operation, the cyclic counter is incremented when each sample is received. Continuous operation of the cyclic counter with the capturing of samples enables precise time alignment between ensembles of samples. Specifically, the beginning of a discrete ensemble is identified by a reset of the cyclic counter. Because each ensemble is time aligned, further processing (e.g., coherent averaging) may occur without post-processing to time-shift each sample to achieve the time alignment.

Abstract: A time varying electrical excitation(s) is applied to a system containing biologic and/or non-biologic elements, whereupon the time-varying electrochemical or electrical response is detected and analyzed. For biologic specimens, the presence, activity, concentration or relative quantity, and certain inherent characteristics of certain target substances (hereinafter referred to as “target analytes”) within, or comprising, the specimen of interest may be determined by measuring either the current response induced by a voltage-mode excitation, or the voltage response induced by a current-mode excitation. Labeling or marker techniques may be employed, whereby electrochemically active auxiliary molecules are attached to the substance to be analyzed, in order to facilitate or enhance the electrochemical or electrical response.

Abstract: A frequency measuring device can measure the frequency of a noisy power system at high speed. The system voltage is measured at timings obtained by equally dividing one reference-wave period. Voltage vectors are calculated which have tip ends, each voltage vector consisting of a real part of a first measured voltage and an imaginary part of another voltage measured at timing 90 degrees before the first measured voltage. The length of a chord connecting tip ends of adjacent voltage vectors is calculated. A voltage root-mean-square value is calculated from voltages measured between two timings spaced from each other by the one reference-wave period. Chord lengths obtained between two timings spaced from each other by the one reference-wave period are summed. Based on the total of the chord lengths and the voltage root-mean-square value, there is calculated a phase angle between two adjacent voltage vectors, from which the system frequency is calculated.

Abstract: A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector having an output and a return which are coupled together by the device when the device requires power. The detector includes a word generator for generating test pulses for transmission to the device via the detector output, and a comparator for comparing the detector output with the detector return. The power detection station has a wide variety of applications, including by way of example, a switch or hub.

Abstract: Data on a period longer than the test cycle period concerned in a high-speed pattern test is preset in a period data storage 41, then a flag 1 is set in a cycle stretch setting part 16E of a pattern-generation memory 16 at an address position where to execute cycle stretch, then a high-speed pattern test signal is applied, and when the flag 1 is read out by an address from an address counter 14, a switching part 42 is controlled to switch data read out of a test cycle memory 34 to data set in a setting register 44 for application to a test cycle generator 36, thereby lengthening the test cycle period.

Abstract: A method and apparatus for real-time derivation of precise digital clock edges and synchronous logic samples from a digital signal having a clock channel and at least one data channel acquires a plurality of temporally offset analog samples during each of a sequence of sample periods and from consecutive samples where there is a logic level transition estimates an edge time. From the edge times for the clock channel an offset is added and applied to the at least one data channel to determine the synchronous logic samples for the data channel at each offset clock edge time.

Abstract: A method for adjusting a duration of an internal timing signal in an integrated circuit with a value close to a typical value of the duration may include activating the internal timing signal in the integrated circuit and sequentially sending calibration values to an input of the integrated circuit. The expiration of the internal timing signal may determine the last calibration value received or being received, and the calibration data may be applied to a device for adjusting the duration of the internal timing signal.

Abstract: A circuit and method to automatically identify and manipulate a pulse in each of a sequence of clocking signals for an integrated circuit includes a clock manipulation circuit to manipulation the identified pulse including to shrink or otherwise alter the identified pulse; and a pulse identification circuit to automatically and algorithmically identify each pulse to be shrunk.

Abstract: A hybrid tester architecture for testing a plurality of semiconductor devices in parallel is disclosed. The hybrid tester architecture includes per-pin formatting circuitry having data input circuitry and clock input circuitry and shared timing circuitry coupled to the clock input circuitry. The shared timing circuitry generates programmed timing signals. Per-pin data circuitry couples to the data input circuitry and generates drive data and expected data values associated with each individual device pin. The per-pin formatting circuitry responds to the programmed timing signals to produce tester waveforms in accordance with the per-pin data.

Abstract: The present invention is directed to a method and system for measuring bus frequency. A system suitable for determining bus frequency may include a bus device and a processor. The bus device is suitable for performing an operation and the processor is communicatively coupled to the bus device utilizing a bus. The processor is capable of starting a timer, initiating the bus device to perform a number of operations, receiving an indication that the bus device completed the number of operations, stopping the timer when the indication is received. A bus clock frequency is computed based upon time taken to complete the number of operations as indicated by the timer and the number of operations performed by the bus device.

Abstract: Described are methods for accurately measuring the skew of clock distribution networks on programmable logic devices. Clock distribution networks are modeled using a sequence of oscillators formed on the device using configurable logic. Each oscillator includes a portion of the network, and consequently oscillates at a frequency that depends on the signal propagation delay associated with the included portion of the network. The various oscillator configurations are defined mathematically as the sum of a series of delays, with the period of each oscillator representing the sum. The respective equations of the oscillators are combined to solve for the delay contribution of the included portion of the clock network. The delay associated with the included portion of the clock network can be combined with similar measurements for other portions of the clock network to more completely describe the network.

Abstract: An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path.

Abstract: The present invention is to a measured data synchronization system having measuring instruments for measuring objects and outputting measured data, and a data processing apparatus connected to the measuring instruments via a signal line and which acquires and processes the measured data. The system relates to a measured data synchronization system which performs data processing using measured data for which synchronization among measuring instruments is ensured. The measuring instruments are given an input of reference times from the data processing apparatus and append these reference times to the measured data before outputting the data. The data processing apparatus outputs the reference times at prescribed intervals to each of the measuring instruments; receives an input of the measured data appended with the reference times from each of the measuring instruments; and performs data processing using measured data appended with desired reference times.

Abstract: A timing control device and method for minimizing timing uncertainties due to skew and jitter, wherein a device for the compensation of timing errors in multiple channel electronic devices comprises at least one register having a plurality of channels comprising: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers. For each register, a corresponding feedback loop is associated for the relative alignment of the register's timing. The feedback loop comprises a device for detecting a deviation from a predetermined level of probability of reading by the register of a desired symbol on a boundary of two reference channel symbols in a sequence, and a set of delay devices which use the detected values of probability to generate a feedback signal.

Abstract: A test mode control unit of an integrated circuit receives and decodes a test mode signal to perform testing of the integrated circuit. Logical AND operations are performed on the decoded test control signal and a test signal. The test signal allows the integrated circuit to toggle between test and non-test modes of operation. In one instance, the toggling allows real time debugging of the integrated circuit when test data outputs of internal signals or states are multiplexed onto a data bus.

Abstract: A method and systems to evaluate the propagation delay within a semiconductor chip (305) that is embedded in an electronic system without requiring measurement apparatus and specific electrical contacts is disclosed. Since most of electronic systems use a microprocessor, the basic principle of the invention consists in using the microprocessor capabilities to measure the propagation delay of a chip embedded in such an electronic system. Thus, according to the invention, the microprocessor transmits an instruction to the semiconductor chip that performs propagation delay evaluation and then read the result in a dedicated memory register (415) of the chip. As a consequence, the chip does not require dedicated pins and measurement apparatus. In order to measure the propagation delay, the chip comprise a logic path (400) wherein propagation delay is created, then a rising edge detector (405) is used to analyze logic path signals, A counter (410) based on a system clock is used to measure propagation delay.

Abstract: Systems for performing time domain measurements of a device under test (DUT) are provided. One such system includes a normalization system that receives information corresponding to a model of a test system used for providing differential input signals to a DUT, receives information corresponding to first and second differential input signals provided to the DUT, receives information corresponding to first and second reflected waveforms corresponding to the DUT response to the first and second differential input signals, and computes first and second normalized waveforms using at least a first inverse transfer function of the test system, the first and second normalized waveforms including fewer test system error components than the first and second reflected waveforms, respectively. Methods, computer-readable media and other systems also are provided.

Abstract: A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit 2 in burst mode by detecting and measuring an output 15 of the self-timed sequential circuit 2.

Abstract: The technology and economics of system testing have evolved to the point where a radical change in methodology is needed for effective functional testing of systems at clock rates of 1 GHz and higher. Rather than providing a test fixture to interface between the system under test and an external tester, it is preferable to provide critical testing functions within each electronic system in the form of one or more special-purpose test chips. An architecture is proposed that supports full-speed testing with improved noise margins, and also efficient methods for learning correct system behavior and generating the test vectors. The test program is preferably written using the same programming language as used for the system application.

Abstract: A system for investigating a sample, the system comprising a detector having non-linear current voltage characteristics and being configured to mix two radiation signals having frequencies in the range from 25 GHz to 100 THz, one of the signals being a local oscillator signal and the other signal being a sample signal carrying information about the sample being investigated, the system further comprising a quantum cascade laser for providing at least the local oscillator signal.

Abstract: A technique for determining performance characteristics of electronic systems is disclosed. In one exemplary embodiment, the technique may be realized as a method for determining performance characteristics of electronic systems. The method includes the steps of measuring a first response on a transmission medium from a falling edge transmitted on the transmission medium, and measuring a second response on the transmission medium from a rising edge transmitted on the transmission medium. The method also includes the step of determining worst case bit patterns for transmission on the transmission medium based upon the first response and the second response.

Abstract: A method is provided for testing an integrated circuit in an automatic test environment. According to the method, the automatic test environment is set up, and there is performed a repetitive measurement of at least one electrical quantity representative of an integrated circuit response to a set of prescribed integrated circuit test conditions. The automatic test environment is reset, and the integrated circuit test conditions are changed in synchrony with a synchronization signal having a prescribed periodicity, so that all of the measurements are allotted a time slot of the same length. Also provided is an automatic test equipment apparatus that includes a synchronization generator for supplying a synchronization signal having a prescribed periodicity to means for putting the integrated circuit in a set test condition. The means changes the set test condition in synchrony with the synchronization signal, so that all of the measurements are allotted a time slot of the same length.

Abstract: A method for time reference compensation in a power metering system, the method comprising monitoring a time-dependent characteristic of incoming AC power over a predetermined local time interval, comparing the monitored characteristic over the predetermined local time interval with the expected value of the characteristic based upon the nominal frequency of the AC power, and calculating a correction to one or more of local real-time and time-based measurements of the power metering system, based on the comparing.

Abstract: The inventive method and apparatus include sensory devices that invariantly represent stimuli in the presence of processes that cause systematic sensor state transformations. Such processes include: 1) alterations of the device's detector, 2) changes in the observational environment external to the sensory device and the stimuli, and 3) certain modifications of the presentation of the stimuli themselves. A specific embodiment of the present invention is an intelligent sensory device having a “front end” comprised of such a representation “engine”. The detectors of such a sensory device need not be recalibrated, and its pattern analysis module need not be retrained, in order to account for the presence of the above-mentioned transformative processes. Another embodiment of the present invention is a communications system that encodes messages as representations of signals.

Abstract: Pattern detection methods and arrangements are provided for monitoring a Fibre Channel, a Gigabit Ethernet, or other like data stream for programmable trigger patterns. Upon detecting a trigger pattern, the pattern detection methods and arrangements will assert an output. The output is useful for triggering oscilloscopes to be able to properly display the signal and more importantly, for arming time interval analyzers and other like test instruments. The pattern detection methods and arrangements are capable of dealing with elasticity in the data transmission channel. For example, the trigger pattern can be uniquely configured to a frame header or frame contents and the test instrument can be set to limit its sampling to within the frame bounds. In this manner all of the variability of fill transmission words appearing or disappearing essentially becomes transparent to the test instrument.

Abstract: A method of testing a circuit having an interface which includes data and clock information where phase jitter is introduced into the clock that produces the clock information. The clock is cycled by increasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift advance in the clock. The clock is also cycled by decreasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift delay in the clock. The circuit under test is caused to sample the data using a clock derived from the clock information. The sampled data is then compared with reference data to determine the error rate.

Abstract: The compilation of a high-level software-based description of an algorithm into efficient digital hardware implementation(s) is addressed. This is done through the definition of new semantics for software constructs with respect to hardware implementations. This approach allows a designer to work at a high level of abstraction, while the semantic model can be used to infer the resulting hardware implementation. These semantics are interpreted through the use of a compilation tool that analyzes the software description to generate a control and data flow graph. This graph is then the intermediate format used for optimizations, transformations and annotations. The resulting graph is then translated to either a register transfer level or a netlist-level description of the hardware implementation.

Abstract: A “Streaming Distributed Oscilloscope” (SDO) architecture comprises at least one channel including a preamplifier module, a Digitizer Module, and an Acquisition Memory Module. An SDO couples all acquired samples of a waveform being monitored to all of its processing boards. Because multiple processor boards can access all of the sample data, an SDO can perform measurements on substantially all samples of a continuous data stream without dead time. An SDO is readily expandable in terms of memory length by simply adding more memory boards, and can be reconfigured by a user by virtue of its object-oriented architecture. An SDO waveform is defined by a trigger source and an acquisition memory. An SDO is capable of acquiring multiple waveforms based upon different triggers from the same data stream in the same channel. An SDO timebase for a given channel is defined by a decimator followed by an acquisition memory. Multiple timebases can co-exist in the same SDO channel.

Abstract: A method and apparatus to calibrate an LED matrix display such that a driver will provide a proper precharge voltage to LED elements within the display during a scan period. A current is driven through a calibration element, and a voltage reflecting the steady-state element voltage is measured and stored as a calibration value. A processor controls whether to precharge during the calibration cycle, and determines when the calibration cycle is completed. During subsequent normal scans, a driver applies a voltage based on the stored calibration value to rapidly precharge parasitic capacitance associated with a display element to a proper value, and also drives a selected current through the device.

Abstract: A waveform generating apparatus capable of outputting a desired waveform is provided. Among delay data is selected a set pulse generating delay data depending on test logical data and waveform mode information. The delay data, a skew adjusting delay data, and a fraction data in each test cycle are computed to obtain an integer delay data and a fraction delay data, which are supplied to a counter delay circuit. From the counter delay circuit are outputted a set pulse generating effective flag for delaying a test period timing by a delay time corresponding to the integer delay data, and a fraction delay data related thereto. The effective flag is delayed based on the related fraction delay data to obtain a set pulse. Similarly with the set pulse, a reset pulse is obtained, thereby to set/reset an S-R flip-flop to output a desired waveform.

Abstract: A method to automate techniques for using delay correlation effects to optimize the design of digital circuits, including a graphical method of data-entry and an optimized calculation scheme. It is used in conjunction with, or is part of, a computer program which performs timing analysis of digital circuits. The method calculates the time difference between two user-input timing paths in a circuit which include delay ranges for each gate in the paths along with correlation factors between any pair of gates. The method checks the user-input to determine an optimal calculation procedure. If none exists, it resorts to a calculation based on a sequential search of many possible timing states.

Abstract: A trigger node for a measurement and control system which enables relatively precise timing in the application of stimuli and/or measurement of responses without specialized adaptation of analog signaling to the measurement and control system. A trigger node according to the present teachings includes a synchronized clock that maintains a time using a synchronization scheme that provides the timing precision needed for the application of stimuli and/or measurement of responses. A trigger node according to the present teachings further includes mechanisms for asserting a trigger signal when the time from its synchronized clock matches a trigger time associated with the trigger signal. Multiple trigger nodes may be used to coordinate the timing of multiple measurement and control devices by appropriately setting the trigger times in the trigger nodes.

Abstract: Pattern detection methods and arrangements are provided for monitoring a Fibre Channel, a Gigabit Ethernet, or other like data stream for programmable trigger patterns. Upon detecting a trigger pattern, the pattern detection methods and arrangements will assert an output. The output is useful for triggering oscilloscopes to be able to properly display the signal and more importantly, for arming time interval analyzers and other like test instruments. The pattern detection methods and arrangements are capable of dealing with elasticity in the data transmission channel. For example, the trigger pattern can be uniquely configured to a frame header or frame contents and the test instrument can be set to limit its sampling to within the frame bounds. In this manner all of the variability of fill transmission words appearing or disappearing essentially becomes transparent to the test instrument.

Abstract: In accordance with one embodiment, a method for scheduling the servicing of job requests in a point-to-point communication system having a central server providing job requests to a plurality of local channel servers. In a first step, the method receives a new job request at a central server. A performance of each local channel server is measured, and the job request is dispatched to one of the local channel servers for servicing thereby dependent upon the performance of each of the local channel servers. In one embodiment, the job request is dispatched to the local channel servers having the lowest current average flow time.

Abstract: A system uses an event based equivalent time sampling method for ascertaining a value of each bit of a data frame repeated in a digital signal of indeterminate phase. The system measures time intervals between rising edges of the digital signal and a reference time and between falling edges of the digital and that reference time in response to pulses of a periodic arming signal. The measured time intervals are then normalized to equivalent time intervals and those intervals analyzed to determine values of each bit of the data frame.

Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells.

Abstract: Systems and methods for testing digital components in the multiple gigahertz range using an automatic test system. A digital component-under-test is connected to the automatic test system having a driver module and a receiver module coupled to the automatic test system. The driver module generates high-speed signals that are provided to the digital component-under-test. The receiver module samples the high speed output data from the digital component-under-test and transmits sampled data to the automatic test equipment at a data rate supported by the automatic test equipment.

Abstract: An adaptive delay learning algorithm is presented that reduces the amount of delay before making test measurements in an automated test that requires a delay of any type to be completed before a measurement is made in order to remove the possibility that a tester component lying in the measurement path has not achieved a ready state. In the execution of an automated test, a current delay time is set to an initial delay value. Test execution does not begin until the current delay time elapses. If, upon execution, the test fails, the current delay time is set to a different delay time, and the test is reexecuted only after the updated current delay time has elapsed.

Abstract: The invention accurately determines propagation delay for a sawtooth pattern. Through measurement, the actual delays added per bend in the sawtooth pattern are determined and the values are then used in a CAD tool. The invention can add a known amount of propagation delay to a wire length by routing net wires close together without using a large amount of board space.

Abstract: A method for presenting information and a digital storage oscilloscope are disclosed in which primary measurements of a signal are performed and displayed. Parameters are also derived for the signal based upon the primary measurement data. These derived parameters are then also displayed as a function of time on the display, preferably with a common time axis. This enables the oscilloscope operator to correlate features found by reference to the derived parameters directly to the primary measurements of the signal. Moreover, since the data from the primary measurements are stored in the oscilloscope, multi parameter calculation and parameter recalculation can be performed.

Abstract: A method for presenting information and a digital storage oscilloscope are disclosed in which primary measurements of a signal are performed and displayed. Parameters are also derived for the signal based upon the primary measurement data. These derived parameters are then also displayed as a function of time on the display, preferably with a common time axis. This enables the oscilloscope operator to correlate features found by reference to the derived parameters directly to the primary measurements of the signal. Moreover, since the data from the primary measurements are stored in the oscilloscope, multi parameter calculation and parameter recalculation can be performed.

Abstract: A method and program for producing a test pattern of a semiconductor device includes using a result of timing verification of the semiconductor device to select an unverified path in the semiconductor device. A signal line on the unverified path is selected and a dummy element that always outputs an inconstant value is virtually inserted into the signal line. The test pattern for the semiconductor device with the virtually inserted dummy element is then produced.

Abstract: A variable color digital measuring instrument sequentially exhibits measured values in a color in accordance with the relation of the present measured value to a past measured value. A memory, controlled by a timer, is provided for storing data representing the past measured value. A comparator compares the present measured value with the data stored in the memory and develops a comparison signal accordingly, which is then used to control the color of the presently exhibited measured value.

Abstract: An electronic system such as a processor or computer system includes circuitry that supports a plurality of clock modes. The clock modes may be used for, for example, testing for critical paths. The clock modes include a variety of clock signal variations that may be utilized such as cycle stretch clock mode, pulse or delay fault mode, and stop mode which provide substantial flexibility in support of a multitude of tests. In one embodiment, a processor of an electronic system includes test clock mode circuitry to support and utilize test clock modes without dependence on an external bypass clock signal operating at processor operational frequencies. Furthermore, the processor implements the test clock modes at full processor operational frequencies. Additionally, a phase-locked loop is utilized to synchronize test mode clock signals with a reference clock signal to, for example, facilitate realistic operational conditions and acquisition of accurate test results.

Abstract: A method for performing a test and controlling the test mode of an electric device. The method reduces the amount of time and labor expended during fabrication, and accordingly enhances productivity by detecting time information from a timer (a clock generator, or a variable clock generator) and multiplying the detected time information by a predetermined value, and controlling the driving time of the device during a test operation in response to the multiplied time value.

Abstract: A test system testing whether test objects, such as semiconductor parts, are good or bad collects operation status data to increase the operation rate of the tester testing the test objects and the handlers handling the test objects. The relay device to which the handlers and the tester are connected, collect operation status data from them, makes a count of test objects, and sends the data and the count to the server device and the storage device. Based on the collected data and count, the server device calculates the operation time of the handlers and the tester necessary or testing a unit of test objects. The next time the test is made, the handler references the operation time to search for the optimum combination of the handlers and the tester.

Abstract: Automatic test equipment with programmable timing generators to generate digital signals and analog signals. The digital timing generator can be programmed to generate timing signals with a resolution finer than that of the master clock of the timing generator. Extremely fine resolution is achieved by specifying the numerator and denominator of a fractional portion of a period. A similar arrangement is used to allow fine frequency resolution for the analog timing generator. The fine resolution achievable with the timing generators allows the digital timing generator to be synchronized to the analog timing generator.