Abstract: In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock generator. The first clock generator is coupled to receive an input clock to the integrated circuit and is configured to generate the first clock. The control unit is also coupled to receive a trigger input to the integrated circuit. During a test of the integrated circuit, the control unit is configured to cause the first clock generator to generate the first clock at a first clock frequency, The control unit is configured to cause the first clock generator to generate the first clock at a second frequency greater than the first clock frequency for at least one clock cycle responsive to an assertion of the trigger input.

Abstract: A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start pattern within the serial data stream, such as a packet header, is detected to generate an enable signal. A stop event, such as a packet trailer, a specified digital event, a time interval or the like, is identified to generate a disable signal. The enable and disable signals are combined to produce a qualification signal that allows a trigger circuit to trigger on a specified anomaly within the portion of the serial data stream defined by the qualification signal.

Abstract: This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

Abstract: A detection apparatus is provided. The detection apparatus includes; a multi-strobe generating section that generates a plurality of strobe signals with phases different from one another; a plurality of acquiring sections each of which acquires a signal value of a signal under measurement at a timing of each of the plurality of strobe signals; a plurality of changing point detecting sections that detect a fact that there is a changing point of the signal under measurement between two adjacent strobe signals when two signal values which are acquired in accordance with the two adjacent strobe signals are different from one another; a mask setting section that sets the changing point detecting section to be enabled among the plurality of changing point detecting sections; and a changing timing output section that outputs a changing timing of the signal under measurement based on an output of the enabled changing point detecting section.

Abstract: According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.

Abstract: A technique for performing frequency margin testing of communications system circuit boards incorporates a frequency agile clock source on a communications system circuit board. The clock source may be programmed to operate the circuit board at a nominal operating frequency and at frequencies suitable to characterize actual and/or apparent frequency tolerances of the circuit board. The technique maintains transmission line integrity of the on-board clock.

Abstract: A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit generates a core clock signal enabling full speed operation of core circuitry of the IC during test mode. The pad clock circuit generates a preliminary clock signal suitable for normal operation, and the test clock circuit generates a test clock signal suitable for operating the I/O interface logic during the test mode. The select circuit selects, based on the test signal, between the test clock signal and the preliminary clock signal as the pad clock signal. The tester provides the bus clock signal and indicates the test mode to the DUT via the I/O interface logic.

Abstract: A programmable system for testing relays and controlling systems is provided. In one embodiment the present disclosure provides a programmable device capable of, for example, testing relays. The device includes a signal generator for generating signals to test relays. The device includes a memory location, and a first program stored in the memory location. The first program supports relay testing. The device includes a versioned program to support relay testing, and a processor in communication with the signal generator and the memory location. The device also includes a routine that is operable by the processor to install a versioned program in the memory location replacing the first program.

Abstract: Overclocking parameters in a graphics system are automatically set. In one embodiment, in response to a user request, overclocking parameters for different sets of overclocking parameters are tested using a graphical stress test to select optimum overclocking parameters.

Abstract: There is provided a test apparatus that decides the good or bad of an electronic device adopting source synchronous clocking with high precision.

Abstract: A method and system for generating test pulses to test electronic elements are disclosed. After determining a transmission clock, which is smaller than a test clock, and a serial of predetermined pulses, the serial of data bits corresponding to the serial of predetermined pulses can be generated. Then the serial of data bits can be transformed into a serial data stream for transmission. By transmitting the serial data stream according to the transmission clock, the serial of predetermined pulses corresponding to the test clock can be generated.

Abstract: A system and method of generating a test clock signal for scan testing of a main circuit in a semiconductor device includes receiving an external clock signal and a control signal and generating a gated clock signal by gating an internal clock signal based on the control signal. The internal clock signal has a frequency higher than a frequency of the external clock signal. One of the external clock signal and the gated clock signal is selectively output based on the control signal.

Abstract: A test apparatus that tests a device under test is provided. The test apparatus includes: a control processor that executes a test program to test the device under test; a test unit connected to the device under test that tests the device under test according to an instruction by the control processor; and a relay section connected to the control processor and the test unit that relays a control instruction transmitted from the control processor to the test unit. The relay section includes: a buffer section that buffers the control instruction to be written to the address assigned from the control processor to the test unit; a timing storage section that stores a timing at which the control instruction received from the control processor should be transmitted to the test unit; and a buffer control unit that transmits the control instruction buffered in the buffer section to the test unit in response to that the timing stored in the timing storage section comes.

Abstract: A method comprises a receiving system computing a time difference between a current time and a time that a last sync message was received from a sending system. If such a time difference meets or exceeds a first threshold, the method further comprises generating an alert (e.g., visual alert, audible alert, etc.).

Abstract: An integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven by a first clock and configured to supply a zero-delay value of the first clock to a first flip-flop. The circuitry also includes a second delay element having a selectable delay, the second delay element configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second flip-flop. A third delay element has a selectable delay and is coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output of the second flip-flop is coupled to an input of the third flip-flop.

Abstract: A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subsystems. The subsystems may be comprised in the data acquisition device or may be external to the data acquisition device. The real-time monitoring circuit may receive a plurality of timing signals from the plurality of subsystems and may select a control loop timing signal out of the plurality of timing signals. The real-time monitoring circuit may determine whether the operations of the control loop are performed within a particular period of time by monitoring the control loop timing signal and communicating with the processing unit. In response to an error notification, the processing unit may take appropriate action, such as shutting down the system and/or reporting an error or warning.

Abstract: A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test, BIST Test, Functional) as contrasted with doing STA with only one worst-case SDF for all modes. The multiple SDFs account for the impact of dynamic voltage drops on delays in addition to static IR drops.

Abstract: A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators.

Abstract: According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.

Abstract: An application programming interface (API) for synchronizing multiple devices in a system. The API includes a plurality of functions invocable in a program to synchronize multiple devices, where each function is executable to perform a respective functionality related to synchronizing the devices, and at least one of the functions is executable to access a plurality of instrument drivers corresponding respectively to the plurality of devices to synchronize the plurality of devices. In synchronizing the plurality of devices, the functions determine a trigger clock signal for each of the plurality of devices, and synchronize the plurality of devices based on the determined trigger clock signals. The API also includes a plurality of attributes corresponding to respective properties of the system related to synchronization of the devices, including one or more trigger attributes and/or one or more trigger clock attributes for each of the devices. The API representations may be text-based and/or graphical.

Abstract: A method and system for performing a bit error rate test on a device with substantial duty cycle output distortion are described herein.

Abstract: Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.

Abstract: A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a multi-cycle path detector determines whether all the paths in the path set are multi-cycle paths. When the path set is a multi-cycle path, it is added to a timing exception path list that is output by an output unit.

Abstract: The present invention provides for a method for examining high-frequency clock-masking signal patterns at a reduced frequency. A first mode of a first shift register is selected. A plurality of bits is loaded on the first shift register at a first frequency. A second mode of the first shift register is selected. A first mode of a second shift register is selected. The plurality of bits is loaded on the second shift register. A second mode of the second shift register is selected. A first mode of a third shift register is selected. The plurality of bits is loaded on the third shift register. A second mode of the third shift register is selected and the plurality of bits is loaded from the third shift register at a second frequency, where the second frequency is lower than the first frequency, thereby providing for examining high-frequency clock-masking signal patterns at a reduced frequency.

Abstract: A phase difference between a timing of rising or falling of the data read from a semiconductor device to be test and a timing of rising or falling of a reference clock outputted synchronized with the data is measured by operating sampling with strobe pulses configured with multi-phase pulses given the phase difference by a small amount in regard to the timing of the data and the timing of the reference clock. In addition, a glitch of the data is detected, and the quality of the semiconductor device to be tested is judged based on the phase difference and/or the glitch.

Abstract: Unique representation, such as music or image full of originality, is generated in relation to a specific data sequence such as a telephone number. A music generation server 10 is provided with a material table TA in which material data associated with music phrases are provided in correspondence with the digits of the telephone number and the numerals thereof given at the respective digits, and such server is connected to a user's terminal, such as a PC 50 or a cellular phone 56. When a specific data acquisition program 30 is executed to acquire a telephone number as a specific data sequence from a user, a material data extraction program 32 is executed to make reference to the foregoing material table TA and extract therefrom a particular material data MD corresponding to the acquired telephone number. Then, a generation program 34 is executed to arrange such material data MD in a predetermined order and thereby generate one completed piece of music.

Abstract: There is provided a timing generator that outputs a second periodic signal having a desired phase difference to a first periodic signal by superimposing a voltage on a control voltage of a voltage-controlled oscillating unit of a PLL circuit for generating the second periodic signal. The timing generator includes an initializing unit for measuring a timing shift gain indicative of a ratio of a timing shift amount to a change of a superimposed voltage and a voltage generating unit for generating the superimposed voltage based on the desired phase difference and the timing shift gain.

Abstract: A programmable system for testing relays and controlling systems is provided. In one embodiment the present disclosure provides a programmable device capable of, for example, testing relays. The device includes a signal generator for generating signals to test relays. The device includes a memory location, and a first program stored in the memory location. The first program supports relay testing. The device includes a versioned program to support relay testing, and a processor in communication with the signal generator and the memory location. The device also includes a routine that is operable by the processor to install a versioned program in the memory location replacing the first program.

Abstract: An interpolator testing system and method comprises an interpolator that includes a phase shift module. The phase shift module receives a reference clock signal and generates M clock signals having phase shifts in increments of 360/M degrees relative to the reference clock signal. A phase select module receives the reference clock signal and a recovered clock signal during a normal mode and generates a select signal based on a comparison of the reference clock signal and the recovered clock signal during the normal mode. A selector receives the M clock signals and outputs one of the M clock signals as the recovered clock signal based on the select signal. A recovered clock counter counts an attribute of the recovered clock signal during a test mode. The phase select module sequentially selects the M clock signals N times during the test mode.

Abstract: Systems and methods are disclosed measuring the turn-on and turn-off times of an optoelectronic transceiver's transmitter circuitry. The method includes generating a two bit sequences from separate bit sequence generators using the same controlling pattern. The first bit sequence is transmitted through an optoelectronic device and compared with corresponding bit groups in the second bit sequence. The optoelectronic device is disabled and a count of compared bit groups is kept until the comparison indicates that the optoelectronic device is completely off. Using the count and one or more of the bit groups, a turn-off time is calculated. Alternatively, the method is used to calculate a turn-on time. The optoelectronic device is enabled and a count is kept from the time the device is enabled to when the comparison of the corresponding bit groups indicates that the optoelectronic device is completely on.

Abstract: A method and apparatus for estimating the changing frequency of a signal received by a satellite receiver from, illustratively, positioning system satellites is disclosed that enables a more accurate measurement of the change in frequency of that signal due to movement of the satellite receiver relative to those satellites. The system includes a PLL having a numerically controlled oscillator (NCO) and a filter of frequency estimates (FFE). In operation, an analog signal is received at the satellite receiver and the PLL tracks the changing signal frequency and outputs non-smoothed frequency estimates into the FFE. The FFE then smoothes noise in the signal to produce a more accurate smoothed frequency estimate of the input signal. Comparing multiple estimates over time allows Doppler shift of the signal frequency received by the satellite receiver to be calculated more precisely, thus resulting in more accurate satellite receiver velocity vector determinations and, hence, position measurements.

Abstract: A method and system is presented for measuring a data access time of an embedded macro module in an integrated circuit. A single external test signal is inputted into the embedded macro module for enabling a data input therein and extracting a data output therefrom. A pulse width of the single external test signal is incrementally increased until a latch of the data output is observed. Then, the data access time is obtained, as its substantially equals a time interval of the increased pulse width.

Abstract: There is provided a measuring apparatus that measures digital signals. The measuring apparatus includes a reference timing detecting unit operable to detect a first timing at which a digital signal becomes a first predetermined signal level and a second timing at which the digital signal becomes a second signal level different from the first signal level in an edge of the digital signal, and a timing computing unit operable to compute a third timing at which the digital signal becomes a third predetermined signal level based on the first signal level, the second signal level, the first timing, and the second timing.

Abstract: Embodiments of the present invention include first and second pulse trains input to a switch in synchronization. The first and second pulse trains may have a repeating high and low values at first and second frequencies, respectively, and the first pulse train may transition from the low to the high value with a first edge sharpness. The second pulse train input may have a lower than the first frequency. The switch may use a selection signal in synchronization with the first pulse train to select an output from the first or second pulse train to create an output pulse train appropriate to transition fault test an integrated circuit. The switch may switch from the second pulse train to the first pulse train and substantially maintain the first edge sharpness of the first pulse train during a low value of both the first and second pulse trains.

Abstract: A method of adjusting a strobe timing includes a first determining step in which an output pattern is compared with an expected result pattern at a strobe timing to determine whether the output pattern is matched to the expected result pattern; a variation range setting step in which a variation range of the strobe timing is set when the output pattern is not matched to the expected result pattern; a varying step in which the strobe timing is varied within the variation range; and a second determining step in which the output pattern is compared with the expected result pattern at the varied strobe timing to determine whether the output pattern is matched to the expected result pattern. Based on a result of the comparison, a function test is performed using the strobe timing to determine a pass/fail result of the semiconductor.

Abstract: Performing delay measurement between master and slave devices. The master transmits a delay measuring signal at a fixed timing relative to a synchronous pattern signal in an overhead and transmits a frame signal in which an internal delay time, associated with a frame signal generation, from a delay measurement start timing to a transmission timing of the delay measuring signal is stored in the delay measuring signal as a master offset value. The slave adds an internal delay time associated with a frame signal generation to the master offset value of the frame signal, making a slave offset value and transmits an updated delay measuring signal with the slave offset value. The master calculates a delay time by subtracting the slave offset value from a time difference between a timing at which the delay measuring signal transmitted from the slave is received and the delay measurement start timing.

Abstract: a Sensor Web formed of a number of different sensor pods. Each of the sensor pods include a clock which is synchronized with a master clock so that all of the sensor pods in the Web have a synchronized clock. The synchronization is carried out by first using a coarse synchronization which takes less power, and subsequently carrying out a fine synchronization to make a fine sync of all the pods on the Web. After the synchronization, the pods ping their neighbors to determine which pods are listening and responded, and then only listen during time slots corresponding to those pods which respond.

Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: Disclosed are a method and system for detecting point. The method of this invention comprises the steps of providing a set of points representing measured time delays between two clocks, providing a turning indicator to measure a magnitude of turns per measurement interval, and identifying a turn at a given point when the turn indicator at said given point is above a given value. With the preferred embodiment of the invention, the turn indicator is given by the equation: turn_indicator=(rtt_min?rtt_estimate)/number_of_points; where rtt_min is the minimum round trip delay in all the measurement points, and rtt_estimate is estimated round trip delay by using the symmetric convex hull algorithm.

Abstract: A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical parameters are combined to form one path group. For each path group, a statistical group figure is, then, calculated and, for the totality of paths considered, a statistical total figure is calculated. Finally, the critical paths of the circuit are determined by taking into consideration the total figure, comparing the group figures at or above a critical path transit time Tc.

Abstract: A sampling circuit for testing an integrated circuit receives several signals from points of interest in the integrated circuit, digitizes them, and determines whether the digitized signal is above or below a threshold. By sampling the signal at different phases of a system clock signal, a determination can be made of when during the system clock signal the signal at a point of interest changed state. Circuits are provided for making minimal impact on the circuit being observed. Circuits are also provided for clocking the observed signal so that it can be compared to other observed signals.

Abstract: A program and method enables easy creation and manipulation of timing charts. The preferred embodiment employs off-the-shelf commercial software and uses Visual Basic commands to get timing chart drawing commands into the drawing program and out of the spreadsheet program to order the drawing program to produce a displayable and print/plotable file. The user can easily see changes needed and even if they require ripple-through redrawing, because the user manipulates data in the spreadsheet file instead of directly manipulating drawing commands, the spread sheet will carry through ripple-through calculations to modify all lines related to the recalculated data.

Abstract: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

Abstract: A method and apparatus for establishing an average test time (TA) include determining a first time interval (TG) nominally associated with non-failing testing of a unit under test (UUT), and determining a second time interval (TPR) nominally associated with troubleshooting and repairing a failed unit under test. Additionally, a percent yield (Y) nominally associated with a proportion of non-failing units under test is determined. The average test time is a sum of the first time interval associated with the non-failing testing of the UUT, and a ratio of the second time interval associated with troubleshooting and repair of a failed UUT with respect to the yield.

Abstract: A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

Abstract: A system and method for configuring an automatic test system to produce a plurality of clocks from a reference clock includes a user interface and software. The user interface receives a plurality of inputs that specify desired frequencies of the plurality of clocks. In response to a command from the user interface, the software calculates values for dividers coupled to the reference clock, for deriving each of the desired frequencies from the reference clock. According to one embodiment, the desired frequencies form ratios that must be met to satisfy coherence. In calculating the divider values, the software minimizes frequency errors while precisely preserving the required ratios.

Abstract: A method for inspecting an object using a time delay integration sensor. A storage time of the time delay integration sensor is changed in response to a signal level of a signal outputted from the time delay integration sensor, and a scanning speed of a scan by the time delay integration sensor is changed in response to the signal level of the signal outputted from the time delay integration sensor. The object is then scanned using the time delay integration sensor to inspect the object under the changed storage time and the changed scanning speed.

Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Abstract: According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.

Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.