Abstract: A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based on a cumulative probability distribution of the delays of the critical paths, and a probability-density-distribution computing unit that computes a probability density distribution of delay of a critical path that has the greatest delay in the result. The detecting unit detects x number of critical paths having cumulative delays within computed probability density distribution.

Abstract: Methods and systems for verifying a logic circuit. In one embodiment, delay models based on clock cycles are developed and incorporated into the logic circuit so that timing considerations may be simulated.

Abstract: A technique to enable accurate timing and functional verification in a negative constraint calculation (NCC) implemented event-driven logic simulators when there are negative constraints in logic elements. In one example embodiment, the technique adjusts negative timing constraints by grouping the timing constraints based on associated output terminals in a digital logic circuit. The NCC is then applied to each grouped constraint to correct for path delays and resulting timing inaccuracy during an event driven simulation.

Abstract: A film thickness predicting apparatus compares a measurement value of a copper plating formed on wiring grooves of various patterns measured using a TEG and a film thickness of the copper plating calculated based on a plating model and a condition file. The film thickness predicting apparatus then delivers optimal plating model from the comparison result and calculates the film thickness of the copper plating formed on a substrate surface to be designed using the optimal plating model. The film thickness predicting apparatus enables to conduct a highly accurate film thickness predicting simulation.

Abstract: An aspect of the invention relates to a method, apparatus, and computer-readable medium for processing schematic data for an integrated circuit having a boundary scan architecture. A path through cells of the schematic data to generate a hierarchy of cells associated with a boundary scan chain. Each ignore cell in the hierarchy is pruned. Each short cell in the hierarchy is replaced with a direct connection. A shadow net is added to each net of the hierarchy. Each of the cells in the hierarchy is flattened in a bottom-up fashion.

Abstract: The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are replaced by predetermined desired values corresponding to the floating values which are both stored in a lookup table. In another embodiment, when a floating value is detected, that value is ignored and the previous clock value is retained.

Abstract: A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.

Abstract: Disclosed is a permanent recloser simulator feature for use in a single-pole trip capable recloser control. The permanent recloser simulator feature includes a first logic circuit capable of enabling and disabling operation of the permanent recloser simulator feature in response to receipt of a binary logic signal, and a second logic circuit coupled to the first logic circuit where the second logic circuit is configured to provide an indication of a status of a first pole to a logic engine of the single-pole trip capable recloser control. The permanent recloser simulator feature may further include a third logic circuit associated with a second pole, and a fourth logic circuit associated with a third pole where both are coupled to the first logic circuit. Disabling means of the first logic circuit allow the first, second, third and fourth logic circuit to permanently reside in logic of the recloser control.

Abstract: An arithmetic device allocation design method of the present invention includes the steps of: in the case of allocating an arithmetic operation A to the arithmetic device, comparing an increased circuit area due to a selector to be provided so as to allocate the operation A to an arithmetic device C to which another arithmetic operation B has already been allocated and an increased area due to an arithmetic device D to be created anew to which only the operation A is allocated; when the increased circuit area due to the selector is smaller, allocating the operation A to the device C to which the another operation B has already been allocated while providing the selector; and when the increased circuit area due to the device D is smaller, creating the device D anew so as to allocate the operation A to the device D created anew.

Abstract: An event queue for use with a software-enabled logic simulation tool can include a heap array and a hash table data structure. The heap array can include time slots organized such that each time slot conforms to heap properties which specify, at least in part, that a root node of the array indicates a time slot having a minimum simulation time value. The hash table data structure can include a plurality of entries, wherein selected ones of the entries specify references to at least one of the time slots.

Abstract: A system and method for unfolding/replicating logic paths to facilitate propagation delay modeling are provided. With the system and method, nets of an integrated circuit design are unfolded and logic of these nets is replicated such that each leg of a fanout can be driven independently from the signal source. In order to unfold the nets, the nets and logic are replicated in the netlist and connected to replicated source and endpoints. These new nets in the netlist may then be driven separately such that a different propagation delay along different nets from the same source may be simulated. In this way, a level of propagation delay may be abstracted into the modeling by driving or delaying each path separately. The transitioning value will then appear to have differing arrival times from the perspective of the sinks.

Abstract: A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a multi-cycle path detector determines whether all the paths in the path set are multi-cycle paths. When the path set is a multi-cycle path, it is added to a timing exception path list that is output by an output unit.

Abstract: A method for determining a timing margin to be applied in an integrated circuit timing design. Circuit simulator path delays and static timing analysis tool path delays are determined for the integrated circuit timing design. The circuit simulator path delays are plotted in a first plot versus a percentage difference between the circuit simulator path delays and the static timing analysis tool path delays, and in a second plot are plotted versus a numerical difference between the circuit simulator path delays and the static timing analysis tool path delays. A first point is identified on the second plot having a largest numerical difference, and the circuit simulator path delay for the first point is identified. A corresponding point on the first plot having the circuit simulator path delay is found, and the percentage difference for the corresponding point is identified. A combination of both the circuit simulator path delay and the percentage difference is used as the timing margin.

Abstract: An electrical circuit can be described with a reference model that has a plurality of states and a plurality of state transitions. Acceptable and/or unacceptable instruction sets are predefined for each state. Acceptable and unacceptable instruction sets are generated randomly in succession from the reference model and applied to a mapping of the electrical circuit for processing. By comparing the instruction sets processed by the mapping of the electrical circuit with the instruction sets determined from the reference model, conclusive information relating to the mapping of the electrical circuit is obtained.

Abstract: A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more accurate matching of actual receiver signal timing characteristics. For example, a two-capacitance receiver model can be generated by using the first capacitance value to match the delay characteristics of an actual receiver, and by using the second capacitance (in light of the use of the first capacitance) to match the slew characteristics of that actual receiver. Because typical EDA timing analyses focus mainly on delay and slew (and not the detailed profile of circuit signals), a two-capacitance receiver model can provide a high degree of accuracy without significantly increasing cell library size and computational complexity.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The at least one daughter card and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard and the at least one daughter card is tested.

Abstract: A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at least one storage unit, and simulating the segment in accordance with the state of the at least one storage unit; and the system including a memory for describing storage units of a circuit, maintaining states of the storage units, and identifying distributed segments comprising combinational logic separated by the storage units, and processing units, each for simultaneously simulating at least one of the segments in accordance with the maintained states.

Abstract: A code coverage tool provides that a netlist is instrumented with gates for providing a comparison of an output of the design gates on one cycle with their output on a next cycle to determine if the gate was exercised during an emulation.

Abstract: A method of developing the physical layout of an electronic component in a data bus connected logic analog system includes: providing a data bus connected logic analog system modeled as a software-implemented channel simulation model including: a bit pattern generator for generating a bit pattern; the electronic component, whose physical layout is to be determined by being modeled as a black box characterized by model parameters; and a bit pattern analyzer for analyzing a bit error rate of the bit pattern; sending an input bit pattern through the black box to produce an output bit pattern and comparing the output bit pattern with the input bit pattern to determine a bit error rate; and varying the model parameters and repeating the process until the determined bit error rate is below a pre-determined value to determine at least one critical model parameter boundary.

Abstract: A method of conducting timing analysis on an integrated circuit design includes performing a first routing operation on the design to generate a first routed design that includes redundant vias, and storing the first routed design in a first design database, and performing a second routing operation on the synthesized design to generate a second routed design that does not include redundant vias, and storing the second routed design in a second design database. Then, extractions are performed on the first and second designs and delay calculations are performing on the first and second extractions files. The first and second delay calculations are compared to determine a delay difference between the first and second designs and timing analysis is performed using the delay difference.

Abstract: A circuit design method utilizes existing late mode worst case slack calculation functions inherent in timing path trace algorithms which only need to record the worst arrival and worst required arrival times at each netlist node as traced paths. Because of this, most individual path tracing is curtailed due to the likelihood that a more critical arrival or required arrival time has already been recorded at a given netlist node. Worst case slacks are then determined by subtracting the worst case arrival time from the worst case required arrival time. In this manner, worst case slack values are calculated for the entire netlist within a reasonable amount of time. The method uses these existing functions by querying the worst case slack at each netlist node under varied timing model scenarios. These varied timing model scenarios include altering the cell and net delays and arrival times in the model.

Abstract: A design tool inserts randomized delays into synchronizers for signals crossing from one clock domain to another. Rather than having a wide range of random delays to select from, each synchronizer's randomized delay is selected from only two possibilities. An added delay of either zero or one clock period of the new domain's clock is added as the randomized delay. The randomized delay causes the re-synchronized domain-crossing signal to become available either in the expected cycle or in the cycle following the expected cycle. Logic hazards caused by the domain-crossing signal can be detected and the possible results simulated. The synchronizer can be a series of two flip-flops, with the random delay added to the first flip-flop. Randomized delays of either one or none added periods of the clock can also be added to multi-cycle signals within one clock domain that have two or more clock cycles to propagate.

Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Abstract: Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, associating the plurality of power domains and the power information specifications in the RTL design environment, where the plurality of power domains are controlled by a set of power control signals through a power manager logic, isolating a power domain among the plurality of power domains for simulation, and simulating isolation behavior of the power domain in response to variations in power applied to the power domain.

Abstract: The present invention provides techniques for high speed electrical simulation of circuits. According to one embodiment of the present invention, a delay path can be divided into sub-paths called simulation paths. Each simulation path is simulated separately to determine its contribution to the overall delay in the path. According to another embodiment of the present invention, linear and non-linear loads are modeled using linear circuit models to further increase the speed of the simulator. According to another embodiment, driver circuits are simulated using non-linear circuit models. Before a simulation is performed, sample input and output values for the non-linear models are computed and stored in memory. When a circuit design is simulated, the input and output values are accessed from the memory. Intermediate values are determined by interpolating from the values stored memory.

Abstract: A method and apparatus for computer modeling the production process is disclosed. An integrated product and process engineering system may be a computer modeling system that models both a generic production process and a specific individual production process. The integrated product and process engineering system may store a time dependent process parameter related to the production process, having uploaded them via an interface. The time dependent process parameters may be retrieve and displayed to the user on a display using a remote function call enabled function module. The time dependent process parameters may be uploaded from an external system or revised using a remote function call enabled function module.

Abstract: A method for modeling engine operation comprising the steps of: 1. collecting a first plurality of sensory data, 2. partitioning a flight envelope into a plurality of sub-regions, 3. assigning the first plurality of sensory data into the plurality of sub-regions, 4. generating an empirical model of at least one of the plurality of sub-regions, 5. generating a statistical summary model for at least one of the plurality of sub-regions, 6. collecting an additional plurality of sensory data, 7. partitioning the second plurality of sensory data into the plurality of sub-regions, 8. generating a plurality of pseudo-data using the empirical model, and 9. concatenating the plurality of pseudo-data and the additional plurality of sensory data to generate an updated empirical model and an updated statistical summary model for at least one of the plurality of sub-regions.

Abstract: A timing analysis method evaluates a performance of a target circuit that is to be designed, and includes calculating a correlation coefficient r between two arbitrary macro cells that are coupled and form the target circuit based on layout information including an arrangement of macro cells forming the target circuit and correlation information indicating a correlation between two macro cells that are coupled for each of arrangements of macro cell pairs, calculating a distribution function ? of a standard deviation of delay times of the two arbitrary macro cells based on the correlation coefficient ?, and carrying out a statistical timing analysis of the target circuit based on the correlation coefficient r and the distribution function ? of the standard deviation with respect to each of the macro cell pairs forming the target circuit.

Abstract: A technique for performing signal integrity analysis of a system includes providing a stimulus pattern and a model of the system and performing analog simulation of the model utilizing the stimulus pattern. The stimulus pattern includes sequences of signal transitions with associated transition times and the sequences of signal transitions conform to a bus protocol and the associated transition times are according to characteristics of the system. The stimulus pattern is generated by initializing each of the sequences of signal transitions to an initial signal value and the associated transition times to an initial time, generating subsequent signal values and subsequent transition times by applying protocol rules and calculating timing adjustments for each of a list of transactions; the subsequent signal values and subsequent transition times to be added to the sequences of signal transitions.

Abstract: An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility of executing the extracted unexecuted descriptions. A prohibited-input-checker generator generates a test pattern. The test pattern is to execute descriptions including unexecuted descriptions that there is a possibility of executing and excluding unexecuted descriptions that there is no possibility of executing as determined by the examiner. The prohibited-input-checker generator also generates a prohibited-input checker to check whether or not an input pattern of a logic simulation to be carried out is equal to an input pattern of the test pattern to execute the unexecuted description if the test bench is regarded as a prohibited input under a specification at a logic simulation using the test pattern to execute the unexecuted description.

Abstract: One embodiment of the invention provides a system that facilitates integrating a simulation log into a verification environment. The system operates by first creating the simulation log during a simulation of a register transfer language description of an integrated circuit design. Next, for each entry in the simulation log, the system places a corresponding entry in a “log entry table.” When a user selects an entry from the simulation log, the system determines a file offset for the entry within the simulation log. Next, the system locates the corresponding entry in the log entry table. The system then uses the log entry table to locate entries within simulator state files, which describe which portion of the integrated circuit is being simulated. This enables the system to display the corresponding entries from the simulator state files to a user.

Abstract: An apparatus is adapted to be used to create software and programming instructions for a distributed process control system having a user workstation remotely located from a distributed controller that controls one or more field devices using control modules. The apparatus includes a computer having a memory and a processing unit as well as a configuration application and a controller application stored on the computer memory to be executed on the processor. The configuration application is further capable of being executed on the user workstation of the distributed process control system to create the control modules for execution by the distributed controller while the controller application is adapted to be executed on the distributed controller to implement one of the control modules during operation of the distributed process control system.

Abstract: A method for simulating a circuit includes representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph. The method further includes arranging the subcircuits from the hierarchically arranged set of branches into one or more groups, determining a data structure for each subcircuit in a group that supports a combination of selectively flattened and selectively expanded group of subcircuits, selecting a subcircuit as a simulation leader and identifying remaining subcircuits as followers in the group, where the simulation leader have states substantially equivalent to the followers, simulating the respective simulation leader of each group using a selectable simulation driver, and replicating simulation results of the respective simulation leader of each group to its followers.

Abstract: In hierarchical design of a logic circuit by utilizing lower-level blocks of the logic circuit, data on the logic circuit with the hierarchical structure, library data holding primitive information on the logic circuit and timing constraints on the lower-level blocks are input at a data input step. Based on these input data, it is determined whether or not interface specifications of timing constraints on the lower-level blocks match each other at a matching determination step before a constraint converting step of converting the timing constraints on the lower-level blocks into a timing constraint on a higher-level block. Accordingly, it is possible to avoid generation of an excessively reduced or rigorous timing constraint on the higher-level block resulting from mismatching between interface specifications of timing constraints on the lower-level blocks.

Abstract: A method for transforming a behavioral specification involves converting the behavioral specification into a diagram representation, converting a delay from the diagram representation if the behavioral specification comprises a delay, generating a compliant cycle diagram from the diagram representation, and deriving a cycle equivalent behavioral specification from the compliant cycle diagram.

Abstract: The system simulator comprises master simulators 1f, 1s, 2f and 2s for simulating a bus master, a slave simulator L for simulating a bus slave, a function manager F for sequentially actuating the master simulator and the slave simulator by using a function call and a thread manager S for actuating the master simulator by using a thread switching. When the master simulator activated by using the function call from the function manager accesses the slave simulator and an access blocking is caused, the master simulator controls the thread manager such that the master simulator is activated by using the thread switching carried out by the thread manager. Thus, it is possible to carry out the simulation at a high speed without getting into a dead lock state caused by the access blocking and without changing the simulator for simulating a conventional bus master.

Abstract: Lookback is defined as the ability of a logical process to change its past locally (without involving other logical processes). Logical processes with lookback are able to process out-of-timestamp order events, enabling new synchronization protocols for the parallel discrete event simulation. Two of such protocols, LB-GVT (LookBack-Global Virtual Time) and LB-EIT (LookBack-Earliest Input Time), are presented and their performances on the Closed Queuing Network (CQN) simulation are compared with each other. Lookback can be used to reduce the rollback frequency in optimistic simulations. The relation between lookahead and lookback is also discussed in detail. Finally, it is shown that lookback allows conservative simulations to circumvent the speedup limit imposed by the critical path.

Abstract: A method, data processing system, and program product for building an instrumented simulation model of a digital design are disclosed. According to the method, a model build tool locates, within design data collectively defining a simulation model of the digital design, a definition of a configuration construct specifying a relationship between values of one or more configuration latches within the digital design and settings of the configuration construct. In response to locating the definition of the configuration construct, the model build tool automatically creates an instrumentation entity within the design data. The instrumentation entity has one or more inputs logically coupled to the one or more configuration latches and one or more outputs for providing signals indicating characteristics of the configuration construct during simulation.

Abstract: A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.

Abstract: A method for modeling a circuit layout to determine behavior responsive to a radiation event is set forth. The method includes identifying a first portion of the circuit layout that includes at least one body region of a MOS transistor in the circuit layout, the at least one region having a width substantially equal to that of the MOS transistor. A first model corresponding to the first portion of the circuit layout is selected. A second portion of the circuit layout that includes at least a first region within a drain of the MOS transistor in the circuit layout is identified and an appropriate second model corresponding to the second portion of the circuit layout is selected, wherein the at least one second model includes at least one parasitic bipolar transistor.

Abstract: The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of simulating a digital circuit in such a way that the simulation is stopped at desired functions for subsequent analysis. A hardware design code describing the digital circuit is converted to an assignment decision diagram (ADD) representation that is then annotated with one or more control nodes that are used for maintaining control flow through a simulator. In this way, one or more break points are created that allow the simulator to stop at associated points in the simulation.

Abstract: In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.

Abstract: A distributed simulation system is provided in which timesteps may be divided into a first phase (referred to as the zero time phase herein) and a second phase (referred to as the real time phase herein). In the first phase, each distributed simulation node in the system may process one or more received commands without causing the simulator to evaluate the model in that distributed simulation node. In the second phase, each distributed simulation node may cause the simulator to evaluate the model in response to a command supplying one or more signal values to the model. In one embodiment, the second phase may iterate the evaluation of the model for each command received which supplies signal values. Each iteration may optionally include transmitting a command including the output signal values produced by the model during that iteration.

Abstract: Methods and apparatus are provided for efficiently generating test components for testing and evaluating a design under test. As a design is being configured, generated test components are made available. In one example, test components are automatically generated and included in a simulation testbench based on selected components in the design. Generally, the test components complement the selected components in the design. Moreover, the test components can be automatically seeded with initial contents.

Abstract: A method for routing a message from a source node to a destination node, where the source node and the destination node are connected by a plurality of nodes in a cycle-based system, is disclosed. The method includes generating a maze data structure including the plurality of nodes, where each of the plurality of nodes is associated with a dimension corresponding to time, and routing the message from the source node to the destination node using the dimension corresponding to time.

Abstract: For the purpose of readily specifying a portion of the circuit which has a high possibility of error occurring due to a variation in the supply voltage so that the specified vulnerable portion is countermeasured in a mask layout process, a simulation section simulates the operation of a semiconductor integrated circuit to obtain a transition timing of an input signal that is input to each circuit element. A simultaneous-operation circuit element number detecting section detects, based on a result of the simulation, the number of circuit elements which are supplied with the supply voltage through a common power supply line and in which transition timings of input signals occur within a predetermined time interval (e.g., 0.3 ns or shorter). A supply voltage variation level estimating section estimates the variation level of the supply voltage according to the number of circuit elements which is detected by the simultaneous-operation circuit element number detecting section.

Abstract: Computer time for modeling VLSI interconnection circuits is reduced by using symmetric properties of modified nodal analysis formulation. The modeling uses modified nodal analysis matrices then applies a Krylov subspace matrix to construct a congruence transformation matrix to generate the reduced order model of the VLSI.

Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.

Abstract: A method and computer readable storage medium for estimating total path delay in an integrated circuit design include of receiving as input a number of stage delays and stage delay variations constituting a path in an integrated circuit design. A sum of the stage delays, a worst case sum of the stage delay variations, and a root-sum-square of the stage delay variations are calculated. A a value of a weighting function is calculated as a function of the number of stage delays. A a weighted sum of the worst case sum of the stage delay variations and the root-sum-square of the stage delay variations is calculated from the weighting function. The weighted sum is generated as output to estimate total path delay.

Abstract: Under the present invention, a proposed placement of I/O pads into one or more groups on a chip analyzed. Specifically, using resources such as a control file, cross-reference table, an I/O limit table, and an optional information file, a group switching current for each proposed I/O pad group is automatically calculated and compared to predetermined maximum switching current(s). If an I/O pad group exhibits a switching current that exceeds its predetermined maximum, corrective action is taken. Such action can include, for example, relocation of an I/O pad from an overloaded I/O pad group to another I/O pad group, insertion of an additional power pad into the overloaded I/O pad group, etc.