Including Logic Patents (Class 703/15)
  • Patent number: 11874920
    Abstract: Disclosed herein are systems and methods for preventing malicious injections. In one aspect, a method includes monitoring active processes that are running in suspended mode. For each active process being monitored, the method includes injecting a dynamic link library (DLL) into the active process to hook an application programming interface (API) of an application corresponding to the active process, wherein the DLL is injected for tracking commands for suspension and resumption of the active process. The method includes monitoring file inputs and outputs of the application for anomalies while the active process is in the suspended mode, and when a command for resuming the active process is detected using the DLL, determining, based on the monitoring, whether a malicious process is inserted into the active process. The method includes allowing the suspended process to resume execution in response to determining that no malicious process is inserted in the active process.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 16, 2024
    Assignee: Acronis International GmbH
    Inventors: Vladimir Strogov, Serguei Beloussov, Stanislav Protasov
  • Patent number: 11871003
    Abstract: This disclosure is directed to systems and methods of rate control in multiple pass video encoding. The video encoder may complete multiple encoding passes for slices of an image. Rate control algorithms may be implemented that scale the quantization step size and quantization matrix values depending on the determined size of the image slices. This may enable the size of slices to be adjusted based on size parameters for the image data.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 9, 2024
    Assignee: Apple Inc.
    Inventors: Sorin C Cismas, Ganesh G Yadav
  • Patent number: 11816410
    Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: November 14, 2023
    Assignee: Siemens Electronic Design Automation Gmbh
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
  • Patent number: 11816343
    Abstract: Non-volatile memory (NVM) dies of a data storage device, wherein on-chip latches of the dies are made available to a host device for use as volatile memory. In some examples, a data storage controller dynamically determines when the latches of a particular NVM die of an NVM array are available for use as volatile memory and exports those particular latches to the host device for use as random access memory (RAM). In other examples, the data storage controller dynamically determines when particular dies of the NVM array of dies are available and exports all latches of those dies to the host device for use as RAM. The data storage controller may rotate NVM die usage so that, over time, different dies are used for latch-based volatile memory while other dies are used for NVM storage. Usage profiles are described that allow the host device to select particular latch usage configurations.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: November 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Dinesh Kumar Agarwal
  • Patent number: 11775693
    Abstract: The present disclosure describes systems and methods for test pattern generation to detect a hardware Trojan using delay-based analysis. One such method comprises determining a set of initial test patterns to activate the hardware Trojan within an integrated circuit design; and generating a set of succeeding test patterns to activate the hardware Trojan within the integrated circuit design using a reinforcement learning model. The set of initial test patterns can be applied as an input to the reinforcement learning model. Further, the reinforcement learning model can be trained with a stochastic learning scheme to increase a probability of triggering one or more rare nodes in the integrated circuit design and identify optimal test vectors to maximize delay-based side-channel sensitivity when the hardware Trojan is activated in the integrated circuit design. Other methods and systems are also provided.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: October 3, 2023
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Prabhat Kumar Mishra, Jennifer Marie Sheldon, Zhixin Pan
  • Patent number: 11776425
    Abstract: Examples include a frame supporting a holding slot with guide surfaces along an axis from a slot power connector. A first and a second circuit board device are movably supported by the guide surfaces. Each includes a first side edge, a second side edge, and a laterally stackable power rail extending from a first connector on the first side edge to a second connector on the second side edge. Each includes a guide structure moveably engaging the slot guide surfaces. In a state, the first circuit board device is adjacent the slot power connector. The second circuit board device is adjacent the first circuit board device. the first connector of the first circuit board device is aligned and coupled with the slot power connector, the second connector of the first circuit board device is aligned and coupled with the first connector of the second circuit board device.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: October 3, 2023
    Inventors: Asim Dajoh, Mohammed Altalhi
  • Patent number: 11726899
    Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: August 15, 2023
    Assignee: Synopsys, Inc.
    Inventors: Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Solaiman Rahim, Olivier Coudert
  • Patent number: 11680982
    Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: June 20, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Manish Sharma, Tripti Gupta
  • Patent number: 11645438
    Abstract: Generating a template-driven schematic from a netlist of electronic circuits is disclosed. The template-driven schematic may be useful to generate a set of related circuits for a single overall design as well as allow for a common transfer mechanism between different Computer Aided Design (CAD) systems. To assist in portability of designs, a common file format is disclosed based on a structured text file (e.g., XML). Further, in the disclosed approach, it is possible to not only place primitives but create custom symbols as well. In addition, primitives and symbols may be attached to models, simulation settings may be added, and routing of the circuit in a schematic may be completed. Associated devices and methods are disclosed as well.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 9, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pradeep Kumar Chawda, Makram Monzer Mansour
  • Patent number: 11599697
    Abstract: Various examples are directed to systems and methods for evaluating electronic components. A server computing device may provide an evaluation user interface to a user application executing at a user computing device. The server computing device may receive an indication of an electronic component for evaluation from the user application and via the user interface and access a configuration data set for the electronic component. The configuration data set may comprise argument data describing a set of arguments for the electronic component; binding data describing a relationship between a first argument of the set of arguments and a first model input parameter; and simulator data describing a model for the electronic component. The server computing device may also evaluate the electronic component based at least in part on the configuration data set.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 7, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Jason Cockrell, Thomas M. MacLeod
  • Patent number: 11494537
    Abstract: One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: November 8, 2022
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Aleksandar B. Feldman, Johan de Kleer, Alexandre Campos Perez, Ion Matei
  • Patent number: 11487643
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for implementing a debugger for integrated scripting applications. One of the methods includes generating a modified script from an original script, the modified script being written in a scripting language and having a respective breakpoint inquiry command for a plurality of original commands from the original script, wherein each breakpoint inquiry command calls a breakpoint inquiry function with a unique identifier assigned to a corresponding original command. The modified script is executed including calling the breakpoint inquiry function before the plurality of original commands from the original script. If a particular call to the breakpoint inquiry function corresponds to a set breakpoint, execution of the modified script is stopped and updated debugging information is provided to a debug client configured to generate a user interface presentation of the updated debugging information.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: November 1, 2022
    Assignee: XILINX, INC.
    Inventor: Stephen L. Bade
  • Patent number: 11475191
    Abstract: Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Paul Umbarger, Debapriya Chatterjee, Karen Yokum, John A. Schumann, Bryant Cockcroft, Kevin Barnett
  • Patent number: 11461148
    Abstract: In an acceleration processing method, an acceleration processing device combines a first acceleration application and a second acceleration application to obtain a first combined application, and burns the first combined application to a first acceleration resource, where the first combined application includes a top module, the first acceleration application, and the second acceleration application, and the top module includes a statement used to invoke the first acceleration application and a statement used to invoke the second acceleration application.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: October 4, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Conghua Lei, Weijun Le, Lei Shi
  • Patent number: 11403450
    Abstract: A system and method for providing convergence centric coverage for clock domain crossing (CDC) jitter in simulation is described. The method includes, in part, defining one or more design constraints associated with the circuit design, determining at least one group of converging signals associated with the circuit design using the one or more design constraints, applying a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and storing the jitters in a jitter database.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: August 2, 2022
    Assignee: Synopsys, Inc.
    Inventors: Anshu Malani, Paras Mal Jain, Rajarshi Mukherjee, Sudeep Mondal
  • Patent number: 11347918
    Abstract: This validation processing device is provided with: a processing unit that performs model checking on a model to be checked; and a selection unit that selects, on the basis of the result of the model checking, one element from among elements that have undergone state change in a process leading to an unsafe event. The processing unit further performs model checking again on the model to be checked excluding the one element.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 31, 2022
    Assignee: MITSUBISHI HEAVY INDUSTRIES ENGINEERING, LTD.
    Inventors: Kenji Takao, Keita Hirayama
  • Patent number: 11288430
    Abstract: A simulation circuit, that simulates characteristics of transistors is produced to include: an isolation body resistor representing resistance of a channel isolation portion of a transistor; a main body resistor representing resistance of main channel portion of the transistor; an isolation transistor connected to the isolation body resistor; and a body-contact transistor connected to the main body resistor. Simulated data is generated by supplying test inputs to the simulation circuit, while selectively activating either the isolation transistor or the body-contact transistor. Test data is generated by supplying the test inputs to the transistors, and measuring output of the transistors. The simulated data is compared to the test data to identify data differences. The design of the transistors is changed to reduce the data differences. The generation of test data, comparing, and design changes are repeated, until the data differences are within a threshold.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 29, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Anupam Dutta, Tamilmani Ethirajan
  • Patent number: 11275582
    Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: March 15, 2022
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
  • Patent number: 11221930
    Abstract: A method of simulating device state changes in an integrated system includes receiving a transaction request from a client device, storing the transaction request as a first event in an event log, transmitting the transaction request to a terminal device, storing the transmission of the transaction request as a second event in the event log, receiving a device response from the terminal device, storing the device response as a third event in the event log, and when the integrated system is under test, a simulator replays the stored events in the integrated system under test.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: January 11, 2022
    Assignee: Worldpay, LLC
    Inventor: Jared Wood
  • Patent number: 11184006
    Abstract: According to some aspects, a method is provided of operating a system that includes a multi-level quantum system dispersively coupled to a first quantum mechanical oscillator and dispersively coupled to a second quantum mechanical oscillator, the method comprising applying a first drive waveform to the multi-level quantum system, applying one or more second drive waveforms to the first quantum mechanical oscillator, and applying one or more third drive waveforms to the second quantum mechanical oscillator.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 23, 2021
    Assignee: Yale University
    Inventors: Chen Wang, Yvonne Gao, Luigi Frunzio, Michel Devoret, Robert J. Schoelkopf, III
  • Patent number: 11170147
    Abstract: A function equivalence check method includes receiving a cell list, receiving an analog constraint of a cell in the cell list, generating the full-coverage input stimuli according to the analog constraint, performing a behavioral-level simulation using the full-coverage input stimuli and according to the behavioral code to generate a behavioral-level simulation result, performing a circuit-level simulation using the full-coverage input stimuli and according to the circuit-level netlist to generate a circuit-level simulation result, and comparing the behavioral-level simulation result and the circuit-level simulation result to generate a comparison report for an analog value auto-comparison.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: November 9, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lu Liao, Mei Wang, Yueping Li
  • Patent number: 11157671
    Abstract: A method of checking equivalence between a first design comprising a shift register logic SRL chain and a second design comprising a memory block. The method comprises identifying an inductive invariant to replace the SRL chain or the memory block, and replacing the SRL chain and the memory block by a set of constraints, wherein the set of constraints state that the SRL chain and the memory block are equivalent for the checking of equivalence between the first design and the second design.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: October 26, 2021
    Assignee: OneSpin Solutions GmbH
    Inventors: Peter Warkentin, Arun Chandrasekharan, Tobias Welp
  • Patent number: 11156660
    Abstract: A system for testing of one or more electronic devices is disclosed. In an embodiment, a processor transmits one or more test vectors to the one or more electronic devices. The one or more test vectors are based upon configuration parameters of the processor and input-output parameters of the one or more electronic devices. The processor receives scan vectors from the one or more electronic devices in response to the plurality of test vectors. The processor verifies in-system behavior of the one or more electronic devices based upon comparing received scan vectors with expected scan vectors.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 26, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Mitchell Poplack, Xiaolei Guo, Phung Truong, Justin Schmelzer
  • Patent number: 11151326
    Abstract: A method and a systems of interchanging code-mixed words and uni-language words are described. In an embodiment, the method may include identifying two or more portions of a target word, wherein the target word is one of a code-mixed word and a uni-language word. The method may further include determining one or more equivalent words corresponding to at least one portion of the two or more portions, wherein the one or more equivalent words are in at least one predetermined target language. The method may further include selecting at least one equivalent word from the one or more equivalent words, based on a context of the target word within a sentence comprising the target word. The method may further include replacing the at least one portion of the two or more portions of the target word with the selected at least one equivalent word.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 19, 2021
    Assignee: Wipro Limited
    Inventors: Manjunath Ramachandra Iyer, Boby Chaitanya Villari
  • Patent number: 11087001
    Abstract: A system includes a memory, a processor in communication with the memory, and a scanner. The scanner is configured to execute a first simulation instructions and track a register value and/or a stack value while executing the simulation. Responsive to encountering a conditional branch, the scanner is configured to split the first simulation into a second simulation and a third simulation to follow respective legs of the conditional branch. The scanner is also configured to track a movement from a register and/or a stack associated with the memory, record the movement and instruction associated with the movement, and report potential vulnerabilities.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: August 10, 2021
    Assignee: Red Hat, Inc.
    Inventor: Nick Clifton
  • Patent number: 11055140
    Abstract: A system for hierarchical cooperative computing is provided, comprising a vector definition service configured to receive a user-submitted request, and compile the request into a vector; a rules engine configured to retrieve the vector from the vector definition service, and evaluate the vector for appropriateness; a parametric evaluator configured to parameterize the vector, and generate at least a run from the parameterized vector; and an optimizer configured to retrieve the run from the parametric evaluator, and determine an optimal plan for executing the user-submitted request.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 6, 2021
    Assignee: QOMPLX, Inc.
    Inventors: Jason Crabtree, Andrew Sellers
  • Patent number: 10997335
    Abstract: For exceptional logic element management, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method identifies an exceptional logic element, wherein the exceptional logic element comprises one or more of an exceptional logic state, an exceptional state transition, and an exceptional input combination. In addition, the code displays the plurality of logic states excluding the exceptional logic elements from display.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: May 4, 2021
    Assignee: Assurant Design Automation LLC
    Inventor: M. David McFarland
  • Patent number: 10990504
    Abstract: A novel and useful system and method of time traveling source code debugging including several advanced capabilities that significantly improve the source code debugging process. Upon hitting a breakpoint or opening a dump file, the debugger travels to the future which can be altered by a user by modifying code on the fly (live coding) and receiving immediate feedback to validate bug fixes. Visual annotations including values of variables and expressions are provided as a heads up display effectively flattening time and space. A pivoting capability allows a user to switch the execution context of the code at any time. Point in time links that store the state of the debugging session can be created and activated. An asynchronous collaboration and messaging system enables multiple participants to share a debugging session. An optional redaction capability is also provided for obscuring or replacing sensitive private information.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: April 27, 2021
    Assignee: OzCode Ltd.
    Inventors: Omer Raviv, Alon Mordechai Fliess
  • Patent number: 10969429
    Abstract: The present disclosure relates to a system and method for debugging in fault simulation associated with an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and performing concurrent fault simulation on a fault to be analyzed associated with the electronic circuit design, wherein the fault has a fault propagation path associated therewith. Embodiments may also include identifying a trace of one or more signals of interest that are in the fault propagation path and generating a faulty database and a good database associated with the one or more signals of interest that are in the fault propagation path. Embodiments may further include identifying one or more differences between the faulty database and the good database.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manoj Kumar, Rishabh Gupta, Inderpreet Singh Baweja
  • Patent number: 10942737
    Abstract: Techniques and mechanisms for exchanging control signals in a data path module of a data stream processing engine. In an embodiment, the data path module may be configured to form a set of one or more data paths corresponding to an instruction which is to be executed. In another embodiment, data processing units of the data path module may be configured to exchange one or more control signals for elastic execution of the instruction.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventor: Vladimir Ivanov
  • Patent number: 10896273
    Abstract: A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Schumann, Debapriya Chatterjee, Bryant Cockcroft, Kevin Barnett, Piriya K. Hall, Paul Umbarger, Karen Yokum
  • Patent number: 10866885
    Abstract: Methods, systems and apparatuses may provide for technology that applies a functional safety test stimulus to a hardware level simulator, automatically compiles an output of the hardware level simulator into a software test library (STL), and iteratively verifies that the diagnostic coverage of the STL file approximates the diagnostic coverage of the functional safety test stimulus.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Krishnan Anandh, Richard Bousquet, Vyasa Sai, Andrea Kroll, Mauro Pipponzi
  • Patent number: 10816600
    Abstract: Protocol analysis can include simulating, using a processor, a circuit design including a protocol analyzer embedded therein. The protocol analyzer can be coupled to low-level signals of an interface of the circuit design. During the simulating, the protocol analyzer detects a transaction from the low-level signals received from the interface. Transaction data is generated by the protocol analyzer specifying the transaction. The transaction data is output from the protocol analyzer.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 27, 2020
    Assignee: Xilinx, Inc.
    Inventors: David K. Liddell, Paul R. Schumacher
  • Patent number: 10796048
    Abstract: The independent claims of this patent signify a concise description of embodiments. A method of performing hardware emulation of a circuit design is presented. The method includes partitioning a first portion of the circuit design to a first configurable logic chip of a hardware emulator, adding a selection circuit to the circuit design in the first configurable logic chip, and selecting one of a first signal or a second signal during a first clock cycle. The first signal and the second signal are used in the circuit design. The method further includes storing a first value associated with the selected signal during a second clock cycle, and sending the first value to an output pin of the first configurable logic chip during a third clock cycle. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: October 6, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Nathaniel Azuelos, Alex Shot, Daniel Geist
  • Patent number: 10789118
    Abstract: The present invention provides an information processing device that improves the detectability of system errors. This information processing device includes: a means that generates a state graph based on relationship change information indicating a change in the relationship between a plurality of elements included in a system, the state graph having the elements as the vertices thereof and the relationship between the elements as the sides thereof; a means that generates a normal model having the state graph as a set of conditions to be fulfilled during normal system operation, based on the relationship change information; and a means that detects system errors and outputs error information indicating detected errors, based on the state graph and the normal model.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 29, 2020
    Assignee: NEC Corporation
    Inventors: Takashi Nomura, Koji Kida, Junpei Kamimura, Yoshiaki Sakae, Etsuko Katsuda, Kazuhiko Isoyama, Kentaro Yamasaki, Yuji Kobayashi
  • Patent number: 10783292
    Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: September 22, 2020
    Assignee: Pulsic Limited
    Inventors: Paul Clewes, Liang Gao, Jonathan Longrigg
  • Patent number: 10755026
    Abstract: A method of improving a design rule fixing process comprises receiving an integrated circuit design, including layout elements, and identifying a plurality of design rule violations in the integrated circuit design. The process then identifies a plurality of possible actions, each action comprising fixing a design rule. The process then uses a deep learning algorithm to select an action, the action representing fixing of a particular design rule violation. The process then comprises applying a first patch, based on the order returning to step (b) to select a next patch to apply.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 25, 2020
    Assignee: Synopsys, Inc.
    Inventor: Jianfeng Luo
  • Patent number: 10698805
    Abstract: A method for debugging a system on chip (SoC) under test, may include automatically inserting commands in a test code for testing the SoC for invoking printing of messages of data, each message of the messages including start time, end time of each executed action of a plurality of actions, the executed action to be invoked by the test code when testing the SoC, the data further including identity of a processing component of a plurality of processing components of the SoC, on which the executed action was executed; recording the data of the invoked printed messages during testing of the test code on the SoC; and displaying, via a graphical user interface, one or a plurality of graphical representations, each of said graphical representations relating to a period of activity of one of the plurality of processing components over time, based on the recorded data.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: June 30, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Meir Ovadia
  • Patent number: 10671774
    Abstract: A method for tailoring a bespoke processor includes generating first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application. The method includes gate cutting and stitching based on the first gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 2, 2020
    Assignees: Regents of the University of Minnesota, The Board of Trustees of the University of Illinois
    Inventors: Hari Cherupalli, Rakesh Kumar, John Sartori
  • Patent number: 10650323
    Abstract: Systems and methods are provided for coupling two flux qubits. A quantum circuit assembly includes a first flux qubit, having at least two potential energy minima, and a second flux qubit, having at least two potential energy minima. A system formed by the first and second qubits has at least four potential energy minima prior to coupling, each of the four potential energy minima containing at least one eigenstate of a system comprising the first flux qubit and the second flux qubit. A coupler creates a first tunneling path between a first potential energy minimum of the system and a second potential energy minimum of the system, and a second tunneling path between a third potential energy minimum of the system and a fourth potential energy minimum of the system. The coupler creates the first and second tunneling paths between potential energy minima representing states of equal bit parity.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 12, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Ryan J. Epstein, David George Ferguson
  • Patent number: 10635556
    Abstract: A device maintenance apparatus includes a setting operator configured to allow for setting a test pattern, the test pattern being set to define a change of output signals output from a device over time, and an execution operator configured to make the device output the output signals based on the set test pattern.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 28, 2020
    Assignee: Yokogawa Electric Corporation
    Inventors: Hirotaka Katayama, Hiromi Okamoto, Yuya Iketsuki
  • Patent number: 10613143
    Abstract: A controller system includes a microprocessor having a sequencer configured to output at least one spare multiplexor control signal, a memory, and a plurality of sensor inputs. At least one stimulation circuit is connected to a sensor signal line. The at least one stimulation circuit being connected to the at least one spare multiplexor control signal. The stimulation circuit is configured such that a state of the at least one spare multiplexor control signal controls a state of the stimulation circuit.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 7, 2020
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Lon R. Hoegberg
  • Patent number: 10606737
    Abstract: The present disclosure relates to the field of device testing. In one embodiment, a method is provided for testing a resource constrained device. The method includes determining a test case for testing the resource constrained device, and accessing a test script corresponding to the test case. The test script includes a set of mutually independent primitive executables. The method further includes transmitting each of the set of primitive executables to the resource constrained device for execution, and receiving a result corresponding to the execution of the each of the set of primitive executables.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 31, 2020
    Assignee: Wipro Limited
    Inventors: Souvik Dutta, Debasish Chanda, Swarup Mandal
  • Patent number: 10592068
    Abstract: A customer of a computing resource service provider may use an interface to access a graphical composer and generate one or more graphical representations of applications that may be provided to a variety of users of the customer's one or more resources. Once the customer has created a graphical representation of an application, a domain specific language model based at least on the graphical representation of the application may be created such that one or more simulations may be performed to determine whether the requested application includes any errors or conflicts. If the one or more simulations result in the application including no errors or conflicts, the domain specific language model may be compiled in an executable programming language to create the application. The application may then be provided to users who may utilize devices capable of understanding the executable programming language to install the application.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: March 17, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Khaled Salah Sedky, Ajith Harshana Ranabahu
  • Patent number: 10579758
    Abstract: Embodiments of present disclosure relates to a method and a system for implementation of user logic in a FPGA device. For the implementation, user logic is mapped onto cells of the FPGA device in implementation platform associated with FPGA device. The mapping is based on user logic constraints to be met and received for FPGA device. Further, mapped cells of FPGA device are placed in implementation platform based on local mapping optimization parameters. The placing also comprises of performing placement optimization on placed cells of FPGA device. Upon placement, placed cells of FPGA device are routed in implementation platform based on at least local mapping optimization parameters and local placement optimization parameters. The routing also comprises of performing routing optimization on routed cells of FPGA device.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 3, 2020
    Assignee: Wipro Limited
    Inventor: Kodavalla Vijay Kumar
  • Patent number: 10528698
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • Patent number: 10529909
    Abstract: A technique relates a superconducting microwave cavity. An array of posts has different heights in the cavity, and the array supports a localized microwave mode. The array of posts includes lower resonant frequency posts and higher resonant frequency posts. The higher resonant frequency posts are arranged around the lower resonant frequency posts. A first plate is opposite a second plate in the cavity. One end of the lower resonant frequency posts is positioned on the second plate so as to be electrically connected to the second plate. Another end of the lower resonant frequency posts in the array is open so as not to form an electrical connection to the first plate. Qubits are connected to the lower resonant frequency posts in the array of posts, such that each of the qubits is physically connected to one or two of the lower resonant frequency posts in the array of posts.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oliver Dial, Jay M. Gambetta, Douglas T. McClure, III, Matthias Steffen
  • Patent number: 10528699
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • Patent number: 10515168
    Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: December 24, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Pankaj P. Chauhan, Sameer Kapoor, Saurabh Jain, Kunal Bindal, Bryan D. Bowyer, Andres R. Takach, Peter P. Gutberlet, Gagandeep Singh, Maheshinder Goyal
  • Patent number: 10349172
    Abstract: A microphone apparatus is provided. The microphone apparatus includes a microphone cover; a circuit board, an integrated circuit, a first microphone, and a second microphone. The integrated circuit is coupled to the microphone cover and the circuit board to form a first chamber and a second chamber. The first microphone is placed inside the first chamber and configured to capture a first acoustic signal from a sound source. The second microphone is placed inside the second chamber and configured to capture a second acoustic signal from the sound source. The first microphone and the second microphone have the same sensitivity, phase, and omni-directivity. The integrated circuit performs a time-delay process on the second acoustic signal and subtracts the time-delayed second acoustic signal from the first acoustic signal to generate a differential signal. The integrated circuit forms a polar pattern of the microphone apparatus according to the differential signal.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 9, 2019
    Assignee: FORTEMEDIA, INC.
    Inventors: Yen-Son Paul Huang, Tsung-Lung Yang