Including Logic Patents (Class 703/15)
  • Patent number: 10796048
    Abstract: The independent claims of this patent signify a concise description of embodiments. A method of performing hardware emulation of a circuit design is presented. The method includes partitioning a first portion of the circuit design to a first configurable logic chip of a hardware emulator, adding a selection circuit to the circuit design in the first configurable logic chip, and selecting one of a first signal or a second signal during a first clock cycle. The first signal and the second signal are used in the circuit design. The method further includes storing a first value associated with the selected signal during a second clock cycle, and sending the first value to an output pin of the first configurable logic chip during a third clock cycle. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: October 6, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Nathaniel Azuelos, Alex Shot, Daniel Geist
  • Patent number: 10789118
    Abstract: The present invention provides an information processing device that improves the detectability of system errors. This information processing device includes: a means that generates a state graph based on relationship change information indicating a change in the relationship between a plurality of elements included in a system, the state graph having the elements as the vertices thereof and the relationship between the elements as the sides thereof; a means that generates a normal model having the state graph as a set of conditions to be fulfilled during normal system operation, based on the relationship change information; and a means that detects system errors and outputs error information indicating detected errors, based on the state graph and the normal model.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 29, 2020
    Assignee: NEC Corporation
    Inventors: Takashi Nomura, Koji Kida, Junpei Kamimura, Yoshiaki Sakae, Etsuko Katsuda, Kazuhiko Isoyama, Kentaro Yamasaki, Yuji Kobayashi
  • Patent number: 10783292
    Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: September 22, 2020
    Assignee: Pulsic Limited
    Inventors: Paul Clewes, Liang Gao, Jonathan Longrigg
  • Patent number: 10755026
    Abstract: A method of improving a design rule fixing process comprises receiving an integrated circuit design, including layout elements, and identifying a plurality of design rule violations in the integrated circuit design. The process then identifies a plurality of possible actions, each action comprising fixing a design rule. The process then uses a deep learning algorithm to select an action, the action representing fixing of a particular design rule violation. The process then comprises applying a first patch, based on the order returning to step (b) to select a next patch to apply.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 25, 2020
    Assignee: Synopsys, Inc.
    Inventor: Jianfeng Luo
  • Patent number: 10698805
    Abstract: A method for debugging a system on chip (SoC) under test, may include automatically inserting commands in a test code for testing the SoC for invoking printing of messages of data, each message of the messages including start time, end time of each executed action of a plurality of actions, the executed action to be invoked by the test code when testing the SoC, the data further including identity of a processing component of a plurality of processing components of the SoC, on which the executed action was executed; recording the data of the invoked printed messages during testing of the test code on the SoC; and displaying, via a graphical user interface, one or a plurality of graphical representations, each of said graphical representations relating to a period of activity of one of the plurality of processing components over time, based on the recorded data.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: June 30, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Meir Ovadia
  • Patent number: 10671774
    Abstract: A method for tailoring a bespoke processor includes generating first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application. The method includes gate cutting and stitching based on the first gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 2, 2020
    Assignees: Regents of the University of Minnesota, The Board of Trustees of the University of Illinois
    Inventors: Hari Cherupalli, Rakesh Kumar, John Sartori
  • Patent number: 10650323
    Abstract: Systems and methods are provided for coupling two flux qubits. A quantum circuit assembly includes a first flux qubit, having at least two potential energy minima, and a second flux qubit, having at least two potential energy minima. A system formed by the first and second qubits has at least four potential energy minima prior to coupling, each of the four potential energy minima containing at least one eigenstate of a system comprising the first flux qubit and the second flux qubit. A coupler creates a first tunneling path between a first potential energy minimum of the system and a second potential energy minimum of the system, and a second tunneling path between a third potential energy minimum of the system and a fourth potential energy minimum of the system. The coupler creates the first and second tunneling paths between potential energy minima representing states of equal bit parity.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 12, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Ryan J. Epstein, David George Ferguson
  • Patent number: 10635556
    Abstract: A device maintenance apparatus includes a setting operator configured to allow for setting a test pattern, the test pattern being set to define a change of output signals output from a device over time, and an execution operator configured to make the device output the output signals based on the set test pattern.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 28, 2020
    Assignee: Yokogawa Electric Corporation
    Inventors: Hirotaka Katayama, Hiromi Okamoto, Yuya Iketsuki
  • Patent number: 10613143
    Abstract: A controller system includes a microprocessor having a sequencer configured to output at least one spare multiplexor control signal, a memory, and a plurality of sensor inputs. At least one stimulation circuit is connected to a sensor signal line. The at least one stimulation circuit being connected to the at least one spare multiplexor control signal. The stimulation circuit is configured such that a state of the at least one spare multiplexor control signal controls a state of the stimulation circuit.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 7, 2020
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Lon R. Hoegberg
  • Patent number: 10606737
    Abstract: The present disclosure relates to the field of device testing. In one embodiment, a method is provided for testing a resource constrained device. The method includes determining a test case for testing the resource constrained device, and accessing a test script corresponding to the test case. The test script includes a set of mutually independent primitive executables. The method further includes transmitting each of the set of primitive executables to the resource constrained device for execution, and receiving a result corresponding to the execution of the each of the set of primitive executables.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 31, 2020
    Assignee: Wipro Limited
    Inventors: Souvik Dutta, Debasish Chanda, Swarup Mandal
  • Patent number: 10592068
    Abstract: A customer of a computing resource service provider may use an interface to access a graphical composer and generate one or more graphical representations of applications that may be provided to a variety of users of the customer's one or more resources. Once the customer has created a graphical representation of an application, a domain specific language model based at least on the graphical representation of the application may be created such that one or more simulations may be performed to determine whether the requested application includes any errors or conflicts. If the one or more simulations result in the application including no errors or conflicts, the domain specific language model may be compiled in an executable programming language to create the application. The application may then be provided to users who may utilize devices capable of understanding the executable programming language to install the application.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: March 17, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Khaled Salah Sedky, Ajith Harshana Ranabahu
  • Patent number: 10579758
    Abstract: Embodiments of present disclosure relates to a method and a system for implementation of user logic in a FPGA device. For the implementation, user logic is mapped onto cells of the FPGA device in implementation platform associated with FPGA device. The mapping is based on user logic constraints to be met and received for FPGA device. Further, mapped cells of FPGA device are placed in implementation platform based on local mapping optimization parameters. The placing also comprises of performing placement optimization on placed cells of FPGA device. Upon placement, placed cells of FPGA device are routed in implementation platform based on at least local mapping optimization parameters and local placement optimization parameters. The routing also comprises of performing routing optimization on routed cells of FPGA device.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 3, 2020
    Assignee: Wipro Limited
    Inventor: Kodavalla Vijay Kumar
  • Patent number: 10529909
    Abstract: A technique relates a superconducting microwave cavity. An array of posts has different heights in the cavity, and the array supports a localized microwave mode. The array of posts includes lower resonant frequency posts and higher resonant frequency posts. The higher resonant frequency posts are arranged around the lower resonant frequency posts. A first plate is opposite a second plate in the cavity. One end of the lower resonant frequency posts is positioned on the second plate so as to be electrically connected to the second plate. Another end of the lower resonant frequency posts in the array is open so as not to form an electrical connection to the first plate. Qubits are connected to the lower resonant frequency posts in the array of posts, such that each of the qubits is physically connected to one or two of the lower resonant frequency posts in the array of posts.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oliver Dial, Jay M. Gambetta, Douglas T. McClure, III, Matthias Steffen
  • Patent number: 10528699
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • Patent number: 10528698
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • Patent number: 10515168
    Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: December 24, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Pankaj P. Chauhan, Sameer Kapoor, Saurabh Jain, Kunal Bindal, Bryan D. Bowyer, Andres R. Takach, Peter P. Gutberlet, Gagandeep Singh, Maheshinder Goyal
  • Patent number: 10349172
    Abstract: A microphone apparatus is provided. The microphone apparatus includes a microphone cover; a circuit board, an integrated circuit, a first microphone, and a second microphone. The integrated circuit is coupled to the microphone cover and the circuit board to form a first chamber and a second chamber. The first microphone is placed inside the first chamber and configured to capture a first acoustic signal from a sound source. The second microphone is placed inside the second chamber and configured to capture a second acoustic signal from the sound source. The first microphone and the second microphone have the same sensitivity, phase, and omni-directivity. The integrated circuit performs a time-delay process on the second acoustic signal and subtracts the time-delayed second acoustic signal from the first acoustic signal to generate a differential signal. The integrated circuit forms a polar pattern of the microphone apparatus according to the differential signal.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 9, 2019
    Assignee: FORTEMEDIA, INC.
    Inventors: Yen-Son Paul Huang, Tsung-Lung Yang
  • Patent number: 10346273
    Abstract: Systems and methods are provided for an automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 9, 2019
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Courtney E. Fricano, Paul P. Wright, David Brownell
  • Patent number: 10289512
    Abstract: Embodiments relate to pre-silicon device testing using a persistent command table. An aspect includes receiving a value for a persistent command parameter from a user. Another aspect includes determining whether the value of the persistent command parameter is greater than zero. Another aspect includes based on determining whether the value of the persistent command parameter is greater than zero, selecting a number of commands equal to the value of the persistent command parameter from a regular command table of a driver of a device under test. Another aspect includes adding the selected commands to the persistent command table of the driver. Another aspect includes performing testing of the device under test via the driver using only commands that are in the persistent command table of the driver.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 14, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dean G. Bair, Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis, Chakrapani Rayadurgam
  • Patent number: 10268510
    Abstract: A device may receive one or more first objects and one or more second objects to be processed. The device may store, in a first queue, information identifying the one or more first objects, the one or more second objects, and an order in which the one or more first objects and the one or more second objects were received. The device may store, in a second queue, information identifying the one or more first objects based on the one or more first objects being associated with the first priority level. The device may process the one or more first objects and the one or more second objects based on the first queue and the second queue. The device may perform one or more actions based on processing the one or more first objects and the one or more second objects.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 23, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Amit Arora, Srinivasa DS
  • Patent number: 10262088
    Abstract: A method for converting real number modeling to cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, cleaning the real number modeling code in the file, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a non-transitory, computer readable medium to perform the above method are also provided.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 16, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ophir Turbovich, Yosinori Watanabe
  • Patent number: 10262095
    Abstract: A method for converting real number modeling to a cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, requesting a user input parameter, converting the file to a cycle-driven simulation interface file based on the user input parameter, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a computer readable medium to perform the above method are also provided.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 16, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ophir Turbovich, Yosinori Watanabe
  • Patent number: 10242149
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • Patent number: 10235485
    Abstract: Circuitry for the simulation of partial reconfiguration of a logic design for an integrated circuit device using a hybrid model is provided. The circuitry may create a hybrid model by combining structural model netlists of one or more partial reconfiguration partitions of the logic design with a behavioral model of a static partition of the logic design. The hybrid model may undergo partial reconfiguration verification to ensure that undefined signals do not bypass a freeze bridge and pass from registers in the partial reconfiguration partitions to the static partition, and to ensure that these registers are each in a defined state after the partial reconfiguration operation and a register reset operation are completed.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 19, 2019
    Assignee: Altera Corporation
    Inventors: Mahesh A. Iyer, Kalen B. Brunham
  • Patent number: 10228422
    Abstract: An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit. Execution of one or more scripts select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Debapriya Chatterjee, Shakti Kapoor, John A. Schumann
  • Patent number: 10169514
    Abstract: A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tsz-mei Ko, Jason D. Morsey, Steven E. Washburn, Patrick M. Williams
  • Patent number: 10161999
    Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: December 25, 2018
    Assignee: XILINX, INC.
    Inventors: Heera Nand, Niloy Roy, Mahesh Sankroj, Siddharth Rele, Riyas Noorudeen Remla, Rajesh Bansal, Bradley K. Fross
  • Patent number: 10133837
    Abstract: A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. The method further includes converting the cycle-driven simulation interface file into a register-transfer level file suitable to perform a circuit emulation in digital mixed signal environments, and verifying that the register-transfer level file is ready to perform circuit emulation in the digital mixed signal environments. A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 20, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ophir Turbovich, Yosinori Watanabe, Michael Young, Sean Dart
  • Patent number: 10109259
    Abstract: Disclosed herein is a method for displaying a monitoring viewer in an HMI system. The method includes, upon receiving a request to display a monitoring viewer from a user, acquiring screen data to be displayed in the monitoring viewer; displaying a control area of the monitoring viewer on a display; displaying a view area of the monitoring viewer on the display; and displaying a monitoring screen in the view area by using the screen data. The view area includes one or more taps. Monitoring performance and efficiency of the HMI system can be increased.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 23, 2018
    Assignee: LSIS CO., LTD.
    Inventors: Ae-Kyoung Bae, Shin-Jo Kong, Yeo-Chang Yoon, Seok-Chan Lee, Seung-Ju Lee
  • Patent number: 10089089
    Abstract: A device may receive input code that includes one or more input objects. The input code may be used in connection with generation of output code. The output code, when generated, may include one or more output objects, corresponding to and different than the one or more input objects. The device may receive or determine conversion information identifying a conversion operation to perform to generate the one or more output objects based on the one or more input objects. The conversion information may be received separately from the input code. The device may generate, based on the conversion information and the input code, an intermediate representation. The intermediate representation may include one or more annotations corresponding to the one or more input objects and defining the conversion operation. The device may compile, based on the intermediate representation, the output code. The device may execute or provide the output code.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 2, 2018
    Assignee: The MathWorks, Inc.
    Inventors: Anand Krishnamoorthi, Kiran K. Kintali, Ebrahim Mehran Mestchian, Srinivas Muddana
  • Patent number: 10084725
    Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 25, 2018
    Assignee: NETSPEED SYSTEMS, INC.
    Inventors: Pier Giorgio Raponi, Nishant Rao, Sailesh Kumar
  • Patent number: 10074792
    Abstract: Systems and methods are provided for a ZZZ coupler. A first tunable coupler is coupled to the first qubit and tunable via a first control signal. A second tunable coupler is coupled to the first tunable coupler to direct a flux of the first qubit into a tuning loop of the second tunable coupler, such that when a first coupling strength associated with the first tunable coupler is non-zero, a second coupling strength, associated with the second tunable coupler, is a function of a second control signal applied to the second tunable coupler and a state of the first qubit. The second qubit and the third qubit are coupled to one another through the second tunable coupler, such that, when the second coupling strength is non-zero it is energetically favorable for the states of the first and second qubits to assume a specific relationship with respect to the Z-axis.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 11, 2018
    Assignee: Northrop Grumman Systems Corporation
    Inventors: David George Ferguson, Anthony Joseph Przybysz, Joel D. Strand
  • Patent number: 10067854
    Abstract: Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes a simulation of the finite state machine representation. Execution of the simulation is suspended in response to the detecting the condition in the finite state machine.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Jason Villarreal, Kumar Deepak
  • Patent number: 10031178
    Abstract: A testing system includes a vacuum pump, testing equipment and a vibration device. A vacuum tray is configured to provide relative movement between a DUT and the vacuum pump, testing equipment and the vibration device. The vacuum tray includes a vacuum chamber configured to define a sealed vacuum environment around the DUT, and a DUT support carried by the vacuum chamber and configured to support the DUT within the chamber during testing thereof. The DUT support includes a pedestal configured to hold the DUT within the chamber during vibration testing, and an extension that extends outside the vacuum chamber and is configured to connect to the vibration device. An electrical test interface unit is carried by the vacuum chamber and configured to connect between the DUST and the test equipment, and a vacuum interface is carried by the vacuum chamber and configured to connect to the vacuum pump.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: July 24, 2018
    Assignee: Keysight Technologies, Inc.
    Inventor: David Henderson
  • Patent number: 9996637
    Abstract: A method for formally verifying a hardware/software co-design includes providing in a co-design, a first model, and a second model, the first model is one of a hardware model, and the second model is one of a software model, or vice versa, providing a safety property expected to be satisfied by the co-design, combining an abstraction of the first model and the safety property to obtain an abstracted first model, composing the abstracted first model and the second model to obtain a composed model, checking if the composed model satisfies the safety property, and signaling that the hardware/software co-design violates the safety property if the safety property is violated in the composed model.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventor: Mitra Purandare
  • Patent number: 9946624
    Abstract: A system for tracing an operation of an electronic circuit is provided. The system includes an electronic circuit, a trace buffer, and a trigger detection circuit. The trace buffer includes a plurality of segments configured to continually collect and store data signals of the electronic circuit. The data signals are collected in a current segment of the plurality of segments. The trigger detection circuit is adapted to provide a trigger signal when a trigger condition is met. Each time upon generation of the trigger signal when the trigger condition is met, the collection of the data signals is stopped in the current segment and subsequent data signals are collected in a new segment of the plurality of segments.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: April 17, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Alon Kfir
  • Patent number: 9940166
    Abstract: A system for allocating field-programmable gate array (FPGA) resources comprises a plurality of FPGAs operable to implement one or more pipeline circuits, the plurality of FPGAs comprising FPGAs of different processing capacities, and one or more processors operable to access a set of data comprising a plurality of work items to be processed according to a pipeline circuit associated with each of the plurality of work items, determine processing requirements for each of the plurality of work items based at least in part on the pipeline circuit associated with each of the plurality of work items, sort the plurality of work items according to the determined processing requirements, and allocate each of the plurality of work items to one of the plurality of FPGAs, such that no FPGA is allocated a work item with processing requirements that exceed the processing capacity of the FPGA.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: April 10, 2018
    Assignee: Bank of America Corporation
    Inventor: Steven A. Guccione
  • Patent number: 9874859
    Abstract: An initial data state is obtained for an adaptive system. A simulation is started for the adaptive system on an electronic computing device. A first trial is run of the simulation of the adaptive system until a first stop point is reached. When the first stop point is reached, one or more recursive simulations are run from the first stop point. After the one or more recursive simulations have been run, an optimized set of modified data states for the adaptive system at the first stop point is automatically determined. Using the optimized set of modified data states, the run of the first trial of the simulation is continued from the first stop point until either additional stop points are reached or the first trial of the simulation is completed. An additional set of optimized modified data states is determined for at least one of the additional stop points.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: January 23, 2018
    Assignee: Wells Fargo Bank, N.A.
    Inventor: Marco Paul Perzichilli
  • Patent number: 9870277
    Abstract: The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: January 16, 2018
    Assignee: D-Wave Systems Inc.
    Inventor: Andrew J. Berkley
  • Patent number: 9857865
    Abstract: A power measurement circuit is disclosed. The power measurement circuit comprises a sampling register, a latch generator, an accumulation unit, a calculation unit and an output register. The sampling register samples an input signal based on a sampling clock to generate a binary digit. The latch generator generates a latch signal based on the sampling clock and a measurement interval. The accumulation unit accumulates the binary digit based on the latch signal to generate a sum value. The calculation unit calculates an ON-phase rate of the input signal according to the sum value and the measurement interval. The output register stores a power consumption value according to the ON-phase rate of the input signal.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: January 2, 2018
    Assignee: Aspeed Technology Inc.
    Inventors: Chung-Yen Lu, Hung-Ming Lin
  • Patent number: 9830133
    Abstract: Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least one local memory unit that allows for data reuse opportunities. The first custom computing apparatus optimizes the code for reduced communication execution on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 28, 2017
    Assignee: Significs and Elements, LLC
    Inventors: Muthu Baskaran, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache
  • Patent number: 9823689
    Abstract: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 21, 2017
    Inventor: Laurence H. Cooke
  • Patent number: 9779192
    Abstract: Methods and systems are disclosed related to multi-rate parallel circuit simulation. In one embodiment, a computer implemented method of partitioning the circuit into a plurality of partitions, wherein each partition is represented by a set of linear differential equations, determining a simulation time step for each partition of the plurality of partitions, grouping the plurality of partitions into multiple groups, wherein each group includes one or more partitions having simulation time steps within a predefined range of each other, and solving the multiple groups with their corresponding simulation time steps in parallel.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: October 3, 2017
    Assignee: PROPLUS DESIGN SOLUTIONS, INC.
    Inventors: Bruce W. McGaughy, Zhenzhong Zhang, Jun Fang
  • Patent number: 9753752
    Abstract: The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: September 5, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Handong Ye, Peng Zhao, Senhuo Zheng, Jiong Cao
  • Patent number: 9753798
    Abstract: A method and system for automatically auditing an electronic component design process comprising a plurality of design steps. The method includes: extracting, optionally in parallel and in a single pass, a plurality of non-error data types from obtained electronic component design information to produce one or more summary files; and determining whether an audit failure exists in a current design step of the plurality of design steps based on a comparison of the one or more summary files with one or more stored failure indicators. The one or more stored failure indicators comprising a plurality of non-error triggers associated with later failures. The present disclosure simplifies the organization of the gathered data to prevent the automated electronic design process from generating an inferior design, which wastes time of both human and computing resources.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: September 5, 2017
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Jon Haldorson, Joseph Rhodes, Gwyneth Morrison, Kevin Clements
  • Patent number: 9747396
    Abstract: An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Debapriya Chatterjee, Shakti Kapoor, John A. Schumann
  • Patent number: 9727432
    Abstract: Apparatus and method for accelerated testing of a multi-device storage system. In some embodiments, the storage system includes a server adapted to communicate with a user device, and a plurality of data storage devices adapted to store and retrieve data objects from the user device. The server maintains a map structure that describes the data objects stored on the data storage devices. A fault injection module is adapted to induce simulated failures of selected data storage devices in relation to a time-varying failure rate distribution associated with the data storage devices that indicates an observed failure rate over a first time interval. The simulated failures are induced by the fault injection module over a second time interval shorter than the first time interval. The server operates to modify the map structure responsive to the simulated failures.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: August 8, 2017
    Assignee: Seagate Technology LLC
    Inventors: Craig F. Cutforth, Ajaykumar Rajasekharan, Rajaram Singaravelu
  • Patent number: 9727685
    Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 8, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Yan Wang, Chenchen Wang, Jongwook Kye
  • Patent number: 9729130
    Abstract: A method can include receiving an input signal having multiple signal edges, performing an initial scan of the input signal to identify peaks corresponding to the signal edges, and determining whether each peak is a Uniformly Synchronous (US) edge or a Quasi-Synchronous (QS) edge. The method can also include generating a final waveform and displaying the final waveform on a display device.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 8, 2017
    Assignee: Tektronix, Inc.
    Inventor: Jonathan D. Clem
  • Patent number: 9715566
    Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: July 25, 2017
    Assignee: Zipalog, Inc.
    Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu