Including Logic Patents (Class 703/15)
  • Patent number: 10346273
    Abstract: Systems and methods are provided for an automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 9, 2019
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Courtney E. Fricano, Paul P. Wright, David Brownell
  • Patent number: 10349172
    Abstract: A microphone apparatus is provided. The microphone apparatus includes a microphone cover; a circuit board, an integrated circuit, a first microphone, and a second microphone. The integrated circuit is coupled to the microphone cover and the circuit board to form a first chamber and a second chamber. The first microphone is placed inside the first chamber and configured to capture a first acoustic signal from a sound source. The second microphone is placed inside the second chamber and configured to capture a second acoustic signal from the sound source. The first microphone and the second microphone have the same sensitivity, phase, and omni-directivity. The integrated circuit performs a time-delay process on the second acoustic signal and subtracts the time-delayed second acoustic signal from the first acoustic signal to generate a differential signal. The integrated circuit forms a polar pattern of the microphone apparatus according to the differential signal.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 9, 2019
    Assignee: FORTEMEDIA, INC.
    Inventors: Yen-Son Paul Huang, Tsung-Lung Yang
  • Patent number: 10289512
    Abstract: Embodiments relate to pre-silicon device testing using a persistent command table. An aspect includes receiving a value for a persistent command parameter from a user. Another aspect includes determining whether the value of the persistent command parameter is greater than zero. Another aspect includes based on determining whether the value of the persistent command parameter is greater than zero, selecting a number of commands equal to the value of the persistent command parameter from a regular command table of a driver of a device under test. Another aspect includes adding the selected commands to the persistent command table of the driver. Another aspect includes performing testing of the device under test via the driver using only commands that are in the persistent command table of the driver.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 14, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dean G. Bair, Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis, Chakrapani Rayadurgam
  • Patent number: 10268510
    Abstract: A device may receive one or more first objects and one or more second objects to be processed. The device may store, in a first queue, information identifying the one or more first objects, the one or more second objects, and an order in which the one or more first objects and the one or more second objects were received. The device may store, in a second queue, information identifying the one or more first objects based on the one or more first objects being associated with the first priority level. The device may process the one or more first objects and the one or more second objects based on the first queue and the second queue. The device may perform one or more actions based on processing the one or more first objects and the one or more second objects.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 23, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Amit Arora, Srinivasa DS
  • Patent number: 10262095
    Abstract: A method for converting real number modeling to a cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, requesting a user input parameter, converting the file to a cycle-driven simulation interface file based on the user input parameter, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a computer readable medium to perform the above method are also provided.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 16, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ophir Turbovich, Yosinori Watanabe
  • Patent number: 10262088
    Abstract: A method for converting real number modeling to cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, cleaning the real number modeling code in the file, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a non-transitory, computer readable medium to perform the above method are also provided.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 16, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ophir Turbovich, Yosinori Watanabe
  • Patent number: 10242149
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • Patent number: 10235485
    Abstract: Circuitry for the simulation of partial reconfiguration of a logic design for an integrated circuit device using a hybrid model is provided. The circuitry may create a hybrid model by combining structural model netlists of one or more partial reconfiguration partitions of the logic design with a behavioral model of a static partition of the logic design. The hybrid model may undergo partial reconfiguration verification to ensure that undefined signals do not bypass a freeze bridge and pass from registers in the partial reconfiguration partitions to the static partition, and to ensure that these registers are each in a defined state after the partial reconfiguration operation and a register reset operation are completed.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 19, 2019
    Assignee: Altera Corporation
    Inventors: Mahesh A. Iyer, Kalen B. Brunham
  • Patent number: 10228422
    Abstract: An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit. Execution of one or more scripts select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Debapriya Chatterjee, Shakti Kapoor, John A. Schumann
  • Patent number: 10169514
    Abstract: A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tsz-mei Ko, Jason D. Morsey, Steven E. Washburn, Patrick M. Williams
  • Patent number: 10161999
    Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: December 25, 2018
    Assignee: XILINX, INC.
    Inventors: Heera Nand, Niloy Roy, Mahesh Sankroj, Siddharth Rele, Riyas Noorudeen Remla, Rajesh Bansal, Bradley K. Fross
  • Patent number: 10133837
    Abstract: A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. The method further includes converting the cycle-driven simulation interface file into a register-transfer level file suitable to perform a circuit emulation in digital mixed signal environments, and verifying that the register-transfer level file is ready to perform circuit emulation in the digital mixed signal environments. A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 20, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ophir Turbovich, Yosinori Watanabe, Michael Young, Sean Dart
  • Patent number: 10109259
    Abstract: Disclosed herein is a method for displaying a monitoring viewer in an HMI system. The method includes, upon receiving a request to display a monitoring viewer from a user, acquiring screen data to be displayed in the monitoring viewer; displaying a control area of the monitoring viewer on a display; displaying a view area of the monitoring viewer on the display; and displaying a monitoring screen in the view area by using the screen data. The view area includes one or more taps. Monitoring performance and efficiency of the HMI system can be increased.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 23, 2018
    Assignee: LSIS CO., LTD.
    Inventors: Ae-Kyoung Bae, Shin-Jo Kong, Yeo-Chang Yoon, Seok-Chan Lee, Seung-Ju Lee
  • Patent number: 10089089
    Abstract: A device may receive input code that includes one or more input objects. The input code may be used in connection with generation of output code. The output code, when generated, may include one or more output objects, corresponding to and different than the one or more input objects. The device may receive or determine conversion information identifying a conversion operation to perform to generate the one or more output objects based on the one or more input objects. The conversion information may be received separately from the input code. The device may generate, based on the conversion information and the input code, an intermediate representation. The intermediate representation may include one or more annotations corresponding to the one or more input objects and defining the conversion operation. The device may compile, based on the intermediate representation, the output code. The device may execute or provide the output code.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 2, 2018
    Assignee: The MathWorks, Inc.
    Inventors: Anand Krishnamoorthi, Kiran K. Kintali, Ebrahim Mehran Mestchian, Srinivas Muddana
  • Patent number: 10084725
    Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 25, 2018
    Assignee: NETSPEED SYSTEMS, INC.
    Inventors: Pier Giorgio Raponi, Nishant Rao, Sailesh Kumar
  • Patent number: 10074792
    Abstract: Systems and methods are provided for a ZZZ coupler. A first tunable coupler is coupled to the first qubit and tunable via a first control signal. A second tunable coupler is coupled to the first tunable coupler to direct a flux of the first qubit into a tuning loop of the second tunable coupler, such that when a first coupling strength associated with the first tunable coupler is non-zero, a second coupling strength, associated with the second tunable coupler, is a function of a second control signal applied to the second tunable coupler and a state of the first qubit. The second qubit and the third qubit are coupled to one another through the second tunable coupler, such that, when the second coupling strength is non-zero it is energetically favorable for the states of the first and second qubits to assume a specific relationship with respect to the Z-axis.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 11, 2018
    Assignee: Northrop Grumman Systems Corporation
    Inventors: David George Ferguson, Anthony Joseph Przybysz, Joel D. Strand
  • Patent number: 10067854
    Abstract: Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes a simulation of the finite state machine representation. Execution of the simulation is suspended in response to the detecting the condition in the finite state machine.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Jason Villarreal, Kumar Deepak
  • Patent number: 10031178
    Abstract: A testing system includes a vacuum pump, testing equipment and a vibration device. A vacuum tray is configured to provide relative movement between a DUT and the vacuum pump, testing equipment and the vibration device. The vacuum tray includes a vacuum chamber configured to define a sealed vacuum environment around the DUT, and a DUT support carried by the vacuum chamber and configured to support the DUT within the chamber during testing thereof. The DUT support includes a pedestal configured to hold the DUT within the chamber during vibration testing, and an extension that extends outside the vacuum chamber and is configured to connect to the vibration device. An electrical test interface unit is carried by the vacuum chamber and configured to connect between the DUST and the test equipment, and a vacuum interface is carried by the vacuum chamber and configured to connect to the vacuum pump.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: July 24, 2018
    Assignee: Keysight Technologies, Inc.
    Inventor: David Henderson
  • Patent number: 9996637
    Abstract: A method for formally verifying a hardware/software co-design includes providing in a co-design, a first model, and a second model, the first model is one of a hardware model, and the second model is one of a software model, or vice versa, providing a safety property expected to be satisfied by the co-design, combining an abstraction of the first model and the safety property to obtain an abstracted first model, composing the abstracted first model and the second model to obtain a composed model, checking if the composed model satisfies the safety property, and signaling that the hardware/software co-design violates the safety property if the safety property is violated in the composed model.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventor: Mitra Purandare
  • Patent number: 9946624
    Abstract: A system for tracing an operation of an electronic circuit is provided. The system includes an electronic circuit, a trace buffer, and a trigger detection circuit. The trace buffer includes a plurality of segments configured to continually collect and store data signals of the electronic circuit. The data signals are collected in a current segment of the plurality of segments. The trigger detection circuit is adapted to provide a trigger signal when a trigger condition is met. Each time upon generation of the trigger signal when the trigger condition is met, the collection of the data signals is stopped in the current segment and subsequent data signals are collected in a new segment of the plurality of segments.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: April 17, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Alon Kfir
  • Patent number: 9940166
    Abstract: A system for allocating field-programmable gate array (FPGA) resources comprises a plurality of FPGAs operable to implement one or more pipeline circuits, the plurality of FPGAs comprising FPGAs of different processing capacities, and one or more processors operable to access a set of data comprising a plurality of work items to be processed according to a pipeline circuit associated with each of the plurality of work items, determine processing requirements for each of the plurality of work items based at least in part on the pipeline circuit associated with each of the plurality of work items, sort the plurality of work items according to the determined processing requirements, and allocate each of the plurality of work items to one of the plurality of FPGAs, such that no FPGA is allocated a work item with processing requirements that exceed the processing capacity of the FPGA.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: April 10, 2018
    Assignee: Bank of America Corporation
    Inventor: Steven A. Guccione
  • Patent number: 9874859
    Abstract: An initial data state is obtained for an adaptive system. A simulation is started for the adaptive system on an electronic computing device. A first trial is run of the simulation of the adaptive system until a first stop point is reached. When the first stop point is reached, one or more recursive simulations are run from the first stop point. After the one or more recursive simulations have been run, an optimized set of modified data states for the adaptive system at the first stop point is automatically determined. Using the optimized set of modified data states, the run of the first trial of the simulation is continued from the first stop point until either additional stop points are reached or the first trial of the simulation is completed. An additional set of optimized modified data states is determined for at least one of the additional stop points.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: January 23, 2018
    Assignee: Wells Fargo Bank, N.A.
    Inventor: Marco Paul Perzichilli
  • Patent number: 9870277
    Abstract: The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: January 16, 2018
    Assignee: D-Wave Systems Inc.
    Inventor: Andrew J. Berkley
  • Patent number: 9857865
    Abstract: A power measurement circuit is disclosed. The power measurement circuit comprises a sampling register, a latch generator, an accumulation unit, a calculation unit and an output register. The sampling register samples an input signal based on a sampling clock to generate a binary digit. The latch generator generates a latch signal based on the sampling clock and a measurement interval. The accumulation unit accumulates the binary digit based on the latch signal to generate a sum value. The calculation unit calculates an ON-phase rate of the input signal according to the sum value and the measurement interval. The output register stores a power consumption value according to the ON-phase rate of the input signal.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: January 2, 2018
    Assignee: Aspeed Technology Inc.
    Inventors: Chung-Yen Lu, Hung-Ming Lin
  • Patent number: 9830133
    Abstract: Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least one local memory unit that allows for data reuse opportunities. The first custom computing apparatus optimizes the code for reduced communication execution on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 28, 2017
    Assignee: Significs and Elements, LLC
    Inventors: Muthu Baskaran, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache
  • Patent number: 9823689
    Abstract: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 21, 2017
    Inventor: Laurence H. Cooke
  • Patent number: 9779192
    Abstract: Methods and systems are disclosed related to multi-rate parallel circuit simulation. In one embodiment, a computer implemented method of partitioning the circuit into a plurality of partitions, wherein each partition is represented by a set of linear differential equations, determining a simulation time step for each partition of the plurality of partitions, grouping the plurality of partitions into multiple groups, wherein each group includes one or more partitions having simulation time steps within a predefined range of each other, and solving the multiple groups with their corresponding simulation time steps in parallel.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: October 3, 2017
    Assignee: PROPLUS DESIGN SOLUTIONS, INC.
    Inventors: Bruce W. McGaughy, Zhenzhong Zhang, Jun Fang
  • Patent number: 9753798
    Abstract: A method and system for automatically auditing an electronic component design process comprising a plurality of design steps. The method includes: extracting, optionally in parallel and in a single pass, a plurality of non-error data types from obtained electronic component design information to produce one or more summary files; and determining whether an audit failure exists in a current design step of the plurality of design steps based on a comparison of the one or more summary files with one or more stored failure indicators. The one or more stored failure indicators comprising a plurality of non-error triggers associated with later failures. The present disclosure simplifies the organization of the gathered data to prevent the automated electronic design process from generating an inferior design, which wastes time of both human and computing resources.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: September 5, 2017
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Jon Haldorson, Joseph Rhodes, Gwyneth Morrison, Kevin Clements
  • Patent number: 9753752
    Abstract: The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: September 5, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Handong Ye, Peng Zhao, Senhuo Zheng, Jiong Cao
  • Patent number: 9747396
    Abstract: An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Debapriya Chatterjee, Shakti Kapoor, John A. Schumann
  • Patent number: 9729130
    Abstract: A method can include receiving an input signal having multiple signal edges, performing an initial scan of the input signal to identify peaks corresponding to the signal edges, and determining whether each peak is a Uniformly Synchronous (US) edge or a Quasi-Synchronous (QS) edge. The method can also include generating a final waveform and displaying the final waveform on a display device.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 8, 2017
    Assignee: Tektronix, Inc.
    Inventor: Jonathan D. Clem
  • Patent number: 9727432
    Abstract: Apparatus and method for accelerated testing of a multi-device storage system. In some embodiments, the storage system includes a server adapted to communicate with a user device, and a plurality of data storage devices adapted to store and retrieve data objects from the user device. The server maintains a map structure that describes the data objects stored on the data storage devices. A fault injection module is adapted to induce simulated failures of selected data storage devices in relation to a time-varying failure rate distribution associated with the data storage devices that indicates an observed failure rate over a first time interval. The simulated failures are induced by the fault injection module over a second time interval shorter than the first time interval. The server operates to modify the map structure responsive to the simulated failures.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: August 8, 2017
    Assignee: Seagate Technology LLC
    Inventors: Craig F. Cutforth, Ajaykumar Rajasekharan, Rajaram Singaravelu
  • Patent number: 9727685
    Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 8, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Yan Wang, Chenchen Wang, Jongwook Kye
  • Patent number: 9715566
    Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: July 25, 2017
    Assignee: Zipalog, Inc.
    Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
  • Patent number: 9697306
    Abstract: A computer program product includes program instructions to: Receive a unit including register transfer level content for a component of an integrated circuit and one or more IP blocks; Select one or more input pins for each IP block; Assign a numerical value of either zero or one to each of the one or more input pins to yield at least one numerical sequence; For each numerical sequence, perform a check to yield a number of fails, wherein the check is formal verification of each of the one or more IP blocks; Determine a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails; Set the one or more input pins to the simulation condition for power modeling of the unit; and Determine a number of design errors of the unit based on the simulation condition.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao
  • Patent number: 9696894
    Abstract: Embodiments of the present invention are directed to a method and system for developing an analytic process. The method includes displaying, within an electronic system, a plurality of components operable to be used for designing a data analysis process. A user makes a selection of a data access component from the plurality of components. The data access component is operable for configuring access to a data source. The method further includes the user making a selection of a data selection component from the plurality of components and a data display component. The data selection component is operable for selecting data accessed via the data access component. The data display component is operable for configuring display of data based on the data selection component. Configuration data corresponding to the data access component, the data selection component, and the data display component can then be stored.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 4, 2017
    Assignee: Accenture Global Services Limited
    Inventor: David Martin Hummel, Jr.
  • Patent number: 9697304
    Abstract: A graphical model may include a plurality of graphical objects representing physical elements, and connections between graphical objects may be represented by physical connection lines. A set of physical connections between two or more graphical objects may be configured as belonging to a group. A switching unit may toggle the graphical model between a single-line display mode and a multi-line display mode. In the multi-line display mode, each of the individual physical connection lines linking two or more graphical objects are displayed in the model. In response to user or other input, the switching unit may redraw the graphical model in single line mode in which the individual physical connections configured as a group are replaced with a single, composite connection line. The graphical model may be executable to simulate the physical system, and the execution may be unaffected by the display mode.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: July 4, 2017
    Assignee: The MathWorks, Inc.
    Inventors: Jeffrey M. Wendlandt, Andrew C. Bennett
  • Patent number: 9697321
    Abstract: A method for identifying a value of an unknown circuit component for an analog signal having a known output profile in which a simulation list of the analog circuit is first created including the component with the unknown value. A transfer function for the known output value is then created using a programmed processor and the transfer function is then solved by the processor for the value of the unknown component. For nonlinear circuit components, a linear model is substituted for the nonlinear components prior to creating the simulation list.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: July 4, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Yuan Xiao, Donald J. McCune, Can Wang, Heming Chen, Sujit Phatak, Yasuhiro Ito
  • Patent number: 9659118
    Abstract: Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a signal is indicated and propagated through digital logic circuits represented in a disclosed semantic to enable prompt detection of improper operation of the DUT, for example, due to power shut down or inadequate initialization.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: May 23, 2017
    Assignee: Synopsys, Inc.
    Inventors: Alexander Rabinovitch, Ludovic Marc Larzul
  • Patent number: 9600613
    Abstract: Various example implementations are directed to methods and systems for simulating circuit designs having configuration parameters. According to one example implementation, code blocks of a circuit design for which execution of operations described by the code blocks is conditioned on a value of one or more of a set of configuration parameters, are identified. For each identified code block, a respective expression is determined that indicates whether or not the code block will be executed for different sets of values of the set of configuration parameters. The circuit design is simulated for a first set of values for the configuration parameters. The simulation is performed using a model that omits code blocks that describe sets of operations that will not be executed. The determined expressions are evaluated to determine whether or not each identified code block was realized in the simulation model.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 21, 2017
    Assignee: XILINX, INC.
    Inventor: Kyle Corbett
  • Patent number: 9589088
    Abstract: Various example implementations are directed to circuits and methods for partitioning a memory for a circuit design in a programmable IC. A user interface is provided for a user to define subsystems, master circuits, memory segments, and permissions for accessing the memory segments by the master circuits. For each defined memory segment, a respective access control entry is generated that includes data for determining master circuits that are permitted access to the memory segment by the user-defined permissions. A first portion of configuration data is generated that is configured to cause a memory management circuit in the programmable IC to enforce access to address ranges, corresponding to the respective memory segments, in a memory of the programmable IC according to the respective access control entries. A second portion of configuration data is generated that is configured to cause programmable resources of the programmable IC to implement the circuit design.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: March 7, 2017
    Assignee: XILINX, INC.
    Inventors: Pradeep Kumar Mishra, Gangadhar Budde, Somdutt Javre, Siddharth Rele
  • Patent number: 9589115
    Abstract: An obfuscation assisting apparatus assists in the obfuscation of a program. The obfuscation assisting apparatus includes an analyzer which identifies corresponding respective blocks in the source code and in the transformed code generated through the obfuscation of the source code. A browser obtains obfuscation information relating to obfuscation of the respective blocks of the source code and the transformed code, and causes an output device to display the respective parts of the source code and the transformed code, and the obfuscation information in association with each other.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: March 7, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kenneth Alexander Nicolson, Rieko Asai, Taichi Sato, Hideki Matsushima
  • Patent number: 9507898
    Abstract: A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: November 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Santosh Balasubramanian, Aaron C. Brown, David W. Cummings, Ambalath Matayambath Roopesh
  • Patent number: 9501608
    Abstract: Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Yanai Danan, Vasant B. Rao, Xin Zhao
  • Patent number: 9483593
    Abstract: Described is a method performed by a computing device, the method comprises: deriving a hierarchal structure of hardware instances of a hardware block, wherein the hardware block is described in a register transfer language (RTL); determining complexity of at least one hardware instance, in the hierarchal structure, with reference to a complexity metric; identifying, in response to the determined complexity of the at least one hardware instance, whether the at least one hardware instance is to be modeled; and modifying the hierarchal structure with information about the to be modeled hardware instance.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventors: Robert Hartung, Matthias Glueck
  • Patent number: 9471726
    Abstract: Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: October 18, 2016
    Assignee: NETSPEED SYSTEMS
    Inventors: Sailesh Kumar, Amit Patankar, Eric Norige
  • Patent number: 9454466
    Abstract: A methods, apparatus and product for explaining partially illegal combinations in combinatorial models. The method comprising: obtaining a combinatorial model defining a legal test space, the combinatorial model comprising a set of attributes, a respective domain for each attribute defining possible values for the attribute, and a set of restrictions, wherein the restrictions define a combination of values of the attributes that are illegal and are excluded from the legal test case; obtaining a partially illegal combination defining value assignments to a portion of the attributes; automatically identifying an extension of the partially illegal combination, wherein the extension is excluded from the legal test space, wherein the extension can be modified to become legal by changing a portion of the value assignments defined by the partially illegal combination; and outputting the extension.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alexander Ivrii, Itai Segall, Rachel Tzoref-Brill
  • Patent number: 9411569
    Abstract: A system, method and computer-readable storage devices for providing a climate data analytic services application programming interface distribution package. The example system can provide various components. The system provides a climate data analytic services application programming interface library that enables software applications running on a client device to invoke the capabilities of a climate data analytic service. The system provides a command-line interface that provides a means of interacting with a climate data analytic service by issuing commands directly to the system's server interface. The system provides sample programs that call on the capabilities of the application programming interface library and can be used as templates for the construction of new client applications. The system can also provide test utilities, build utilities, service integration utilities, and documentation.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: August 9, 2016
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: John L. Schnase, Daniel Q. Duffy, Glenn S. Tamkin
  • Patent number: 9330757
    Abstract: An electronic device comprising a semiconductor memory unit that may include a cell array including a plurality of storage cells; a first line connected to one ends of the plurality of storage cells; a second line connected to the other ends of the plurality of storage cells; a first driver connected to one end of the first line at a first contact location on one side of the cell array, and configured to apply a first electrical signal to the one end of the first line; and a second driver connected to one end of the second line at a second contact location on a side of the cell array opposing the side of the cell array where the first contact location is located, and configured to apply a second electrical signal to the one end of the second line.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 3, 2016
    Assignee: SK hynix Inc.
    Inventor: Dong-Keun Kim
  • Patent number: 9300544
    Abstract: Methods and arrangements for identifying and characterizing subgraphs of a network. In a network comprising a plurality of nodes and edges, there is identified a subgraph including a plurality of nodes. Communication workload closure of the subgraph is calculated via: identifying and counting all length-2 paths in the network that include at least one of the nodes of the subgraph, each length-2 path including three nodes and two edges interconnecting the three nodes; for each of the length-2 paths, determining whether all three nodes belong to the subgraph; thereupon identifying and counting a subset of the length-2 paths wherein, for each path in the subset, all three nodes of the path belong to the subgraph; and dividing the number of paths in the subset by the total number of length-2 paths that include at least one of the nodes of the subgraph. Other variants and embodiments are broadly contemplated herein.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Seema Nagar, Amit Anil Nanavati, Raghavendra Singh