Abstract: A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.

Abstract: Computer-aided design tools analyze a custom logic design for a programmable logic device integrated circuit. The tools identify distinct clock domains in the design. The tools also identify which of the clock domains are synchronous. The tools examine the synchronous clock domains to determine which of the clock domains have required fixed phase relationships. Clocks for clock domains that do not have required fixed relationships can be adjusted in phase to minimize power supply simultaneous switching noise. Noise may be minimized by making clock phase adjustments using a programmable phase-locked loop circuit.

Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Abstract: A system that determines the performance of an integrated circuit (IC). During operation, the system receives probability distributions for parameters for the IC. Next, the system generates samples of the IC, wherein generating a given sample involves using the probability distribution to assign values to the parameters for components within the IC. The system then calculates output performance metrics for the samples based on the assigned values of the parameters, and uses the calculated output performance metrics to generate a distribution of output performance metrics for the samples.

Abstract: A modular instance-aware event-driven test framework is described. It includes an event-driven test framework, a transition-graph test model for the event-driven text framework, an instance-aware event-driven test framework built on said event-driven test framework and a transition-graph test model for said instance-aware event-driven test framework built on said transition-graph test model.

Abstract: A method for generating test cases for software and a test case generator comprising a simulator that drives software under test from one input state to the next. The simulator is constrained by predetermined criteria to visit states that meet the criteria thus preserving computer resources. The states reached by the simulator are tested.

Abstract: The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.

Abstract: A process and system for estimating the soft error rate of an integrated circuit. The process involves determining the surface area of and charge stored on each logic node on the integrated circuit. Then a response curve is used to estimate the soft error rate for a logic node using the charge stored on the logic node. Different response curves exist for integrated circuits of different technologies and products. Finally, the soft error rate of the integrated circuit can be estimated using the soft error rates for each logic node.

Abstract: A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function.

Abstract: A simulation that integrates historical data and real-time data as a test or simulation tool can capture an entry that relates to a desired output as function points. A determination can intellectually be made as to which activities can achieve the desired output. The activities can be process steps that can represent a workflow that can be automatically implemented by an MES Appliance or other enterprise components. If a simulation reveals that the desired output might not be achieved, a change to one or more function points can be analyzed in an attempt to achieve the desired result. This change can be input into a simulation tool through a feedback loop, for example. Another simulation can performed on the modified data until a determination is made that the desired output can be achieved.

Abstract: Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.

Abstract: A software-controlled chemical process emulation system and environment having individually-addressable and/or group-addressable software-controlled chemical system processing modules, software-controlled chemical system handling modules, and related components. The software-controlled modules may be designed and interconnected to emulate various fixed, configurable, and reconfigurable “Lab-on-a-Chip” (“LoC”) devices. The software-controlled modules may be designed as separate units with well-defined ports and interfaces that can be used in the construction of larger systems. Alternatively, the software-controlled modules may be integrated into more complex subsystems that can be used in similar or other ways. These aspects may be used to design a LoC device, develop software for the operation of a LoC device, or may be used together with actual LoC devices as part of a larger system.

Abstract: A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

Abstract: Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps.

Abstract: Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks.

Abstract: Each node in a communication system operates on a repetitive internal timing cycle, at certain phases in which the node transmits data and state variable signals. The state variable signals indicate the node's data transmission timing. Each node has a virtual node calculator that simulates the timing cycles of neighboring nodes according to the state variable signals received from those nodes, and a phase calculator that varies the phase state of the node according to the simulated phase states of the neighboring nodes. Neighboring nodes can therefore interact continuously, even though they transmit state variable signals only intermittently. Consequently, a group of neighboring nodes can autonomously establish and maintain transmission time slots of equal length.

Abstract: An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators. A software debugger interface permits a software application to be loaded and executed on the virtual embedded system. A virtual test bench may be coupled to the simulation to serve as a human-machine interface. In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project. IP components, such as processor cores, may be evaluated using a virtual embedded system. In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system.

Abstract: A method for providing independent static and dynamic models in a prediction, control and optimization environment utilizes an independent static model (20) and an independent dynamic model (22). The static model (20) is a rigorous predictive model that is trained over a wide range of data, whereas the dynamic model (22) is trained over a narrow range of data. The gain K of the static model (20) is utilized to scale the gain k of the dynamic model (22). The forced dynamic portion of the model (22) referred to as the bi variables are scaled by the ratio of the gains K and k. The bi have a direct effect on the gain of a dynamic model (22). This is facilitated by a coefficient modification block (40). Thereafter, the difference between the new value input to the static model (20) and the prior steady-state value is utilized as an input to the dynamic model (22). The predicted dynamic output is then summed with the previous steady-state value to provide a predicted value Y.

Abstract: A network troubleshooting framework is described. In an implementation, a method includes generating a first estimation of network performance by a simulator based on network settings obtained from a network, estimating the new performance under an alternative setting by providing the alternative setting to the network simulation and observing the simulation output, repeating the procedure for other alternative settings, and suggesting the alternative setting that improves network performance.

Abstract: The invention provides methods for enhancing circuit reliability under statistical process variation. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may induce a not-so-rare system failure. To combat this, the invention discloses the method called “Statistical Blockade,” a Monte Carlo-type technique that allows the efficient filtering—blocking—of unwanted samples insufficiently rare in the tail distributions of interest, with speedups of 10-100×. Additionally, the core Statistical Blockade technique is further extended in a “recursive” or “bootstrap” formulation to create even greater efficiencies under a much wider variety of circuit performance metrics, in particular two-sided metrics such a Data Retention Voltage (DRV) which prior Monte Carlo techniques could not handle.

Abstract: An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time.

Abstract: A simulation apparatus that performs simulation of design data of a verification target circuit including a logic circuit that operates as a multi-cycle path of N cycles in synchronization with a clock signal, the simulation apparatus includes a design data generation section that generates design data of a multi-cycle verification circuit for selectively providing an undefined value signal in place of a signal in a multi-cycle part in the verification target circuit; a logical simulation section that performs logical simulation, without delay, on the basis of design data of the verification target circuit and the design data of the multi-cycle verification circuit; and a comparison section that compares the signal of the verification target circuit with a signal of an expected value in the verification target circuit in the logical simulation.

Abstract: A method includes grouping cells with similar topological characteristics into a family of cells, the topological characteristics being defined in part by topological layouts of transistors in the respective cells in the family of cells; and computing data characterizing a relationship between a variability of delay and a magnitude of delay shared among the cells in the family of cells.

Abstract: A method for rapidly simulating combined analog circuits and digital circuits includes separating the combined circuits into a linear sub-network and logic sub-network. Shared nodes, shared by the linear sub-network and logic sub-network, are identified. The values of the shared nodes represent logic state values, or digital values, in the logic sub-network, and represent voltages, currents, control inputs and/or circuit parameters in the linear sub-network. Operation of the logic sub-network is simulated using logic node values for the shared nodes. Operation of the linear sub-network is simulated using linear node values for the shared nodes. The method allows fast simulation and rapid revision of mixed signal designs, saving design time and computing resources.

Abstract: A method and system is provided for generator successor nodes in an external-memory search of a graph having a plurality of nodes and outgoing edges of the plurality of nodes. The method and system includes construction of an abstract representation of the graph to include a set of abstract nodes and abstract outgoing edges of the abstract set of nodes. The edges of the graph are partitioned based on the abstract representation of the graph. The partitioning includes grouping edges (or instantiated operators of a search problem) that map to the same abstract edge of the abstract representation together as isomorphic edges. Successor nodes along outgoing edges that belong to the same group are generated consecutively. By this design, partial and incremental expansion of nodes can be achieved in order to limit the number of time-consuming I/O (or other communication) operations in search algorithms that take advantage of the memory hierarchy in a computer system, such as those that use disk storage.

Abstract: An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same module need not be re-simulated when it has the same input combination as the prior circuit module instance. The results computed earlier for the earlier circuit module instance can be re-used for the current circuit module instance.

Abstract: A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated properties (P0, P1, . . . Pn) of the form Pi=(forall t. Ai(t)=>Zi(t)), wherein Ai(t) present an initial state and Zi(t) a target state for a corresponding property and at least one initial state Ai is dependant on internal signals and including a step for checking whether at least one aspect of the input/output behaviour of the machine described by the properties, which cannot be derived from an individual property Pi, is described to such an accurate extent that one property Q exists, which represents this aspect without being dependant on the internal signals. The procedure is capable of providing a measurement and can particularly be used in the verification and specification of circuits.

Abstract: Simulating device interactions. A method may be practiced in a computing system for simulating interconnected devices. The method of simulating device interactions may be done in performing an overall transaction to obtain an output of system performance characteristics including measurement of latencies and/or device loads for actions performed by devices in performing the overall transaction. The method includes dividing a transaction into individual actions. The actions are applied to appropriate device models to produce latencies and/or device utilizations for the action as applied to the appropriate device model. This may be done by including an indication of an action type and optionally an action subservice. Memory resources may be conserved by ending the simulation when latencies and/or device utilizations have settled. Device utilization and latency may be aggregated and averaged over time.

Abstract: A processing architecture and methods therein for building application specific array processing utilizing a sequential data bus for control and data propagation. The methods of array processing provided by the architecture allows for numerical analysis of large numerical data such as simulation, image processing, computer modeling or other numerical functions. The architecture is unlimited in scalability and facilitates mixed mode processing of idealized, analytical and real data, in conjunction with real time input and output.

Abstract: The invention concerns a method for testing immunity to noise derived from interferences between components in a mixed analogic and digital electronic system. The method comprises determining by simulating the highest-level noise observed in the system, or the worst noise generated by interferences. If a test for noise sensitivity is successful with this injected worst noise, then the system is accepted. In the case where the worst noise test fails, the method comprises calculating by simulating the lowest-level noise observed in the system, or the injected best noise. If a test for noise sensitivity fails with this injected best signal, then the system is rejected.

Abstract: A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock attributes. The method includes maintaining a data structure for time-scheduled events scheduled to occur at particular simulation-times; and maintaining a data structure for clock-scheduled events each corresponding to a particular clock signal and scheduled to occur at a time that can be determined from at least one attribute of the clock signal, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure.

Abstract: Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.

Abstract: A verification apparatus that efficiently performs hardware verification and software verification in the development of a system LSI with great accuracy. At the hardware verification, an equivalence verification section compares the result of the simulation of an HDL model by a logic simulator and an expected value generated from an expected value calculation model and verifies whether there is equivalence between them. At the software verification, the expected value calculation model is used via an interface section and a firmware is verified by a software debugger. The expected value calculation model is used as an expected value generation model at hardware verification time and is used as a C model of hardware at software verification time. By using the expected value calculation model both for the hardware verification and for the software verification in this way, verification can efficiently be performed with great accuracy.

Abstract: A method for determining system and software configuration that includes: calculating a power consumption estimate of a modeled system associated with an execution of a certain software code; and altering, in response to the power consumption estimate, the certain software code or the modeled system. A method of determining a power consumption of a system that executed a software code, the method includes the stages of: providing a reduced instruction set representation of the software code; and calculating a power consumption estimate of a modeled system associated with an execution of the reduced instruction set representation of the software code.

Abstract: Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.

Abstract: An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time.

Abstract: In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered priority. Events for the device under test may be determined for event regions in each of the kernels. An event region to execute events in is then determined and all kernels may execute events in the same event region. Kernels then execute events for the determined event region. When finished executing events in the event queue, data synchronization may occur. In this case, information may be synced among kernels, such as status and state values for shared objected are synchronized.

Abstract: Disclosed are an apparatus and a method for modeling a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). The method includes establishing an equation and a variable that determine the driving current characteristics of the MOS transistor; generating a random number; converting the random number such that the random number has a value satisfying an equation of a rotated lozenge and determining a variation degree of the variable based on the value of the random number; and outputting the driving current distribution of the MOS transistor using the equation and the variation degree of the variable.

Abstract: According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.

Abstract: A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in an implementation tool. The violation context data includes violation information other than violation location/path information. Because the signoff tool, and more specifically, the signoff algorithm used by that tool is the most accurate model of actual IC behavior, the use of violation context data generated by the signoff tool to implement changes to the design layout will generally produce appropriate and effective results. By accessing this violation context data from the signoff tool, an implementation tool need not rely on its less accurate implementation analysis to determine the optimal design layout modifications for correcting violations detected by the signoff tool.

Abstract: Methods for generating waveforms with realistic transitions, controllable timing jitter, and controllable amplitude noise in a computer-based simulation environment are disclosed. A first method includes obtaining signal information for one or more parallel data signals. In one embodiment, signal information for the one or more parallel data signals is mapped from an HDL format to a new time scale, and during this operation, timing jitter is added independently to the parallel data signals. These jittery parallel data signals may then be returned to the original HDL format, or another format, for simulation. In another embodiment, rather than mapping to a single time vector, information from each signal is modified to have a time scale commensurate with noise and jitter to be added. Timing jitter is superimposed onto each transition, rise and fall times are incorporated, and missing voltage and timing information for each data signal is interpolated into vectors representing the signals.

Abstract: A system, method, and computer program product for approximating intrinsic capacitance of an integrated circuit (IC) block such as, for example, a compliable memory instance. Estimates of N-well capacitance, metal grid capacitance, and non-switching circuitry capacitance associated with the IC block are obtained. A total intrinsic capacitance of the IC block is then estimated based on the aforesaid constituent estimates.

Abstract: A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.

Abstract: An authoring, execution, and participation software system and corresponding method for the capture and execution of real-world events (e.g., crises) involving individuals such as senior private and/or public sector leaders is presented. The authoring system and method are used to model a scenario, incorporating knowledge from domain experts, relevant media, and external computation/simulation engines. The execution system and method execute scenarios created by the authoring system and method and provide a communication hub for the participation system and method. The participation system and method provide individuals, such as senior leaders and their staff, with appropriate views into the unfolding scenario and appropriate decisions to be made. The system and method also include features that allow for research and analysis with respect to, for example, efficient crisis response tactics.

Abstract: A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the output drivers and used to calibrate their output impedances is provided proximate to the output drivers. A state machine is used to query each output model, and to set the proper output enable signals for the enable transistors in the output drivers in each group so as to calibrate their output impedances. By decentralizing the output models, the process used to form the output models will, due to proximity to the output drivers in each group, be indicative of the process used to form the output drivers. Thus, when each group of output drivers is calibrated, the output models used for each will compensate for process variations as may occur across the surface of the integrated circuit.

Abstract: A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow.

Abstract: According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.

Abstract: A method and a design structure. The method includes: generating a board model of a circuit board design; generating a impedance spectrum of the board model; generating a chip model of an integrated circuit chip design; performing a transient analysis of the chip model using an ideal board power supply to generate an initial chip noise signature; based on the transient analysis, adding noise generators to the board model to generate a modified board model and to generate a latest board power supply; performing an additional transient analysis of the chip model using the modified board model and the latest board power supply to generate a latest noise signature; determining if the latest noise signature is within a predetermined chip noise specification; and if the latest noise signature is not within the predetermined chip noise specification, adding at least one decoupling capacitor to the modified board model.

Abstract: The present invention generally relates to microfluidics and more particularly to the design of customized microfluidic systems using a microfluidic computer aided design system. In one embodiment of the present invention a microfluidic circuit design method is provided. The method includes developing synthesizable computer code for a design. Next, a microfluidic circuit schematic, including a plurality of symbols for microfluidic components, is generated either interactively or using the synthesizable computer code. The microfluidic circuit schematic is then functionally simulated. The microfluidic components are placed and routed on a template to form a physical layout. Then the physical layout is physically simulated using dynamic simulation models of the microfluidic components; and the physical layout is written to a layout file.

Abstract: A hardware-block constraint specification method includes defining a plurality of hardware-block constraint categories according to at least one of type of constraint and constraint operating mode and defining a plurality of hardware-block constraint commands. Each of the plurality of hardware-block constraint commands is categorized into one of the plurality of hardware-block constraint categories. The method also includes encapsulating the plurality of hardware-block constraint commands within a plurality of modules usable, via an application programming interface, in a stand-alone mode or an integrated mode.