Circuit Simulation Patents (Class 703/14)
  • Patent number: 11368400
    Abstract: Application data may be transmitted while oscillating a transmission parameter. A metric associated with a complementary network property is analyzed to identify a transition point between a stochastic error state and a deterministic error state of the complementary network property. Additional network properties or states may be inferred from the transition point, and the transmission of the application data may be optimized based on the inferred additional properties or states.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 21, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Stephen Daniel Vilke, James Morgan Selvidge, Rudy Willis, Paul Hinks
  • Patent number: 11360743
    Abstract: An example of the instant solution comprises at least one of receiving an encrypted data and an encryption key, generating a randomized matrix, dispersing the encrypted data based on the randomized matrix resulting in a fragmented encrypted data and dispersing the encryption key based on the randomized matrix and the fragmented encrypted data.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 14, 2022
    Assignee: Cyber Reliant Corp.
    Inventors: Katelynn Marie Linthicum, John Michael Suit, Ian Spencer Bartelt Becker
  • Patent number: 11354476
    Abstract: There is a significant precaution when performing random dopant fluctuation by using the drift-diffusion model that is the basis of the conventional device simulation. Because the continuation by a long wavelength approximation was done to derive said drift-diffusion model. That is how to recover the location dependence of discrete impurity ions in the long wavelength approximation. For example, in the case that there is an impurity ion near to the interface to an insulating film, the charge density of an impurity ion, which was made continuous in the conventional method, is unable to catch the charge density change due to polarization at the interface. Because this polarization is dependent of the location of a discrete impurity ion near to the interface.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: June 7, 2022
    Inventor: Hiroshi Watanabe
  • Patent number: 11315237
    Abstract: An image is obtained by using a charged particle beam, and a design layout information is generated to select patterns of interest. Grey levels among patterns can be compared with each other to identify abnormal, or grey levels within one pattern can be compared to a determined threshold grey level to identify abnormal.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: April 26, 2022
    Assignee: ASML Netherlands B.V.
    Inventor: Wei Fang
  • Patent number: 11308250
    Abstract: In an embodiment, a data processing method comprises storing one or more generic machine operating definitions, wherein each of the generic machine operating definitions describes expected operational behavior of one or more types of machines during one or more operating states; analyzing operating data that describes past operation of a plurality of machines of a plurality of types; based at least in part on the operating data and the one or more generic machine operating definitions, generating and storing one or more machine operating models that describe expected operational behavior corresponding to a plurality of operating states of the plurality of machines; wherein the one or more machine operating models comprise a plurality of data patterns, wherein each of the data patterns is associated with a different set of one or more operating states of one or more machines; wherein the method is performed by one or more computing devices.
    Type: Grant
    Filed: September 8, 2019
    Date of Patent: April 19, 2022
    Assignee: Falkonry Inc.
    Inventors: Nikunj R. Mehta, Prasanta Bose
  • Patent number: 11295831
    Abstract: A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ankita Patidar, Sandeep Kumar Goel
  • Patent number: 11288339
    Abstract: Systems and methods are provided for generating a state space model of a physical system. Embodiments of a computer-implemented system may include a physical system data structure that includes frequency-domain response data that is indicative of a response of one or more components of a physical system to a stimulus, and a state space model generation engine that is configured generate a state space model based on the frequency-domain response data, where the state space model is usable to simulate a time-domain response of the one or more components of the physical system.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 29, 2022
    Assignee: Ansys, Inc.
    Inventor: Amit Hochman
  • Patent number: 11281829
    Abstract: A device, system, and method performs an adaptive simulation. The method performed by a similar includes receiving a release to be incorporated into a user device, the user device being a deployed device. The method includes receiving a profile of the user device, the profile being indicative of settings and usage information of the user device. The method includes generating a simulated user device corresponding to the user device, the simulated user device having a simulated profile corresponding to the profile. The method includes performing, by the simulator, a simulation for the release based upon the simulated user device and the simulated profile.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 22, 2022
    Assignee: Wind River Systems, Inc.
    Inventors: Assaf Namer, Anton Langebner
  • Patent number: 11255894
    Abstract: Detecting a counterfeit status of a target utility device by: selecting a set of frequencies that best reflect load dynamics or other information content of a reference utility device while undergoing a power test sequence; obtaining target electromagnetic interference (EMI) signals emitted by the target utility device while undergoing the same power test sequence; creating a sequence of target kiviat plots from the amplitude of the target EMI signals at each of the set of frequencies at observations over the power test sequence to form a target kiviat tube EMI fingerprint; comparing the target kiviat tube EMI fingerprint to a reference kiviat tube EMI fingerprint for the reference utility device undergoing the power test sequence to determine whether the target utility device and the reference utility device are of the same type; and generating a signal to indicate a counterfeit status based at least in part on the results of the comparison.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: February 22, 2022
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Edward R. Wetherbee, Rui Zhong, Kenny C. Gross, Guang C. Wang
  • Patent number: 11249888
    Abstract: One embodiment provides a system and method for identifying invariants in a software system. During operation, the system executes a test suite comprising a plurality of tests associated with the software system to output a list of likely invariants in the software system, and performs a test-generation operation attempting to generate counterexample tests for the likely invariants. In response to a counterexample test being successfully generated for a first likely invariant, the system removes the first likely invariant from the list of likely invariants and adds the successfully generated counterexample test to the test suite.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 15, 2022
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Alexandre Campos Perez, Eric A. Bier, Johan de Kleer, Ron Z. Stern
  • Patent number: 11250560
    Abstract: Disclosed herein is method for multi-perspective-based wafer analysis. The method includes (i) scanning a plurality of pages, or portions thereof, one after the other, wherein each page, or a portion thereof, is successively scanned, in each of a multiplicity of perspectives, and (ii) analyzing scan data of a last scanned page while scanning a next page from the plurality of pages. At least some of the pages include multiple slices of the wafer. The analysis of the scan data includes identifying defects in the scanned pages, based on an integrated analysis combining scan data from each of the multiplicity of perspectives. Further disclosed is a computerized system configured to implement the method.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: February 15, 2022
    Assignee: Applied Materials Israel Ltd.
    Inventors: Doron Korngut, Ido Almog
  • Patent number: 11244096
    Abstract: Embodiments include simulating a design under test on an electronic device. Aspects include running a test program on the design under test and capturing inputs into the design under test. Aspects also include storing the inputs into the design under test in a storage device. Responsive to determining that an event has occurred during execution of the test program, aspects include halting the test program on the design under test. Aspects further include enabling a user via a user interface to determine a cause of the event by performing a simulation of the design under test using the inputs stored in the storage device.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael James Becht, Christopher J. Colonna, Stephen Robert Guendert, Pasquale A. Catalano
  • Patent number: 11243503
    Abstract: A building management system includes building equipment operable to affect a variable state or condition of a building and a control system configured to receive a user input indicating a model form. The model form includes a plurality of matrices having a plurality of elements defined in terms of a plurality of parameters. The control system is configured to parse the model form to generate a sequence of machine-executable steps for determining a value of each of the plurality of elements based on a set of potential parameter values, identify a system model by executing the sequence of machine-executable steps to generate a set of parameter values for the plurality of parameters, generate a graphical user interface that illustrates a fit between predictions of the identified system model and behavior of the variable state or condition of the building, and control the building equipment using the identified system model.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: February 8, 2022
    Assignee: Johnson Controls Tyco IP Holdings LLP
    Inventors: Andrew J. Przybylski, Michael J. Wenzel, Matthew J. Ellis
  • Patent number: 11240169
    Abstract: Various example embodiments relate generally to supporting queuing of packets in a communication network. Various example embodiments for supporting queuing of packets in a communication network may be configured to support queueing of packets based on a packet queuing memory space including a hash entry space configured to maintain a set of H hash entries and a packet queue space configured to maintain a set of Q packet queues, wherein H is greater than Q. Various example embodiments for supporting queuing of packets in a communication network may be configured to support queueing of packets in a manner for handling packet events (e.g., packet arrival events, packet departure events, or the like) while preventing or mitigating queue collisions of hash entries (where a queue collision occurs when multiple hash entries, and the respective network flows of those hash entries, are associated with a single packet queue).
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 1, 2022
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Francini, Sameerkumar Sharma
  • Patent number: 11222159
    Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: January 11, 2022
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Heiko Kalte, Dominik Lubeley
  • Patent number: 11200146
    Abstract: Software verification is a vital process to ensure reliability and robustness of software systems. The software verification is associated with verifying one or more properties associated with a piece of code. Conventional methods are unable to verify properties of piece of code with loops, especially in the presence of loops with a large, unknown or infinite bound, or a large number of complex conditions. The system receives an abstracted piece of code corresponding to an original piece of code to check whether the abstracted piece of code hence the original piece of code is safe or not. The system applies model checking over the abstracted piece of code to check one or more property assertions associated with an abstracted piece of code. If the property assertion fails in model checking, a trace leading to the violation of the one or more property assertions is identified and analyzed.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: December 14, 2021
    Assignee: Tata Consultancy Services Limited
    Inventors: Priyanka Darke, Tanha Shah, Venkatesh Ramanathan
  • Patent number: 11200362
    Abstract: Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 14, 2021
    Assignee: Synopsys, Inc.
    Inventors: Hua Song, Cheng En Wu, James P. Shiely
  • Patent number: 11200361
    Abstract: A method, system and computer program product for appending abstractions to a testbench used for verifying the design of an electronic circuit. According to an embodiment of the invention, a method comprises identifying a set L of one or more support properties l for a set P of one or more properties p for a given electronic circuit; computing a plurality of hardware signals s of the given electronic circuit; and creating a plurality of abstract signals ABS, including declaring a fresh abstract signal abs_s for each of the hardware signals s, and creating a fresh abstract signal abs_l for each of the support properties l of the set L; for each of the properties p of the set P, creating an abstract property version abs_p; and appending the abstract signals ABS and the abstract property abs_p to the testbench to form an appended testbench.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bradley Donald Bingham, Viresh Paruthi, Steven Mark German
  • Patent number: 11188705
    Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: November 30, 2021
    Assignee: Synopsys, Inc.
    Inventors: Tao-Chun Yu, Hsien-Shih Chiu, Shao-Yun Fang, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
  • Patent number: 11188687
    Abstract: A method and apparatus for checking compliance of a design for a product with design rules. An executable rule module comprising the design rules is received. The design rules comprise design checking rules that specify conditions. Design data representing the design is received. The executable rule module is run using the design data to determine compliance of the design with the design rules by determining whether the design satisfies the conditions. A compliance report to indicate the compliance of the design with the design rules is generated. The design data may be used to manufacture the product in response to a determination that the design complies with the design rules.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 30, 2021
    Assignee: The Boeing Company
    Inventors: Christopher Esposito, Jeff Alan Heisserman
  • Patent number: 11176298
    Abstract: The present disclosure provides a method for modeling, including: S1): designing a test key having a source, a drain, and a gate, and testing the test key to obtain test data; S2): extracting a model parameter according to the test data; S3): verifying reasonableness of a physical characteristic of the model parameter based on a relationship between a source-drain voltage and a drain current, if the reasonableness passes the verification, a model file is established and the method proceeds to S4), if the reasonableness fails the verification, the method returns to S2) to adjust the model parameter, until the reasonableness passes the verification; S4): performing quality assurance on the model file, if the model file passes the quality assurance, the modeling is completed, if the model file fails the quality assurance, the method returns to S2) to adjust the model parameter until the model file passes the quality assurance.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: November 16, 2021
    Assignee: CHINA FLASH CO., LTD.
    Inventors: Hong Nie, Ke Wu, Xiang Su
  • Patent number: 11163664
    Abstract: A system and method to verify software includes a debugger setting a breakpoint in the software. The breakpoint indicates a point at which to pause or stop execution of the software. The method also includes setting one or more anchor points associated with the breakpoint. Each of the one or more anchor points represents another point in the software that must be executed prior to pausing or stopping the execution of the software at the breakpoint.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiao Ling Chen, Chuan He, Yan Huang, Jiang Yi Liu, Wei Wu, Jian Xu
  • Patent number: 11163661
    Abstract: Test case generation for a hardware state space including: identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generating a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Madhusudan Kadiyala, Narasimha R. Adiga, Manoj Dusanapudi
  • Patent number: 11157673
    Abstract: A field programmable gate array (FPGA) having at least first and second processing circuits implemented thereon. Each of the first and second processing circuits comprises a numerical core and associated peripheral components. The numerical core in the first processing circuit is dissimilar to the numerical core in the second processing circuit. The first and second processing circuits are segregated from each other in floorplan view.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 26, 2021
    Assignee: RATIER-FIGEAC SAS
    Inventor: Arnaud Bouchet
  • Patent number: 11151294
    Abstract: One or more embodiments disclosed herein pertain to a hybrid emulation system for hybrid emulation of a design under test (DUT). The system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hardware emulation system includes emulated registers for the first portion of the DUT. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. The hybrid emulation system additionally comprises a configuration file that identifies a subset of the emulated registers. The simulation system is configured with the configuration file to selectively mirror, during the hybrid emulation, the subset of the emulated registers identified by the configuration file.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 19, 2021
    Assignee: Synopsys, Inc.
    Inventors: Andreas Gerd Ropers, Sylvain Bayon de Noyer, Alexandru Fiodorov, Filip Constant Thoen, Markus Wedler
  • Patent number: 11144695
    Abstract: A wafer characteristic prediction method and an electronic device are provided. The method includes: receiving a process parameter of a wafer during a mass production; inputting the process parameter to a prediction model to obtain a wafer characteristic of the wafer being mass produced; and outputting the wafer characteristic.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 12, 2021
    Assignee: DigWise Technology Corporation, LTD
    Inventors: JingJie Wu, Yuan-Hung Liao, Chih-Chen Liu
  • Patent number: 11144027
    Abstract: Soft error data describing soft errors predicted to affect at least a particular hardware component of a computing system are used to determine functional safety metric values. The computing system is to control at least a portion of physical functions of a machine using the particular hardware component. Respective soft error rates are determined for each of a set of classifications based on the soft errors described in the soft error data. Derating of the soft error rates are performed based on a set of one or more vulnerability factors to generate derated error rate values for each of the set of classifications. The functional safety metric value is determined from the derated error rate values to perform a functional safety analysis of the computing system.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Giuseppe Capodanno, Jyotika A. Athavale, Riccardo Mariani
  • Patent number: 11144329
    Abstract: A processing unit employs microcode wherein the jump table associated with the microcode is embedded in the microcode itself. When the microcode is compiled based on a set of programmer instructions, the compiler prepares the jump table for the microcode and stores the jump table in the same file or other storage unit as the microcode. When the processing unit is initialized to execute a program, such as an operating system, the processing unit retrieves the microcode corresponding to the program from memory, stores the microcode in a cache or other memory module for execution, and automatically loads the embedded jump table from the microcode to a specified set of jump table registers, thereby preparing the processing unit to process received packets.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 12, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Alexander Fuad Ashkar, Rakan Khraisha, Rex Eldon McCrary, Harry J. Wise
  • Patent number: 11138358
    Abstract: A method includes receiving a circuit design including a plurality of components associated with a plurality of component parameters. The method further includes adjusting a value of a particular component parameter of the plurality of component parameters based on a tolerance to generate a modified plurality of component parameters. The method further includes determining, based on inputting the modified plurality of component parameters into a circuit calculator, that an operating value of the circuit design is sensitive to the particular component parameter. The method further includes selecting a simulation of the circuit design to perform based on the particular component parameter. The method further includes performing the simulation to determine whether the circuit design supports one or more design limits.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pradeep Kumar Chawda, Shrikrishna Srinivasan, Mac Dien, Ning Dong, Makram Monzer Mansour, Jeffrey Robert Perry
  • Patent number: 11137440
    Abstract: A self-heating effect apparatus includes a memory and a processor. The processor is coupled to the memory and configured to process a self-heating effect model for characterizing a heat flow network of devices. The devices include a device under test and one or more adjacent devices surrounding the device under test. The self-heating effect model includes a reference thermal resistance and a reference thermal capacity; a thermal temperature feedback model used to acquire a thermal level of the device under test; a thermal resistance modification model used to acquire a modified thermal resistance of the device under test according to the thermal level of the device under test and the reference thermal resistance; and a thermal capacity modification model used to acquire a modified thermal capacity of the device under test according to the thermal level of the device under test and the reference thermal capacity.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 5, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xi Lin, Yi Hua Shen, Sen Sheng Li
  • Patent number: 11132790
    Abstract: The invention provides a wafer map identification method, which includes the following steps: obtaining a wafer map of at least one to-be-identified wafer; performing an image processing operation on the wafer map and a reference pattern, wherein the image processing operation includes: performing a convolution operation on the wafer map and the reference pattern respectively, extracting a critical feature of the wafer map after the convolution operation, and calculating a weight distribution based on the reference pattern after the convolution operation; and calculating a similarity between the processed wafer map and the processed reference pattern to identify the wafer map. The invention also provides a computer-readable recording medium recording the above identification method.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: September 28, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chiu-Chieh Lin, Ching-Ly Yueh
  • Patent number: 11127136
    Abstract: A system for defining flexible regions on a sample is disclosed. The system includes an inspection system configured to acquire one or more swath images. The system includes a controller communicatively coupled to the inspection system, the controller configured to: generate one or more median reference die (MRD) images based on the one or more swath images; generate one or more flexible region masks based on the one or more MRD images; identify a set of alignment sites on the one or more flexible region masks based on one or more coordinates of the one or more MRD images; perform patch-to-mask alignment between the one or more flexible region masks and one or more scan images by aligning the scan images and the one or more MRD images at the identified set of alignment sites; and position the one or more flexible region masks on the scan images.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: September 21, 2021
    Assignee: KLA Corporation
    Inventors: Yong Zhang, Tao Luo, Jie Gong, Premchandra M. Shankar
  • Patent number: 11128296
    Abstract: The present disclosure provides a method and a device for simulation of a CMOS radio frequency switch and a communication terminal. The method includes: receiving a first value; obtaining a current value of a first function based on the first value, when the CMOS radio frequency switch is in an on-state, the value of the first function is a first function value, and when the CMOS radio frequency switch is in an off-state, the value of the first function is a second function value; receiving a second value; receiving a third value; outputting an off-state capacitance value of the CMOS radio frequency switch based on the second value and the third value; and outputting an on-state resistance value of the CMOS radio frequency switch based on the second value, the third value and the current value of the first function.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: September 21, 2021
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Xiangquan Fan
  • Patent number: 11119890
    Abstract: A computer-implemented method for instruction-level tracing for analyzing processor failure includes detecting a failure during operation of a processor circuit. The method further includes parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure. The method further includes generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace. The method further includes performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times. The method further includes using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Saurabh Chadha, Daniel Lewis, Diyanesh B. Chinnakkonda Vidyapoornachary
  • Patent number: 11106486
    Abstract: Techniques to manage virtual classes for statistical tests are described. An apparatus may comprise a simulated data component to generate simulated data for a statistical test, statistics of the statistical test based on parameter vectors to follow a probability distribution, a statistic simulator component to simulate statistics for the parameter vectors from the simulated data with a distributed computing system comprising multiple nodes each having one or more processors capable of executing multiple threads, the simulation to occur by distribution of portions of the simulated data across the multiple nodes of the distributed computing system, and a distributed control engine to control task execution on the distributed portions of the simulated data on each node of the distributed computing system with a virtual software class arranged to coordinate task and sub-task operations across the nodes of the distributed computing system. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 31, 2021
    Assignee: SAS INSTITUTE INC.
    Inventors: Xilong Chen, Mark Roland Little
  • Patent number: 11097485
    Abstract: A system and method for resource estimation of an additive manufacturing device is disclosed herein. The system includes at least one processor and one or more software modules. The processor executes the one or more software modules to determine a number of parts that can be manufactured per manufacturing run, estimate manufacturing time to manufacture a specified number of parts, and determine a total cost to manufacture the number of parts with the additive manufacturing device. The one or more software modules can compare the total cost to the cost of a current manufacturing method.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 24, 2021
    Assignee: Solar Turbines Incorporated
    Inventors: Tyler Boveington, Branden Elam, Timothy Evans, Greg Balow, Drew Dominique
  • Patent number: 11100268
    Abstract: Embodiments are generally directed to a hierarchical approach for performing simulation for PDNs that have integrated VRMs. According to certain aspects, embodiments include an approach that decouples the simulation for PDN and the simulation for VRM/PKG through PDN macromodeling. In these and other embodiments, the approach includes a SPICE-accurate simulation for the VRM part using a non-linear solver and using a linear solver for the PDN part, with minimal handshaking between them. For example, using a Backward Euler method having a fixed time step, at every simulation time interval, the linear solver sends reduced boundary currents to the non-linear solver. After the non-linear solver converges at the time interval, it sends boundary voltages back to the linear solver for determining voltages in the PDN part at the time interval.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 24, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Zhiyu Zeng, Hailin Jiang, Yanfei Gu, Nityanand Rai, Xin Gu
  • Patent number: 11101905
    Abstract: A method for operating a data processing system to generate an estimate of radiative contamination at nodes in an RF circuit characterized by a plurality of circuit elements connected by metal traces on a circuit board are disclosed. The data processing system to receive information specifying a coupled radiation matrix based on the metal traces and a simulation of an RF circuit with the components connected by non-radiating nodes. The data processing system generates a coupled power list for at least one node of the model, each entry in the coupled power list includes a coupled power value indicating a power level received by EM radiation from another of the nodes.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: August 24, 2021
    Assignee: Keysight Technologies, Inc.
    Inventors: Rulon Van Dyke, Tong Zhou Wu
  • Patent number: 11080122
    Abstract: Examples described herein provide a computer-implemented method that includes executing, by the microprocessor, instructions in an instruction stream of the microprocessor. The method further includes triggering, by control logic of the microprocessor, error condition monitoring logic. The method further includes executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Larry Leitner, John A. Schumann, Debapriya Chatterjee, Wallace Sharp, Bryant Cockcroft
  • Patent number: 11075815
    Abstract: A network building apparatus (2) includes a collection unit (11) configured to scan each node connected to a network and collect environmental data of the network, a design unit (21) configured to design a virtual network obtained by virtualizing the network based on the environmental data collected by the collection unit (11), and an output unit (31) configured to output design data of the virtual network designed by the design unit (21).
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 27, 2021
    Assignee: NEC CORPORATION
    Inventor: Tatsuya Ito
  • Patent number: 11074385
    Abstract: A method for simulating a hierarchical circuit includes a bottom-up process and a top-down process in each of a series of iteration rounds. The bottom-up process starts from a bottom level of the hierarchical circuit and obtains submatrices and subvectors for each subcircuit instance (SCI) in the hierarchical circuit. For each SCI, after obtaining first and second submatrices and first and second subvectors of the each SCI, the second submatrix and the second subvector are passed up to the next level in the hierarchy and used to calculate the circuit equation for a parent SCI in the next level. In the top-down process, starting at a top circuit, signal values in each level of the hierarchical circuit are determined. Certain signal values of a parent SCI are passed down to each child SCI, and are used to determine the internal signal values of the child SCI together with the first submatrix and the first subvector of the child SCI.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: July 27, 2021
    Assignee: ICEE Solutions LLC
    Inventor: Henry Hongwei Cao
  • Patent number: 11042981
    Abstract: In one embodiment, a computing system may access design data of a printed circuit board to be produced by a first manufacturing process. The system may analyze the design data of the printed circuit board using a machine-learning model, wherein the machine-learning model is trained based on X-ray inspection data associated with the first manufacturing process. The system may automatically determine one or more corrections for the design data of the printed circuit board based on the analysis result by the machine-learning model.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: June 22, 2021
    Assignee: SVXR, Inc.
    Inventors: David Lewis Adler, Freddie Erich Babian, Scott Joseph Jewler
  • Patent number: 11035666
    Abstract: Systems and methods for determining location of critical dimension (CD) measurement or inspection are disclosed. Real-time selection of locations to take critical dimension measurements based on potential impact of critical dimension variations at the locations can be performed. The design of a semiconductor device also can be used to predict locations that may be impacted by critical dimension variations. Based on an ordered location list, which can include ranking or criticality, critical dimension can be measured at selected locations. Results can be used to refine a critical dimension location prediction model.
    Type: Grant
    Filed: February 25, 2018
    Date of Patent: June 15, 2021
    Assignee: KLA-Tencor Corporation
    Inventors: Jagdish Chandra Saraswatula, Arpit Yati, Hari Pathangi
  • Patent number: 11030162
    Abstract: A distributed processing management apparatus analyzes a source file, extracts a reference item name of a reference item that is referenced in processing, and then generates a deletion program describing a process of deleting, from each of plural records, data of a non-reference item having an item name other than the reference item name. Further, the distributed processing management apparatus generates an insertion program describing a process of inserting, in each of the records, dummy data in the position where the data of the non-reference item was located. Then, the distributed processing management apparatus causes plural servers to execute distributed parallel processing based on processing program. When transmitting records, the servers delete data from the records to be transmitted according to the deletion program, before the transmission. When records are received, the servers insert dummy data into the received records according to the insertion program.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 8, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Shun Kudo
  • Patent number: 11023642
    Abstract: An event-driven simulation system is provided. The simulation system classifies events into bypass-events and perform-events. The simulation system performs simulation by executing instructions based on the perform-events and skips simulation for the bypass-events. The simulation system produces partial simulation result data based events that are actually simulated but not the events that are skipped. A post processor is provided to generate the missing simulation result data for the bypass-events and to merge the bypass-event with the partial simulation result to generate a complete simulation result.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: June 1, 2021
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Sherman Lee
  • Patent number: 11017083
    Abstract: Provided are systems, methods, and media for multiphase graph partitioning for malware entity detection. An example method includes receiving an input string associated with the malware entity. A determination is made as to whether the input string includes a symbolic word, a non-symbolic word, a symbolic phrase, or a non-symbolic phrase. A branching graph is formed based on a combination of the input string and a plurality of stored strings that are each associated with the malware entity to determine whether the input string is a valid detection name of the malware entity, in which the branching graph is formed by at least performing a first graph partitioning stage and a second graph partitioning stage. The input string is then labeled based on the formed branching graph and then outputted to a malware detection engine.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ci-Hao Wu, Ying-Chen Yu, June-Ray Lin, Hsieh-Lung Yang, Chen-Yu Huang, Chia-Heng Lin, Kuei-Ching Lee
  • Patent number: 11017139
    Abstract: This application discloses a computing system to select a set of one or more values for control signals internal to multiple circuit designs, generate input stimulus for the circuit designs based, at least in part, on the selected set of values for the control signals, and simulate the circuit designs with the input stimulus, which configures the simulated values of the control signals internal to the circuits designs to the selected set of values. The computing system can perform an equivalence check on the circuit designs using results of the simulation. The computing system can select another set of values for the control signals, and determine that at least the other set of values for the control signals are not realizable during simulation with any input stimulus.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: May 25, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Pritam Roy, Sagar Chaki, Pankaj Chauhan
  • Patent number: 11017143
    Abstract: The disclosure describes a method for modeling excess base current in irradiated bipolar junction transistors (BJTs). The method includes quantifying defect-related electrostatic effects of a BJT device to help improve accuracy in predicting an irradiated excess base current of the BJT device. The method can be adapted to model the excess base current of a lateral P-type-N-type-P-type (LPNP) BJT device in depleted and/or accumulated surface potential states. The predicted excess base current may be used to qualify or disqualify the BJT device or an electrical circuit including the BJT device for use in a space system(s) as a commercial-off-the-shelf (COTS) component. By modeling the excess base current based on quantifying and utilizing the defect-related electrostatic effects, it may be possible to accurately predict a total-ionizing-dose (TID) response of the BJT device, thus enabling faster and lower-cost qualification of a COTS component(s) for use in the space system(s).
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 25, 2021
    Assignees: Arizona Board of Regents on Behalf of Arizona State University, California Institute of Technology
    Inventors: Hugh James Barnaby, Philippe Adell, Blayne Tolleson
  • Patent number: 11003825
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saleha Khatun, Sheng Qian, Wangyang Zhang, Elias Lee Fallon
  • Patent number: 11003819
    Abstract: The independent claims of this patent signify a concise description of embodiments. Multiple copies of the design or multiple designs are compiled into a single emulation module or prototype FPGA/sub-system to enable multiple concurrent users. The design is executed on the emulator or prototype with the main design clock always running. A debug transactor is attached to each copy of the design which connects to one software debugger per user. The improvement is especially important for long interactive debug sessions which often occur with embedded-software debug use models. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 11, 2021
    Assignee: Synopsys, Inc.
    Inventor: Alexander Wakefield