Circuit Simulation Patents (Class 703/14)
  • Patent number: 11030162
    Abstract: A distributed processing management apparatus analyzes a source file, extracts a reference item name of a reference item that is referenced in processing, and then generates a deletion program describing a process of deleting, from each of plural records, data of a non-reference item having an item name other than the reference item name. Further, the distributed processing management apparatus generates an insertion program describing a process of inserting, in each of the records, dummy data in the position where the data of the non-reference item was located. Then, the distributed processing management apparatus causes plural servers to execute distributed parallel processing based on processing program. When transmitting records, the servers delete data from the records to be transmitted according to the deletion program, before the transmission. When records are received, the servers insert dummy data into the received records according to the insertion program.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 8, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Shun Kudo
  • Patent number: 11023642
    Abstract: An event-driven simulation system is provided. The simulation system classifies events into bypass-events and perform-events. The simulation system performs simulation by executing instructions based on the perform-events and skips simulation for the bypass-events. The simulation system produces partial simulation result data based events that are actually simulated but not the events that are skipped. A post processor is provided to generate the missing simulation result data for the bypass-events and to merge the bypass-event with the partial simulation result to generate a complete simulation result.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: June 1, 2021
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Sherman Lee
  • Patent number: 11017143
    Abstract: The disclosure describes a method for modeling excess base current in irradiated bipolar junction transistors (BJTs). The method includes quantifying defect-related electrostatic effects of a BJT device to help improve accuracy in predicting an irradiated excess base current of the BJT device. The method can be adapted to model the excess base current of a lateral P-type-N-type-P-type (LPNP) BJT device in depleted and/or accumulated surface potential states. The predicted excess base current may be used to qualify or disqualify the BJT device or an electrical circuit including the BJT device for use in a space system(s) as a commercial-off-the-shelf (COTS) component. By modeling the excess base current based on quantifying and utilizing the defect-related electrostatic effects, it may be possible to accurately predict a total-ionizing-dose (TID) response of the BJT device, thus enabling faster and lower-cost qualification of a COTS component(s) for use in the space system(s).
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 25, 2021
    Assignees: Arizona Board of Regents on Behalf of Arizona State University, California Institute of Technology
    Inventors: Hugh James Barnaby, Philippe Adell, Blayne Tolleson
  • Patent number: 11017083
    Abstract: Provided are systems, methods, and media for multiphase graph partitioning for malware entity detection. An example method includes receiving an input string associated with the malware entity. A determination is made as to whether the input string includes a symbolic word, a non-symbolic word, a symbolic phrase, or a non-symbolic phrase. A branching graph is formed based on a combination of the input string and a plurality of stored strings that are each associated with the malware entity to determine whether the input string is a valid detection name of the malware entity, in which the branching graph is formed by at least performing a first graph partitioning stage and a second graph partitioning stage. The input string is then labeled based on the formed branching graph and then outputted to a malware detection engine.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ci-Hao Wu, Ying-Chen Yu, June-Ray Lin, Hsieh-Lung Yang, Chen-Yu Huang, Chia-Heng Lin, Kuei-Ching Lee
  • Patent number: 11017139
    Abstract: This application discloses a computing system to select a set of one or more values for control signals internal to multiple circuit designs, generate input stimulus for the circuit designs based, at least in part, on the selected set of values for the control signals, and simulate the circuit designs with the input stimulus, which configures the simulated values of the control signals internal to the circuits designs to the selected set of values. The computing system can perform an equivalence check on the circuit designs using results of the simulation. The computing system can select another set of values for the control signals, and determine that at least the other set of values for the control signals are not realizable during simulation with any input stimulus.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: May 25, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Pritam Roy, Sagar Chaki, Pankaj Chauhan
  • Patent number: 11003825
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saleha Khatun, Sheng Qian, Wangyang Zhang, Elias Lee Fallon
  • Patent number: 11003819
    Abstract: The independent claims of this patent signify a concise description of embodiments. Multiple copies of the design or multiple designs are compiled into a single emulation module or prototype FPGA/sub-system to enable multiple concurrent users. The design is executed on the emulator or prototype with the main design clock always running. A debug transactor is attached to each copy of the design which connects to one software debugger per user. The improvement is especially important for long interactive debug sessions which often occur with embedded-software debug use models. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 11, 2021
    Assignee: Synopsys, Inc.
    Inventor: Alexander Wakefield
  • Patent number: 10997022
    Abstract: A method includes receiving, by a storage unit of a set of storage units of a storage network, a write request of a set of write requests that includes a first group of slice payloads for first encoded data slices of each set of a plurality of sets of encoded data slices and a corresponding revision level. The method includes processing, by the storage unit, the write request by determining whether the corresponding revision level of each of the first encoded data slices is a next revision level and generating a write response message that includes a group of status messages for the first encoded data slices based on the determining whether the corresponding revision level of each of the first encoded data slices is the next revision level. The method continues by sending the write response message to a computing device of the storage network.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 4, 2021
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Patent number: 10990734
    Abstract: Devices, methods, computer readable media, and other embodiments are described for automated formal analysis and verification of a circuit design. One embodiment involves accessing a circuit design and a set of default verification targets for the circuit design. A plurality of partitions for the circuit design are then automatically generated, and a first partition is analyzed to generate a first set of verification targets for the first partition based on the set of default verification targets and a set of partition and schedule values for the first partition. A first formal verification analysis is performed on the first partition, the first set of verification targets, and the set of partition and schedule values, and a formal verification output is generated based on the first formal verification analysis. Various embodiments can additionally involve stagnation analysis and additional automation to customize the analysis for each partition.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 27, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Georgia Penido Safe, Vincent Gregory Reynolds, Adriana Cassia Rossi de Almeida Braz, Julio Alexandre Silva Rezende
  • Patent number: 10990077
    Abstract: A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. The method further includes defining layers associated with the first and second nets, and defining a boundary of the virtual connectivity change. The method further includes performing the virtual connectivity change between the first and second nets within the boundary, and generating a second top view and a second perspective view of the layout of the integrated circuit after the virtual connectivity change.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 27, 2021
    Assignee: SYNOPSYS, INC.
    Inventor: Ankush Bharati Oberai
  • Patent number: 10984160
    Abstract: Circuit analysis and modification by receiving a first description of a circuit, the first description having a first level of detail, receiving a second description of the circuit, the second description having a second level of detail, performing a circuit simulation according to the first description, identifying an active node of the first description according to the simulation, and modifying the second description according to the active node.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Martin Bernhard Schmidt, Alexander Fritsch, Werner Juchmes, Simon Brandl
  • Patent number: 10976367
    Abstract: A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michael Richard Spica
  • Patent number: 10970442
    Abstract: Disclosed is a method of hardware and firmware debugging. The method includes coupling an interface sniffer to an interface of the hardware component on which firmware is running such that the interface sniffer captures a transaction on the interface that is associated with the hardware component, coupling, to the interface sniffer, a simulator including a reference model to receive the captured transaction by the simulator such that the captured transaction affects the reference model, and causing the internal state of the hardware component to be reproduced in the simulator based on the reference model affected by the captured transaction.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Andrey Kuyel
  • Patent number: 10963371
    Abstract: Disclosed herein are system, method, and computer program product embodiments providing a testing integration and automation system. An embodiment operates by receiving a component selection of a set of one or more components of the computing program for testing from a testing interface. A test procedure for testing a new component for the computing program with the selected one or more components of the set is identified. A selection of a runtime environment in which to test the new component and the computing program is received from the testing interface. The test procedure is executed in the selected runtime environment to generate testing results. The testing results of the executing the test procedure in the selected runtime environment are provided via the testing interface.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: March 30, 2021
    Assignee: salesforce.com, inc.
    Inventors: Mariano Edgardo De Sousa Bispo, Evangelina Martinez Ruiz Moreno, Federico Balbi, Santiago Vacas
  • Patent number: 10958537
    Abstract: One exemplary aspect describes systems and methods for determining normal SLE behavior, determining when a SLE exhibits abnormal deterioration, and determining whether to take an action to mitigate what appears to be an indication of an abnormal SLE.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Juniper Networks, Inc.
    Inventor: S. Ebrahim Safavi
  • Patent number: 10956185
    Abstract: A service manages a plurality of virtual machine instances for low latency execution of user codes. The plurality of virtual machine instances can be configured based on a predetermined set of configurations. One or more containers may be created within the virtual machine instances. In response to a request to execute user code, the service identifies a pre-configured virtual machine instance suitable for executing the user code. The service can allocate the identified virtual machine instance to the user, create a new container within an instance already allocated to the user, or re-use a container already created for execution of the user code. When the user code has not been activated for a time-out period, the service can invalidate allocation of the virtual machine instance destroy the container. The time from receiving the request to beginning code execution is less than a predetermined duration, for example, 100 ms.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 23, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Timothy Allen Wagner
  • Patent number: 10949354
    Abstract: In one embodiment, a safe data commit process manages the allocation of task control blocks (TCBs) as a function of the type of task control block (TCB) to be allocated for destaging and as a function of the identity of the RAID storage rank to which the data is being destaged. For example, the allocation of background TCBs is prioritized over the allocation of foreground TCBs for destage operations. In addition, the number of background TCBs allocated to any one RAID storage rank is limited. Once the limit of background TCBs for a particular RAID storage rank is reached, the distributed safe data commit logic switches to allocating foreground TCBs. Further, the number of foreground TCBs allocated to any one RAID storage rank is also limited. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 10949321
    Abstract: Operational management of an integrated circuit device can be performed by a microcontroller based on information associated with the notification messages generated by the integrated circuit device. The notification messages may include timestamps and metadata for different notification types which can be used to build a timeline. The microcontroller may use the information to monitor the operational health and performance of the integrated circuit device or can communicate this information to a remote management server.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 16, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A. Volpe, Alwood Patrick Williams, III, Brian Robert Silver
  • Patent number: 10951503
    Abstract: Technologies are disclosed for determining validity of data obtained from an A/B experiment, where the experiment evaluates the desirability of a potential change at a website. The experiment is run for a period of time and based upon an expected allocation of users into the A group (control group) and the B group (e.g., treatment group), along with an actual number of users directed into the two groups, it is determined if a minimal detectable error of allocation has been exceeded and, if it has, the data is deemed to be invalid. If not, the data is deemed to be valid.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 16, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Rui Chen, Siwei Jia, Tae Yeon Kim, Mengyun Lv, Serguei B. Stepaniants
  • Patent number: 10943052
    Abstract: A method includes assigning a default voltage value of a voltage domain in an integrated circuit (IC) schematic to a net in the voltage domain, generating a simulation voltage value of the net by performing a circuit simulation on the net, and modifying the IC schematic to include a voltage value associated with the net, based on the simulation voltage value of the net.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Wen Chang, Jui-Feng Kuan
  • Patent number: 10936771
    Abstract: Systems and methods for using a common fuse controller hardware design for different applications are described. A method includes specifying a first fuse map for a first system on a chip (SoC) and a second fuse map for a second SoC. The method further includes processing the first fuse map to generate a first hardware description language (HDL) file and processing the second fuse map to generate a second HDL file. The method further includes using a processor, compiling a common hardware state machine HDL file with the first HDL file to generate a first output file capturing behavior expressed in the first fuse map or compiling the common hardware state machine HDL file with the second HDL file to generate a second output file capturing behavior expressed in the second fuse map.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: March 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Avdhesh Chhodavdia
  • Patent number: 10928437
    Abstract: Data indicative of location information of a potential defect of interest revealed in a specimen and of one or more layers of the specimen corresponding to the potential defect of interest may be received. A die layout clip may be generated in accordance with the data by deriving the die layout clip based on the location information of the potential defect of interest and the one or more layers of the specimen corresponding to the potential defect of interest. The die layout clip may include information indicative of one or more patterns characterizing an inspection area that includes the potential defect of interest of the specimen. The generated die layout clip may be transmitted to a semiconductor inspection unit where an inspection by the semiconductor inspection unit of a semiconductor wafer that includes the specimen corresponding to the potential defect of interest is based on the one or more patterns of the die layout clip.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: February 23, 2021
    Assignee: Applied Materials Israel Ltd.
    Inventors: Zvi Goren, Adi Boehm, Amit Batikoff
  • Patent number: 10908204
    Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: February 2, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
  • Patent number: 10901024
    Abstract: A method for measuring a current-voltage characteristic (Id?Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id?Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 26, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
  • Patent number: 10896282
    Abstract: A process, including: obtaining data specifying a layout of a lithographic pattern; obtaining performance metrics of a computational analysis of the layout, the performance metrics indicating performance of one or more computer processes performing respective portions of the computational analysis; correlating the performance metrics to portions of the layout processed during measurement of the respective performance metrics; and generating a three or higher dimensional visualization based on a result of correlating the performance metrics to portions of the layout processed during measurement, wherein at least some of the visualization dimensions indicate relative positions of portions of the layout and at least some of the visualization dimensions indicate a performance metric correlated to the respective portions.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 19, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Taksh Pandey, Mark Christopher Simmons
  • Patent number: 10896276
    Abstract: Disclosed are a timing estimation method and a simulator. The method is applied to a function verification model. In the method, the model issues a first access issue at a first time point; receives a first response to the first access issue from the bus at a second time point; calculates a delay time between the first and second time points; determines whether the delay time is longer than or substantially equal to a transmission time corresponding to the first access issue; issues a second access issue if yes; and issues the second access issue in a compensation time counting from the second time point if not. The compensation time is not longer than the difference between the transmission time and the delay time.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 19, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Mei-Ling Chi, Yao-Hua Chen, Hsun-Lun Huang, Juin-Ming Lu
  • Patent number: 10896274
    Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, disclosed is technology for yield improvement of an integrated circuit device implementing a circuit design which includes, in a first verification, verifying adherence of the circuit design to a set of performance specifications, over a first set of test cases which include variations in a fabrication process variable or an environmental condition. The verification includes identifying, for each test case of the first set of test cases, an extent to which the circuit design satisfies one or more of the performance specifications of the set of performance specifications. A second circuit design is then developed to address corner cases identified in the first verification, and the second circuit design is then re-verified using only a subset of test cases having test cases fewer than test cases of the first set of test cases.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 19, 2021
    Assignee: Synopsys, Inc.
    Inventors: Guy Morency, Donald John Oriordan, Jonathan Lee Sanders
  • Patent number: 10891412
    Abstract: An electronic design automation (EDA) data processing system includes a version graph database and a controller. The version graph database stores a plurality of different versions of graph data sets. Each graph data set corresponds to a respective circuit component located at a given hierarchical level of a semiconductor chip design and each graph data set tagged with a version identifier (ID) indicating the version thereof. The controller determines a hierarchical circuit included in the semiconductor chip and determines a plurality of targeted circuit components that define the hierarchical circuit. The controller determines targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtains the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sheshashayee K. Raghunathan, Thomas S. Guzowski, Nathan Buck, Kerim Kalafala, Jack DiLullo, Debra Dean
  • Patent number: 10878151
    Abstract: The present disclosure discloses a glitch occurring point detection method to detect at least one glitch occurring point in an under-test circuit that includes the steps outlined below. An IC design file is retrieved to further retrieve a plurality of input nodes, at least one output node and a plurality of power nodes corresponding to the under-test circuit in the IC design file. Signals are fed to the input nodes and the power nodes such that a DC analysis is performed on a plurality of internal circuit nodes in the under-test circuit and a plurality of candidate floating points that do not have any charging or discharging path connected thereto are retrieved according to the DC analysis. Each of the candidate floating points capable of triggering the output node during the operation of the under-test circuit are determined to be the glitch occurring point.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: December 29, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Chieh Chen, Mei-Li Yu, Yu-Lan Lo
  • Patent number: 10866630
    Abstract: A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: December 15, 2020
    Assignees: Regents of the University of Minnesota, University of Illinois at Urbana-Champaign
    Inventors: Hari Cherupalli, Rakesh Kumar, John Sartori
  • Patent number: 10867582
    Abstract: A method and apparatus are provided for generating image data for output to a display device such as a HUD or HMD for display and for the validating image data being output to an applicable standard. The image generator comprises an interfacing component, an image rendering component implementing at least one image rendering function and an integrity monitor. The interfacing component receives drawing commands from external systems defining an image to be displayed and derives rendering and other control commands according to a predefined command set recognisable by the image rendering component. The image rendering component generates a set of image data from received rendering commands in the predefined set. The integrity monitor includes a rendering simulator arranged to simulate the at least one image rendering function to generate a nominally identical set of image data from received drawing or rendering commands.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: December 15, 2020
    Assignee: BAE Systems plc
    Inventors: Neil Turnbull Davidson, Ian Gray Rigge
  • Patent number: 10867097
    Abstract: We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, an average EDT (aEDT) is determined based on the EDT. Point-to-point resistance values of the terminal are generated as a function of the aEDT and a capacitance of the terminal.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 15, 2020
    Assignee: Synopsys, Inc.
    Inventor: Ralph Benhart Iverson
  • Patent number: 10860767
    Abstract: Various embodiments describe performing a transient simulation of circuits that have mutual inductors. In particular, some embodiments perform a transient simulation on a circuit model by removing and approximating the effects of one or more entries of a matrix in the circuit model, where the matrix relates to inductors or mutual inductors of the circuit. In doing so, such embodiments can render the matrix more sparse than before which, in turn, can reduce the time spent during the transient simulation to solve equations of the circuit model.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: December 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mina Adel Aziz Farhan, Joel R. Phillips
  • Patent number: 10839118
    Abstract: A circuit design is partitioned into a plurality of partitions during a first synthesis by a computer processor. After modification of the circuit design, the computer processor determines changed partitions and unchanged partitions of the circuit design. The computer processor then determines dependent partitions of the changed partitions. The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions, and the computer processor then combines the respective re-synthesized partitions and the unchanged partitions into a complete synthesized circuit design in a memory.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 17, 2020
    Assignee: Xilinx, Inc.
    Inventors: Kameshwar Chandrasekar, Aman Gayasen, Manpreet Singh, Surya Pratik Saha, Sanjay Saha
  • Patent number: 10830818
    Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
  • Patent number: 10831975
    Abstract: Multiple debug boundaries are defined in a hardware accelerator. The location of debug boundaries can be defined by a human user, or can be determined by automated tools based on characteristics of the circuitry in the hardware accelerator. Each debug boundary includes one or more hardware memory elements that are in a first state to indicate the debug boundary has not yet been reached, and that are changed to a second state by the hardware accelerator to indicate the debug boundary has been reached during execution of the hardware accelerator. Providing multiple debug boundaries in a hardware accelerator aids in debugging the accelerator design by identifying a particular section of the hardware accelerator where the failure occurred. This information regarding location of a failure may be provided to a user or to synthesis and simulation tools for the hardware accelerator design.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul E. Schardt, Jim C. Chen, Lance G. Thompson, James E. Carey
  • Patent number: 10817604
    Abstract: Disclosed herein are embodiments of systems, methods, and products that execute tools to identify non-malicious faults in source codes introduced by engineers and programmers. The tools may execute a machine learning model on the source codes to perform sentiment analysis and pattern analysis on information associated with the source codes to generate annotated source code files identifying anomalies based on the sentiment analysis and the pattern analysis. One or more threat levels are then identified and ranked based on the one or more anomalies and a ranked list of the one or more threat levels is displayed on a graphical user interface of a computer.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 27, 2020
    Assignee: Architecture Technology Corporation
    Inventors: Colleen Kimball, Robert Joyce, Judson Powers, Matthew Donovan
  • Patent number: 10811117
    Abstract: A method for SRAM yield estimation includes: generating a first perturbation vector depending on a DC voltage input condition for an assist operation section of a SRAM which is an estimation target; calculating a first margin on the basis of the first perturbation vector; performing an AC simulation during the assist operation section depending on the DC voltage input condition; generating a second perturbation vector depending on a DC voltage input condition for a normal operation section which is set when the AC simulation is ended; calculating a second margin on the basis of the second perturbation vector; and selecting a minimum margin from among the first margin and the second margin and estimating a yield of the SRAM on the basis of the selected margin.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: October 20, 2020
    Assignee: Korea University Research and Business Foundation
    Inventors: Jongsun Park, Woong Choi
  • Patent number: 10795722
    Abstract: One embodiment of the present invention sets forth a technique for encapsulating compute task state that enables out-of-order scheduling and execution of the compute tasks. The scheduling circuitry organizes the compute tasks into groups based on priority levels. The compute tasks may then be selected for execution using different scheduling schemes. Each group is maintained as a linked list of pointers to compute tasks that are encoded as task metadata (TMD) stored in memory. A TMD encapsulates the state and parameters needed to initialize, schedule, and execute a compute task.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: October 6, 2020
    Assignee: NVIDIA Corporation
    Inventors: Jerome F. Duluk, Jr., Lacky V. Shah, Sean J. Treichler
  • Patent number: 10783601
    Abstract: The present disclosure relates to signal processing such as digital watermarking and other encoded signals. One claim recites a method of offsetting color casting for a printed object associated with a retail product. The method includes: providing a first additive that absorbs light energy at or around a center wavelength of an illumination source; providing a second additive that absorbs in the ultra-violet spectrum, yet fluoresces at or around the center wavelength of the illumination source, wherein a combination of spectral responses of the first additive and the second additive offset color casting; printing the first additive, second additive and a color on the printed object, wherein the printing conveys an encoded plural bit signal. Of course, other claims and combinations are provided in the specification with reference to specific implementations and related examples.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: September 22, 2020
    Assignee: Digimarc Corporation
    Inventors: Tony F. Rodriguez, Alastair M. Reed, Kristyn R. Falkenstern
  • Patent number: 10778533
    Abstract: The disclosed computer-implemented method may include (1) defining a topology of a data center network that defines an arrangement of a plurality of networking devices included in the data center network, (2) generating a routing policy for the data center network based on the defined topology, (3) deriving a forwarding information base (FIB) for each networking device based on the defined topology and the generated routing policy for the data center network, (4) compiling a data center traffic profile for the data center network that includes a set of data flows that include an amount of data that a source networking device begins to transfer to a destination networking device via the data center network at a predetermined time, and (5) executing a simulation of the data center network via the data center traffic profile. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 15, 2020
    Assignee: Facebook, Inc.
    Inventors: Gilad Goldfarb, Naader Hasani, Hans-Juergen Schmidtke
  • Patent number: 10776089
    Abstract: Disclosed herein are system, method, and computer program product embodiments for determining an appropriate FPGA for a particular computer program. An embodiment operates by a central processing unit's counter identifying a plurality of workload properties in processing a computer program, wherein the central processing unit is part of a first computer architecture. The central processing unit then sends the workload properties to a controller trained to identify a field-programmable gate array (FPGA) module based on the plurality of workload properties. The central processing unit thereafter receives a recommended FPGA module from the controller and implements the recommended FPGA module in a computer architecture for processing the computer program, whereby the second computer architecture is able to perform the computer program more efficiently than the first computer architecture.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 15, 2020
    Assignee: Capital One Services, LLC
    Inventors: Reza Farivar, Austin Walters, Anh Truong, Jeremy Goodsitt, Vincent Pham, Galen Rafferty, Mark Watson
  • Patent number: 10771081
    Abstract: In one example, a mixed signaling socket includes a set of central processing unit (CPU) cores coupled via an inter-core link and a set of analog circuits having an analog input, each analog circuit coupled to a respective CPU core via a separate private bus. A field programmable gate array (FPGA) control circuit is coupled to the inter-core link and the set of analog circuits to provide predicable clock timing to the set of analog circuits and control signals to the set of CPU cores. An analog to digital module in at least one CPU core includes instructions to perform an analog to digital conversion to create a digital representation of the analog input using the predictable clock timing and control signals from the FPGA.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 8, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Rachid Kadri
  • Patent number: 10771546
    Abstract: Logically separating users into isolation groups is described. An example computer-implemented method can include identifying a first group of users of an online system that allows users to interact with one another on the online system. The method may also include grouping the first group of users into a first isolation group. The method may also include identifying a second group of users of the online system separate from the first group of users within the online system. The method may also include grouping the second group of users into a second isolation group. The first isolation group and the second isolation group may include logical boundaries that restrict interaction within the online system between users in the first isolation group and users in the second isolation group. Additionally, the first isolation group and the second isolation group may be hosted on the same server.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: September 8, 2020
    Assignee: MZ IP Holdings, LLC
    Inventors: Jai Kim, Garth Gillespie, Ryan Jacobson, Ajk Palikuqi
  • Patent number: 10755014
    Abstract: An event-driven simulation system is provided. The simulation system classifies events into bypass-events and perform-events. The simulation system performs simulation by executing instructions based on the perform-events and skips simulation for the bypass-events. The simulation system produces partial simulation result data based events that are actually simulated but not the events that are skipped. A post processor is provided to generate the missing simulation result data for the bypass-events and to merge the bypass-event with the partial simulation result to generate a complete simulation result.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 25, 2020
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Sherman Lee
  • Patent number: 10756976
    Abstract: Network replica systems and methods include, via a server, a group of servers, or in a cloud computing environment, communicating with one or more management systems and one or more networks associated with the one or more management systems via one or more Application Programming Interfaces (APIs); obtaining data from the one or more management systems and/or the one or more networks; storing the data in a database of record which defines a detailed model of a current state of the networks; and applying one or more assertions to data of interest in the database of record to emulate behavior in the one or more networks, wherein the assertions map actual device, process, business, architecture, and technology behaviors onto the data of interest from the database of record to emulate the behavior, wherein the database of record and the applied one or more assertions include a network replica of the networks.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 25, 2020
    Assignee: Ciena Corporation
    Inventors: Robert Kevin Tomkins, Romualdas Armolavicius
  • Patent number: 10747920
    Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: August 18, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takumi Uezono, Tadanobu Toba, Masahiro Shiraishi, Hideo Harada, Satoshi Nishikawa
  • Patent number: 10740210
    Abstract: Tracing operation of a kernel can include comparing, using a processor, signals of a compiled kernel with a database including compiler generated signals for compute units to determine a list of the signals of the compiled kernel that match the compiler generated signals and generating trace data by emulating the compiled kernel using the processor. The trace data includes values for signals of the compiled kernel collected over time during the emulation. Operational data corresponding to individual compute units of the compiled kernel can be determined from values of the signals of the list within the trace data using the processor. The operational data can be displayed using the processor.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 11, 2020
    Assignee: Xilinx, Inc.
    Inventors: Paul R. Schumacher, Kumar Deepak, Roger Ng, David K. Liddell
  • Patent number: 10726179
    Abstract: According to one embodiment, a circuit design supporting method comprising: generating first determination information based on first information obtained by a cycle based logic simulation; extracting glitch generation sources; generating second determination information based on second information obtained based on the first information by considering glitch; comparing the first and the second determination information to each other and determining whether or not a comparison result satisfies a condition; and performing the generating the second determination information and the determining for each of the glitch generation sources and presenting, to a user, one or a plurality of glitch generation sources in which the comparison result satisfies the condition.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: July 28, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Masafumi Dose
  • Patent number: 10712388
    Abstract: The Translation Layer is embedded into each circuit under test (CUT) to modularize test process. The modularized tests are self-contained and performed in isolation. They are composed without consideration of environment constraints. The CUT and its environment constraints can be concurrently be tested in isolation and independently. Interconnections between the CUT and the environment can be tested in the environment constraint test without additional dedicated test logic. The modularized test process allows the test patterns of the environment constraints to be derived from those of the CUT. The resulting test patterns are used to compose the test patterns of a target system. Since the test process is recursive in nature, the modularized test of each constituent subsystem or design core can be performed in isolation in the target system, while the environment constraints and the interconnections are being tested concurrently.
    Type: Grant
    Filed: May 5, 2019
    Date of Patent: July 14, 2020
    Inventor: Chinsong Sul