Circuit Simulation Patents (Class 703/14)
  • Patent number: 11665203
    Abstract: The innovation disclosed and claimed herein, in one aspect thereof, comprises systems and methods of automatic classification and modeling. The innovation can include determining a failure history of networked architecture, the failure history including data immediately prior to failure. The innovation can include machine learning the failure history to determine failure indicators. The innovation can include generating a black hole model based on the failure history and the machine learning. The innovation can include monitoring a networked architecture. The networked architecture has a set of elements comprising software elements and hardware elements interconnected in a common environment. Each element of the set of elements is monitored. The innovation can include determining an element is trending towards a failure. The trend is determined by a black hole model. The innovation can include enabling security features to prevent the element from failure.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 30, 2023
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Noah L. Hughes, John E. Eisenhauer
  • Patent number: 11658884
    Abstract: One exemplary aspect describes systems and methods for determining normal SLE behavior, determining when a SLE exhibits abnormal deterioration, and determining whether to take an action to mitigate what appears to be an indication of an abnormal SLE.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: May 23, 2023
    Assignee: Juniper Networks, Inc.
    Inventor: Ebrahim Safavi
  • Patent number: 11639951
    Abstract: The invention concerns a method for measuring a power (Pe, Pm) of an electric motor, that involves measuring a real current (I) of the motor, by means of a measurement sensor (11), the invention being characterised in that it involves inputting, on an interface (20), at least one piece of nominal power data (Pn), one piece of nominal speed data (Wn), one piece of nominal current data (In), one piece of nominal voltage data (Un), one piece of power factor data (cos ?) and the real current (I) of the engine, calculating, in the computer, a no-load current of the motor according to a first stored function depending on at least the data (Pn, In, Un, cos ?), calculating, in the computer, the active power (Pe) and/or the mechanical power (Pm) and/or the active energy and/or the mechanical energy according to at least one second stored function depending on at least the data (Pn, In), the real current (I) and the no-load current that has been calculated, and providing the power that has been calculated on an output
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 2, 2023
    Inventors: Jérémy Langlet, Abdessalim Arras
  • Patent number: 11609256
    Abstract: Disclosed are exemplary embodiments of electrostatic discharge (ESD) pulse generators that may provide improved system level ESD robustness characterization and qualification analysis.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: March 21, 2023
    Assignee: Pragma Design, Inc.
    Inventor: Jeffrey C. Dunnihoo
  • Patent number: 11604915
    Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: March 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hung-Chih Ou, Kuo-Fu Lee, Wen-Hao Chen, Keh-Jeng Chang, Hsiang-Ho Chang
  • Patent number: 11599489
    Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
    Type: Grant
    Filed: May 8, 2021
    Date of Patent: March 7, 2023
    Assignee: AyDeeKay LLC
    Inventor: Scott David Kee
  • Patent number: 11593543
    Abstract: A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: February 28, 2023
    Assignee: SYNOPSYS, INC.
    Inventors: Joydeep Banerjee, Debabrata Das Roy
  • Patent number: 11546224
    Abstract: Parameters associated with a distributed network are received. A topology of a virtual network that corresponds to the distributed network is generated in view of the received parameters. The topology of the virtual network is configured to simulate the distributed network and a simulation of the distributed network is executed using the configured virtual network.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: January 3, 2023
    Assignee: Red Hat, Inc.
    Inventors: Martin Vecera, Miroslav Jaros, Stefan Bunciak
  • Patent number: 11537771
    Abstract: A system and method are provided to enable non-quantum experts to schematically represent, simulate and quantify the performance of physically realistic photonic quantum circuits. The framework offers the flexibility for users—not necessarily familiar with the fundamentals of quantum mechanics—to create circuits and work with simple inputs and outputs, while the complexities of manipulating high dimensionality quantum Hilbert spaces supporting photonic and physical quantum object states are handled with the use of purpose-built tools. The tools include a user-friendly method for defining classical photonic circuits which may be coupled to physical objects such as qubits, quantum input states, as well as classical and quantum measurement devices. The tools feature classical-to-quantum S-matrix conversion, quantum S-matrix extraction, as well as capabilities for defining and extracting quantum error parameters.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 27, 2022
    Assignee: ANSYS Inc.
    Inventors: James Frederick Pond, Jeffrey Francis Young, Ellen Natalie Schelew, Xiruo Yan
  • Patent number: 11531563
    Abstract: A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Monica Gupta, Eliezer Weissmann, Hisham Abu Salah, Rajshree Arun Chabukswar, Russell Jerome Fenger, Eugene Gorbatov, Guruprasad Settuvalli, Balaji Masanamuthu Chinnathurai, Sumant Tapas, Meghana Gudaram, Raj Kumar Subramaniam
  • Patent number: 11487923
    Abstract: A Method for simulating, on a computer processing unit including a semiconductor integrated circuit, the operation of a quantum circuit model, which includes the operations of: dividing the quantum circuit into d adjacent layers Lk intended to be successively traversed by the n qubits taken together, each layer including a single quantum gate Gk; and assigning a type to each quantum gate Gk of the circuit, among three predefined types of quantum gates. The three types are: Diagonal type gate, for which the transfer matrix is diagonal; Conventional type gate, for which the transfer matrix is non-diagonal and includes operators having a value of 0 or 1, with only one operator per row and per column; and Dense type gate, which is neither conventional nor diagonal in type.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 1, 2022
    Assignee: BULL SAS
    Inventors: Cyril Allouche, Minh Thien Nguyen
  • Patent number: 11476667
    Abstract: A hybrid electromagnetic transient simulation method for microgrid real-time simulation, wherein a traditional node analysis method (NAM) and a highly parallel latency insertion method (LIM) are combined, so that the microgrid is firstly divided from a filter of a distributed power generation system to form one latency insertion method (LIM) network containing a power distribution line and a plurality of node analysis method (NAM) networks containing the distributed power generation system respectively, the NAM network being simulated by traditional node analysis method, the LIM network being simulated by the latency insertion method, in an initialization stage, one correlation matrix and four diagonal matrixes containing line parameters used for LIM network simulation being formed according to line topology and parameters of the microgrid, in a main cycle of the simulation, the LIM network solved simultaneously with multiple NAM networks, a parallelism of a microgrid simulation being improved.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: October 18, 2022
    Assignee: Shanghai Jiao Tong University
    Inventors: Keyou Wang, Jin Xu, Guojie Li, Zirun Li, Pan Wu
  • Patent number: 11468537
    Abstract: An open market system includes: an information collection circuit that collects prediction information indicating details of a game predicted by prediction sellers; an entry acceptance circuit that accepts entry of tokens possessed by prediction purchasers; an information presentation circuit that presents, to the prediction purchasers who have entered the tokens, the prediction information collected by the information collection circuit and optimum prediction information based on the prediction information; and a distribution execution circuit that distributes, to one or more of the prediction sellers, the tokens entered by one or more of the prediction purchasers for the optimum prediction information.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: October 11, 2022
    Assignee: JUNGLE X CORP.
    Inventor: Fumitada Naoe
  • Patent number: 11455447
    Abstract: Aspects of the disclosed technology relate to techniques of activity coverage assessment. Transistor-level circuit simulation is performed for a circuit design under a set of test stimuli, which determines values of one or more electrical properties for each of circuit elements of interest in the circuit design. The one or more electrical properties are selected based on information of the each of circuit elements of interest, which comprises what circuit element type the each of circuit elements of interest belongs to. Based on the values of the one or more electrical properties, activity coverage information comprising information about which circuit elements in the circuit elements of interest are active or inactive under the set of test stimuli is determined.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 27, 2022
    Assignee: Siemens Industry Software Inc.
    Inventor: Stephen Kenneth Sunter
  • Patent number: 11455203
    Abstract: A system analysis support device includes a data acquisition part that obtains time series data (items) measured in a system that is to be analyzed, an overall abnormality degree calculation part that calculates transition of abnormality degree representing overall abnormality degree of the system that is to be analyzed, using a predictive model generated so that, with 2 or more time series data (items) as input, values representing a relationship between the 2 or more time series data (items) are outputted, and the time series data (items), and a representative index selection part that selects and presents time series data (items) indicating change similar to transition of the overall abnormality degree of the system that is to be analyzed, from among the time series data (items).
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: September 27, 2022
    Inventor: Katsuhiro Ochiai
  • Patent number: 11449653
    Abstract: A converter parameterized constant admittance modeling method based on a cross initialization including the following steps: (1) performing parameterized modeling on a converter, wherein switches are modeled using a parametric historical current source constant admittance model and other components are modeled using a traditional electromagnetic transient simulation integral model in the converter; (2) detecting whether state switching occurs, performing cross initialization correction when occurring; (3) determining model parameters, and establishing an equivalent admittance matrix and an injection current source of a whole grid, to obtain an electromagnetic transient simulation equivalent model; (4) solving a network tide according to a basic solving equation I=YU to obtain an electromagnetic transient model simulation result of the converter at current time; and (5) calculating an equivalent admittance matrix and an injection current source at next time through a current network state quantity, and returni
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: September 20, 2022
    Inventors: Wei Gu, Yang Cao, Dehu Zou, Ke Li, Kun Shi
  • Patent number: 11430311
    Abstract: An imaging device capable of detecting differences with low power consumption is provided. The imaging device includes a pixel including a photoelectric conversion element and a transistor; an analog processing circuit; and a digital processing circuit. The imaging device is operated in a first mode and a second mode. In the first mode, the analog processing circuit detects a difference between first imaging data taken by the pixel and second imaging data taken by the pixel and generates a trigger signal on the basis of the value of the difference. In the second mode, the digital processing circuit converts third imaging data taken by the pixel into digital data. Switching from the first mode to the second mode is performed on the basis of the trigger signal.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 30, 2022
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 11416431
    Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Krishna Teja Malladi, Andrew Chang, Ehsan M. Najafabadi
  • Patent number: 11405195
    Abstract: A method related to authenticating a device may include accessing a plurality of hash values, wherein the plurality of hash values corresponds to a plurality of passwords of a plurality of devices. The method may also include generating a hash value corresponding to the device and authenticating the device by providing the plurality of hash values and the hash value to an authentication system.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: August 2, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Christoph J. Graham
  • Patent number: 11392355
    Abstract: Disclosed herein are system, method, and computer program product embodiments for determining an appropriate FPGA for a particular computer program. An embodiment operates by a central processing unit's counter identifying a plurality of workload properties in processing a computer program, wherein the central processing unit is part of a first computer architecture. The central processing unit then sends the workload properties to a controller trained to identify a field-programmable gate array (FPGA) module based on the plurality of workload properties. The central processing unit thereafter receives a recommended FPGA module from the controller and implements the recommended FPGA module in a computer architecture for processing the computer program, whereby the second computer architecture is able to perform the computer program more efficiently than the first computer architecture.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: July 19, 2022
    Assignee: Capital One Services, LLC
    Inventors: Reza Farivar, Austin Walters, Anh Truong, Jeremy Goodsitt, Vincent Pham, Galen Rafferty, Mark Watson
  • Patent number: 11386154
    Abstract: Systems and methods are described to create a comprehensive model from multiple input data sources in distributed manner for performing diagnostics and/or prognostics of a complex system/platform having its modules/parts implemented independent of each other. In an embodiment, the proposed system for creating a comprehensive connected model of a complex platform includes a input data receive module configured to receive data/content/information from one or more input data sources associated with different modules of the complex platform in a distributed manner, a dependency determination module configured to analyze a plurality of entities/variables retrieved from the data and determine dependency relationships between the plurality of entities by creating a edge list, and a connected model creation module configured to create a comprehensive connected model (connected graph) from the edge list.
    Type: Grant
    Filed: January 28, 2017
    Date of Patent: July 12, 2022
    Inventors: Ravindra Patankar, Mangesh Balkrishna Khare, Venkatesh Kareti, Priti Ranadive
  • Patent number: 11368400
    Abstract: Application data may be transmitted while oscillating a transmission parameter. A metric associated with a complementary network property is analyzed to identify a transition point between a stochastic error state and a deterministic error state of the complementary network property. Additional network properties or states may be inferred from the transition point, and the transmission of the application data may be optimized based on the inferred additional properties or states.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 21, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Stephen Daniel Vilke, James Morgan Selvidge, Rudy Willis, Paul Hinks
  • Patent number: 11360743
    Abstract: An example of the instant solution comprises at least one of receiving an encrypted data and an encryption key, generating a randomized matrix, dispersing the encrypted data based on the randomized matrix resulting in a fragmented encrypted data and dispersing the encryption key based on the randomized matrix and the fragmented encrypted data.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 14, 2022
    Assignee: Cyber Reliant Corp.
    Inventors: Katelynn Marie Linthicum, John Michael Suit, Ian Spencer Bartelt Becker
  • Patent number: 11354476
    Abstract: There is a significant precaution when performing random dopant fluctuation by using the drift-diffusion model that is the basis of the conventional device simulation. Because the continuation by a long wavelength approximation was done to derive said drift-diffusion model. That is how to recover the location dependence of discrete impurity ions in the long wavelength approximation. For example, in the case that there is an impurity ion near to the interface to an insulating film, the charge density of an impurity ion, which was made continuous in the conventional method, is unable to catch the charge density change due to polarization at the interface. Because this polarization is dependent of the location of a discrete impurity ion near to the interface.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: June 7, 2022
    Inventor: Hiroshi Watanabe
  • Patent number: 11315237
    Abstract: An image is obtained by using a charged particle beam, and a design layout information is generated to select patterns of interest. Grey levels among patterns can be compared with each other to identify abnormal, or grey levels within one pattern can be compared to a determined threshold grey level to identify abnormal.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: April 26, 2022
    Assignee: ASML Netherlands B.V.
    Inventor: Wei Fang
  • Patent number: 11308250
    Abstract: In an embodiment, a data processing method comprises storing one or more generic machine operating definitions, wherein each of the generic machine operating definitions describes expected operational behavior of one or more types of machines during one or more operating states; analyzing operating data that describes past operation of a plurality of machines of a plurality of types; based at least in part on the operating data and the one or more generic machine operating definitions, generating and storing one or more machine operating models that describe expected operational behavior corresponding to a plurality of operating states of the plurality of machines; wherein the one or more machine operating models comprise a plurality of data patterns, wherein each of the data patterns is associated with a different set of one or more operating states of one or more machines; wherein the method is performed by one or more computing devices.
    Type: Grant
    Filed: September 8, 2019
    Date of Patent: April 19, 2022
    Assignee: Falkonry Inc.
    Inventors: Nikunj R. Mehta, Prasanta Bose
  • Patent number: 11295831
    Abstract: A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 5, 2022
    Inventors: Ankita Patidar, Sandeep Kumar Goel
  • Patent number: 11288339
    Abstract: Systems and methods are provided for generating a state space model of a physical system. Embodiments of a computer-implemented system may include a physical system data structure that includes frequency-domain response data that is indicative of a response of one or more components of a physical system to a stimulus, and a state space model generation engine that is configured generate a state space model based on the frequency-domain response data, where the state space model is usable to simulate a time-domain response of the one or more components of the physical system.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 29, 2022
    Assignee: Ansys, Inc.
    Inventor: Amit Hochman
  • Patent number: 11281829
    Abstract: A device, system, and method performs an adaptive simulation. The method performed by a similar includes receiving a release to be incorporated into a user device, the user device being a deployed device. The method includes receiving a profile of the user device, the profile being indicative of settings and usage information of the user device. The method includes generating a simulated user device corresponding to the user device, the simulated user device having a simulated profile corresponding to the profile. The method includes performing, by the simulator, a simulation for the release based upon the simulated user device and the simulated profile.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 22, 2022
    Assignee: Wind River Systems, Inc.
    Inventors: Assaf Namer, Anton Langebner
  • Patent number: 11255894
    Abstract: Detecting a counterfeit status of a target utility device by: selecting a set of frequencies that best reflect load dynamics or other information content of a reference utility device while undergoing a power test sequence; obtaining target electromagnetic interference (EMI) signals emitted by the target utility device while undergoing the same power test sequence; creating a sequence of target kiviat plots from the amplitude of the target EMI signals at each of the set of frequencies at observations over the power test sequence to form a target kiviat tube EMI fingerprint; comparing the target kiviat tube EMI fingerprint to a reference kiviat tube EMI fingerprint for the reference utility device undergoing the power test sequence to determine whether the target utility device and the reference utility device are of the same type; and generating a signal to indicate a counterfeit status based at least in part on the results of the comparison.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: February 22, 2022
    Inventors: Edward R. Wetherbee, Rui Zhong, Kenny C. Gross, Guang C. Wang
  • Patent number: 11249888
    Abstract: One embodiment provides a system and method for identifying invariants in a software system. During operation, the system executes a test suite comprising a plurality of tests associated with the software system to output a list of likely invariants in the software system, and performs a test-generation operation attempting to generate counterexample tests for the likely invariants. In response to a counterexample test being successfully generated for a first likely invariant, the system removes the first likely invariant from the list of likely invariants and adds the successfully generated counterexample test to the test suite.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 15, 2022
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Alexandre Campos Perez, Eric A. Bier, Johan de Kleer, Ron Z. Stern
  • Patent number: 11250560
    Abstract: Disclosed herein is method for multi-perspective-based wafer analysis. The method includes (i) scanning a plurality of pages, or portions thereof, one after the other, wherein each page, or a portion thereof, is successively scanned, in each of a multiplicity of perspectives, and (ii) analyzing scan data of a last scanned page while scanning a next page from the plurality of pages. At least some of the pages include multiple slices of the wafer. The analysis of the scan data includes identifying defects in the scanned pages, based on an integrated analysis combining scan data from each of the multiplicity of perspectives. Further disclosed is a computerized system configured to implement the method.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: February 15, 2022
    Assignee: Applied Materials Israel Ltd.
    Inventors: Doron Korngut, Ido Almog
  • Patent number: 11244096
    Abstract: Embodiments include simulating a design under test on an electronic device. Aspects include running a test program on the design under test and capturing inputs into the design under test. Aspects also include storing the inputs into the design under test in a storage device. Responsive to determining that an event has occurred during execution of the test program, aspects include halting the test program on the design under test. Aspects further include enabling a user via a user interface to determine a cause of the event by performing a simulation of the design under test using the inputs stored in the storage device.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: February 8, 2022
    Inventors: Michael James Becht, Christopher J. Colonna, Stephen Robert Guendert, Pasquale A. Catalano
  • Patent number: 11243503
    Abstract: A building management system includes building equipment operable to affect a variable state or condition of a building and a control system configured to receive a user input indicating a model form. The model form includes a plurality of matrices having a plurality of elements defined in terms of a plurality of parameters. The control system is configured to parse the model form to generate a sequence of machine-executable steps for determining a value of each of the plurality of elements based on a set of potential parameter values, identify a system model by executing the sequence of machine-executable steps to generate a set of parameter values for the plurality of parameters, generate a graphical user interface that illustrates a fit between predictions of the identified system model and behavior of the variable state or condition of the building, and control the building equipment using the identified system model.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: February 8, 2022
    Assignee: Johnson Controls Tyco IP Holdings LLP
    Inventors: Andrew J. Przybylski, Michael J. Wenzel, Matthew J. Ellis
  • Patent number: 11240169
    Abstract: Various example embodiments relate generally to supporting queuing of packets in a communication network. Various example embodiments for supporting queuing of packets in a communication network may be configured to support queueing of packets based on a packet queuing memory space including a hash entry space configured to maintain a set of H hash entries and a packet queue space configured to maintain a set of Q packet queues, wherein H is greater than Q. Various example embodiments for supporting queuing of packets in a communication network may be configured to support queueing of packets in a manner for handling packet events (e.g., packet arrival events, packet departure events, or the like) while preventing or mitigating queue collisions of hash entries (where a queue collision occurs when multiple hash entries, and the respective network flows of those hash entries, are associated with a single packet queue).
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 1, 2022
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Francini, Sameerkumar Sharma
  • Patent number: 11222159
    Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: January 11, 2022
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Heiko Kalte, Dominik Lubeley
  • Patent number: 11200361
    Abstract: A method, system and computer program product for appending abstractions to a testbench used for verifying the design of an electronic circuit. According to an embodiment of the invention, a method comprises identifying a set L of one or more support properties l for a set P of one or more properties p for a given electronic circuit; computing a plurality of hardware signals s of the given electronic circuit; and creating a plurality of abstract signals ABS, including declaring a fresh abstract signal abs_s for each of the hardware signals s, and creating a fresh abstract signal abs_l for each of the support properties l of the set L; for each of the properties p of the set P, creating an abstract property version abs_p; and appending the abstract signals ABS and the abstract property abs_p to the testbench to form an appended testbench.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bradley Donald Bingham, Viresh Paruthi, Steven Mark German
  • Patent number: 11200362
    Abstract: Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 14, 2021
    Assignee: Synopsys, Inc.
    Inventors: Hua Song, Cheng En Wu, James P. Shiely
  • Patent number: 11200146
    Abstract: Software verification is a vital process to ensure reliability and robustness of software systems. The software verification is associated with verifying one or more properties associated with a piece of code. Conventional methods are unable to verify properties of piece of code with loops, especially in the presence of loops with a large, unknown or infinite bound, or a large number of complex conditions. The system receives an abstracted piece of code corresponding to an original piece of code to check whether the abstracted piece of code hence the original piece of code is safe or not. The system applies model checking over the abstracted piece of code to check one or more property assertions associated with an abstracted piece of code. If the property assertion fails in model checking, a trace leading to the violation of the one or more property assertions is identified and analyzed.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: December 14, 2021
    Assignee: Tata Consultancy Services Limited
    Inventors: Priyanka Darke, Tanha Shah, Venkatesh Ramanathan
  • Patent number: 11188687
    Abstract: A method and apparatus for checking compliance of a design for a product with design rules. An executable rule module comprising the design rules is received. The design rules comprise design checking rules that specify conditions. Design data representing the design is received. The executable rule module is run using the design data to determine compliance of the design with the design rules by determining whether the design satisfies the conditions. A compliance report to indicate the compliance of the design with the design rules is generated. The design data may be used to manufacture the product in response to a determination that the design complies with the design rules.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 30, 2021
    Assignee: The Boeing Company
    Inventors: Christopher Esposito, Jeff Alan Heisserman
  • Patent number: 11188705
    Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: November 30, 2021
    Assignee: Synopsys, Inc.
    Inventors: Tao-Chun Yu, Hsien-Shih Chiu, Shao-Yun Fang, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
  • Patent number: 11176298
    Abstract: The present disclosure provides a method for modeling, including: S1): designing a test key having a source, a drain, and a gate, and testing the test key to obtain test data; S2): extracting a model parameter according to the test data; S3): verifying reasonableness of a physical characteristic of the model parameter based on a relationship between a source-drain voltage and a drain current, if the reasonableness passes the verification, a model file is established and the method proceeds to S4), if the reasonableness fails the verification, the method returns to S2) to adjust the model parameter, until the reasonableness passes the verification; S4): performing quality assurance on the model file, if the model file passes the quality assurance, the modeling is completed, if the model file fails the quality assurance, the method returns to S2) to adjust the model parameter until the model file passes the quality assurance.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: November 16, 2021
    Assignee: CHINA FLASH CO., LTD.
    Inventors: Hong Nie, Ke Wu, Xiang Su
  • Patent number: 11163661
    Abstract: Test case generation for a hardware state space including: identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generating a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: November 2, 2021
    Inventors: Madhusudan Kadiyala, Narasimha R. Adiga, Manoj Dusanapudi
  • Patent number: 11163664
    Abstract: A system and method to verify software includes a debugger setting a breakpoint in the software. The breakpoint indicates a point at which to pause or stop execution of the software. The method also includes setting one or more anchor points associated with the breakpoint. Each of the one or more anchor points represents another point in the software that must be executed prior to pausing or stopping the execution of the software at the breakpoint.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 2, 2021
    Inventors: Xiao Ling Chen, Chuan He, Yan Huang, Jiang Yi Liu, Wei Wu, Jian Xu
  • Patent number: 11157673
    Abstract: A field programmable gate array (FPGA) having at least first and second processing circuits implemented thereon. Each of the first and second processing circuits comprises a numerical core and associated peripheral components. The numerical core in the first processing circuit is dissimilar to the numerical core in the second processing circuit. The first and second processing circuits are segregated from each other in floorplan view.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 26, 2021
    Inventor: Arnaud Bouchet
  • Patent number: 11151294
    Abstract: One or more embodiments disclosed herein pertain to a hybrid emulation system for hybrid emulation of a design under test (DUT). The system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hardware emulation system includes emulated registers for the first portion of the DUT. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. The hybrid emulation system additionally comprises a configuration file that identifies a subset of the emulated registers. The simulation system is configured with the configuration file to selectively mirror, during the hybrid emulation, the subset of the emulated registers identified by the configuration file.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 19, 2021
    Assignee: Synopsys, Inc.
    Inventors: Andreas Gerd Ropers, Sylvain Bayon de Noyer, Alexandru Fiodorov, Filip Constant Thoen, Markus Wedler
  • Patent number: 11144695
    Abstract: A wafer characteristic prediction method and an electronic device are provided. The method includes: receiving a process parameter of a wafer during a mass production; inputting the process parameter to a prediction model to obtain a wafer characteristic of the wafer being mass produced; and outputting the wafer characteristic.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 12, 2021
    Assignee: DigWise Technology Corporation, LTD
    Inventors: JingJie Wu, Yuan-Hung Liao, Chih-Chen Liu
  • Patent number: 11144329
    Abstract: A processing unit employs microcode wherein the jump table associated with the microcode is embedded in the microcode itself. When the microcode is compiled based on a set of programmer instructions, the compiler prepares the jump table for the microcode and stores the jump table in the same file or other storage unit as the microcode. When the processing unit is initialized to execute a program, such as an operating system, the processing unit retrieves the microcode corresponding to the program from memory, stores the microcode in a cache or other memory module for execution, and automatically loads the embedded jump table from the microcode to a specified set of jump table registers, thereby preparing the processing unit to process received packets.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 12, 2021
    Inventors: Alexander Fuad Ashkar, Rakan Khraisha, Rex Eldon McCrary, Harry J. Wise
  • Patent number: 11144027
    Abstract: Soft error data describing soft errors predicted to affect at least a particular hardware component of a computing system are used to determine functional safety metric values. The computing system is to control at least a portion of physical functions of a machine using the particular hardware component. Respective soft error rates are determined for each of a set of classifications based on the soft errors described in the soft error data. Derating of the soft error rates are performed based on a set of one or more vulnerability factors to generate derated error rate values for each of the set of classifications. The functional safety metric value is determined from the derated error rate values to perform a functional safety analysis of the computing system.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Giuseppe Capodanno, Jyotika A. Athavale, Riccardo Mariani
  • Patent number: 11138358
    Abstract: A method includes receiving a circuit design including a plurality of components associated with a plurality of component parameters. The method further includes adjusting a value of a particular component parameter of the plurality of component parameters based on a tolerance to generate a modified plurality of component parameters. The method further includes determining, based on inputting the modified plurality of component parameters into a circuit calculator, that an operating value of the circuit design is sensitive to the particular component parameter. The method further includes selecting a simulation of the circuit design to perform based on the particular component parameter. The method further includes performing the simulation to determine whether the circuit design supports one or more design limits.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 5, 2021
    Inventors: Pradeep Kumar Chawda, Shrikrishna Srinivasan, Mac Dien, Ning Dong, Makram Monzer Mansour, Jeffrey Robert Perry