Abstract: Disclosure is made of methods, apparatus and system for clustering processes for use by a cloud platform. Process clustering may include receiving traffic data transmitted and received between each pair of processes in a set of processes. A matrix may be generated based on the traffic data, the matrix including a row and a column for each process in the set of processes. The matrix may be hierarchically clustered based on the traffic data, the hierarchical clustering outputting a plurality of clusters, each cluster including one or more processes in the set of processes. The plurality of clusters may then be merged into a set of merged clusters of processes.

Abstract: Techniques are disclosed for generating photorealistic images of objects, such as heads, from multiple viewpoints. In some embodiments, a morphable radiance field (MoRF) model that generates images of heads includes an identity model that maps an identifier (ID) code associated with a head into two codes: a deformation ID code encoding a geometric deformation from a canonical head geometry, and a canonical ID code encoding a canonical appearance within a shape-normalized space. The MoRF model also includes a deformation field model that maps a world space position to a shape-normalized space position based on the deformation ID code. Further, the MoRF model includes a canonical neural radiance field (NeRF) model that includes a density multi-layer perceptron (MLP) branch, a diffuse MLP branch, and a specular MLP branch that output densities, diffuse colors, and specular colors, respectively. The MoRF model can be used to render images of heads from various viewpoints.

Abstract: A system and method are provided for simulating circuits that transmit bidirectional signals between some ports using simulators designed originally for electrical circuits and systems, that eliminate the need for different port interfaces. The system and method can be applied to simulate photonic circuits either standalone or integrated with electrical circuits and systems. In one method implemented by the system potential and flow representations, available for example in Verilog-A simulators, are used to create bidirectional signals on a single bus line to transmit optical signals. In another method implemented by the system, the system auto-configures each optical port type as left or right at runtime or during a pre-simulation initialization to allow for bidirectional signals with a single port interface.

Abstract: A logic simulation device according to an aspect of the present disclosure includes an operation model of a resistance-change memory element. The resistance-change memory element is provided between two terminals. The operation model includes a register section for holding data, a truth table, and a determining section. The truth table defines a relationship between signal values of the two terminals, and data writing to the register section and data reading from the register section. The determining section performs determination about the data writing and the data reading on the basis of signal values inputted to the two terminals and the truth table.

Abstract: A development support device, a terminal device, a development support method, and a computer program are provided. A receiving unit that receives a simulation condition of a power storage device from a terminal device after user authentication of the terminal device, a simulation execution unit that simulates behavior of the power storage device based on the received simulation condition, and a transmission unit that transmits a simulation result by the simulation execution unit to the terminal device are included.

Abstract: A method, system and product comprising: obtaining a functional-level representation of a quantum circuit that comprises a functional block; obtaining an indication of one or more resources that are available to the functional block, the indication regarding a range of cycles and an indication regarding a number of qubits; dynamically generating a gate-level implementation of the functional block that adheres to the indication of the one or more resources; and synthesizing a gate-level implementation of the quantum circuit, wherein the gate-level implementation of the quantum circuit comprises the gate-level implementation of the functional block.

Abstract: This technology described herein provides embodiments of a cloud-based mobility service system for a Connected Automated Vehicle Highway (CAVH). In some embodiments, the technology provides a cloud-based mobility service system to provide the services and functionalities of different components of a CAVH system including, for example, user, vehicle, infrastructure, system, roadside, and CAVH traffic control layers. Detailed cloud-based data interfaces and services are described for each component, e.g., regarding their data needs to and from the cloud system. Cloud functionalities including the communication, computational, and analytic needs are described for each system component. The CAVH cloud services also provide integrated CAVH functionalities including planning, control, sensing, prediction, and analytics at macroscopic, mesoscopic, and microscopic levels of CAVH systems.

Abstract: Systems, apparatuses, and methods directed to generating waveforms that can be used to produce realistic sounding speech when used in a speech synthesis or text-to-speech application. In some embodiments, this includes training a neural network model that is part of a generative adversarial network (GAN) to generate the waveform from an input spectrogram, while implementing a specific set of processing stages to determine loss. The loss is used with a back-propagation process to update the weights of the model during a training cycle. In one example use case, text is converted to a spectrogram and the spectrogram is converted to a waveform by a trained model. The output of the model may be used to drive a transducer that converts the waveform to audible sound.

Abstract: Systems and methods for in-die metrology using target design patterns are provided. These systems and methods include selecting a target design pattern based on design data representing the design of an integrated circuit, providing design data indicative of the target design pattern to enable design data derived from the target design pattern to be added to second design data, wherein the second design data is based on the first design data. Systems and methods can further include causing structures derived from the second design data to be printed on a wafer, inspecting the structures on the wafer using a charged-particle beam tool, and identifying metrology data or process defects based on the inspection. In some embodiments the systems and methods further include causing the charged-particle beam tool, the second design data, a scanner, or photolithography equipment to be adjusted based on the identified metrology data or process defects.

Abstract: In an example method, a system obtains first data indicating a plurality of properties of a plurality of gas flow lines. The properties include, for each of the gas flow lines (i) data representing a flow rate of a gas through that gas flow line, (ii) data representing a pressure of the gas in that gas flow line, and (iii) data representing an additive included in the gas in that gas flow line, such as a substance for inhibiting corrosion. For each of the gas flow lines, the system uses a computerized neural network to determine a risk of corrosion associated with that gas flow line based on the properties of that gas flow line, determines whether the metric for that gas flow line is greater than a threshold level, and if so, generates a notification for presentation to a user.

Abstract: The present disclosure relates to a device and method for measuring wafers. The device comprises: a moving platform, which is used to adjust the location of wafers; a first pre-alignment module and a first image recognition module, which are used to align a first wafer at a first location on the moving platform before measuring the first wafer; a second pre-alignment module and a second image recognition module, which are used to align a second wafer at a second location on the moving platform before measuring the second wafer; and a measurement module, which is used to measure the first wafer and the second wafer at a third location on the moving platform, wherein the first location, second location and third location are different from each other. The embodiments of the present disclosure may improve the measurement efficiency of the device.

Abstract: A method includes operating a digital simulator to mimic loading effects of digital circuit blocks of a circuit design on analog circuit blocks of the circuit design. The digital simulator sets a current signal timing and a current level value at an analog/digital boundary between the digital circuit aspects and the analog circuit aspects. The analog simulator is operated to apply the current signal timing and the current level value to simulate the analog circuit blocks.

Abstract: Computing devices, computer-readable storage media, and computer-implemented methods are disclosed for prediction of capacity. In a central tier, central-tier benchmark values are generated from benchmark testing performed on different test configurations in a reference execution environment. In a deployment tier, deployment-tier benchmark values are generated from benchmark testing performed on a baseline deployed configuration in many execution environments. A sizing model is learned from the central-tier benchmark values to predict execution platform requirements given a set of workload input parameters. A performance model is learned from the deployment-tier and the central-tier benchmark values to predict a performance delta value reflecting relative performance between a particular execution environment and the reference execution environment. The performance delta value is used to adjust predicted execution platform requirements to tailor the prediction to a particular execution environment.

Abstract: Systems and methods generate synthetic sensor data, such as synthetic radar, lidar, and/or sonar data from three dimensional (3D) scene data that may be custom designed. Reflectivity coefficients in the radar, lidar, and/or sonar spectrums may be determined for objects included in the 3D scene data. The reflectivity coefficients may be utilized by a game engine for computing the synthetic sensor data. The synthetic sensor data may be used in the creation, evaluation, and/or verification of a design for a controller or other system that utilizes such data.

Abstract: A method of estimating aging of an integrated circuit (IC) includes: obtaining a first process design kit (PDK) including a plurality of first device models corresponding to a plurality of devices provided by a process of fabricating the IC; obtaining values of aging parameters of device instances included in a netlist defining the IC, by performing a first circuit simulation based on the netlist and the first PDK; and obtaining aging data of the IC by performing a second circuit simulation based on the values of the aging parameters and the netlist, wherein each of the plurality of first device models includes at least one measurement command to be executed in the first circuit simulation to calculate an aging parameter.

Abstract: A model generation system generates three-dimensional object models based on two-dimensional images of an object. The model generation system can apply an iterative gradient decent process to model parameters for part models within an object model to compute a final set of model parameter values to generate the object model. To compute the final set of model parameter values, the model generation generates a reference image of the object model and compares the reference image to a received image. The model generation system uses a differentiable error function to score the reference image based on a received image. The model generation system updates the set of model parameter values based on the score for the reference image, and iteratively repeats the process until a reference image is sufficiently similar to the received image.

Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Abstract: An apparatus for device motion aware temporal denoising includes a processor and a memory that stores code executable by the processor to receive video data comprising a sequence of video frames that includes a current frame and one or more preceding frames captured by a video capture device that functions as a camera of a portable electronic device. In various examples, the code causes the processor to determine one or more camera motion compensation adjustments to apply to the one or more preceding frames of the sequence based on one or more non-imaging device motion sensor measurements for the video capture device and to generate a sequence of camera-motion compensated preceding frames by applying the one or more camera motion compensation adjustments to the preceding frames of the sequence. A method and a computer program may perform the functions of the apparatus.

Abstract: A substrate treatment method includes: generating, for each of layers constituting a stacked film on a substrate, a captured image of the substrate after a treatment regarding a relevant layer; and acquiring information indicating a feature amount estimated based on the captured image for each of a plurality of layers including an outermost layer of the stacked film on the substrate.

Abstract: A DC/DC converter fault diagnosis method based on an improved sparrow search algorithm, includes: establishing an simulation module of the converter, selecting a leakage inductance current of a transformer as a diagnosis signal, and collecting diagnosis signal samples under OC faults of different power switching devices of the converter as a sample set; improving a global search ability of a sparrow search algorithm by using a Levy flight strategy; dividing the sample set into a training set and a test set, preliminarily establishing an architecture of a deep belief network, and initializing network parameters; optimizing a quantity of hidden-layer units of the deep belief network by using an improved sparrow search algorithm, to obtain a best quantity of hidden-layer units of the deep belief network; and training an optimized deep belief network obtained based on the improved sparrow search algorithm, and obtaining a fault diagnosis result based on a trained network.

Abstract: Systems and methods presented herein provide a server that receives a drawing. The server matches assembly types to elements in the drawing and inserts a symbol overlay into the drawing. The symbol overlay includes metadata identifying the assembly types in the drawing. The assembly types are matched to assemblies, including kits, based on user-identified criteria, such as vendor and building codes. The system can then determine logistics for delivering the kits, automatically staggering shipment where dictated by build order of the kits.

Abstract: A processing method of chip probing data includes: determining a new fail bit generated in an already completed chip probing process; acquiring repair record of the new fail bit, and repair records of bits adjacent to the new fail bit; analyzing the repair records to determine attribute information of the new fail bit and the adjacent bits, the attribute information including at least one of address information, redundant circuit information, element pattern of the new fail bit and chip probing flow; performing classification learning according to the attribute information to acquire a fail bit prediction model; and predicting fail bits to be chip-probed through the fail bit prediction model.

Abstract: A machine learning hardware accelerator architecture and associated techniques are disclosed. The architecture features multiple memory banks of very wide SRAM that may be concurrently accessed by a large number of parallel operational units. Each operational unit supports an instruction set specific to machine learning, including optimizations for performing tensor operations and convolutions. Optimized addressing, an optimized shift reader and variations on a multicast network that permutes and copies data and associates with an operational unit that support those operations are also disclosed.

Abstract: Techniques for sequence to sequence (S2S) model building and/or optimization are described. For example, a method of receiving a request to build a sequence to sequence (S2S) model for a use case, wherein the request includes at least a training data set, generating parts of a S2S algorithm based on the at least one use case, determined parameters, and determined hyperparameters, and training a S2S algorithm built from the parts of the S2S algorithm using the training data set to generate the S2S model is detailed.

Abstract: A method of generating a layout diagram of an IC device includes assigning a leakage constraint to a first schematic net of the IC device and determining a violation of the leakage constraint based on a dummy gate region. The IC layout diagram includes the dummy gate region between a first component of the first schematic net and a second component of a second schematic net of the IC device. The method includes modifying the IC layout diagram in response to the leakage constraint violation, and generating a layout file based on the modified IC layout diagrams.

Abstract: Detecting a counterfeit status of a target device by: selecting a set of frequencies that best reflect load dynamics or other information content of a reference device while undergoing a power test sequence; obtaining target electromagnetic interference (EMI) signals emitted by the target device while undergoing the same power test sequence; creating a sequence of target kiviat plots from the amplitude of the target EMI signals at each of the set of frequencies at observations over the power test sequence to form a target kiviat tube EMI fingerprint; comparing the target kiviat tube EMI fingerprint to a reference kiviat tube EMI fingerprint for the reference device undergoing the power test sequence to determine whether the target device and the reference device are of the same type; and generating a signal to indicate a counterfeit status based at least in part on the results of the comparison.

Abstract: An example of the instant solution comprises at least one of receiving an encrypted data and an encryption key, generating a randomized matrix, dispersing the encrypted data based on the randomized matrix resulting in a fragmented encrypted data and dispersing the encryption key based on the randomized matrix and the fragmented encrypted data.

Abstract: A method and system for generating automated front-end code for a website from design files is described. In one embodiment, a method for generating automated front-end code for a website includes obtaining at least one design file associated with a design of a website from a client device. Hypertext markup language (HTML) code and a cascading style sheet (CSS) file is automatically generated from the at least one design file from information obtained from a plurality of layers associated with the design file. The method includes extracting a plurality of extracted image files from the at least one design file. The method further includes providing front-end code for the website that includes the HTML code, the CSS file, and the plurality of extracted image files to the client device.

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

Abstract: The innovation disclosed and claimed herein, in one aspect thereof, comprises systems and methods of automatic classification and modeling. The innovation can include determining a failure history of networked architecture, the failure history including data immediately prior to failure. The innovation can include machine learning the failure history to determine failure indicators. The innovation can include generating a black hole model based on the failure history and the machine learning. The innovation can include monitoring a networked architecture. The networked architecture has a set of elements comprising software elements and hardware elements interconnected in a common environment. Each element of the set of elements is monitored. The innovation can include determining an element is trending towards a failure. The trend is determined by a black hole model. The innovation can include enabling security features to prevent the element from failure.

Abstract: One exemplary aspect describes systems and methods for determining normal SLE behavior, determining when a SLE exhibits abnormal deterioration, and determining whether to take an action to mitigate what appears to be an indication of an abnormal SLE.

Abstract: The invention concerns a method for measuring a power (Pe, Pm) of an electric motor, that involves measuring a real current (I) of the motor, by means of a measurement sensor (11), the invention being characterised in that it involves inputting, on an interface (20), at least one piece of nominal power data (Pn), one piece of nominal speed data (Wn), one piece of nominal current data (In), one piece of nominal voltage data (Un), one piece of power factor data (cos ?) and the real current (I) of the engine, calculating, in the computer, a no-load current of the motor according to a first stored function depending on at least the data (Pn, In, Un, cos ?), calculating, in the computer, the active power (Pe) and/or the mechanical power (Pm) and/or the active energy and/or the mechanical energy according to at least one second stored function depending on at least the data (Pn, In), the real current (I) and the no-load current that has been calculated, and providing the power that has been calculated on an output

Abstract: Disclosed are exemplary embodiments of electrostatic discharge (ESD) pulse generators that may provide improved system level ESD robustness characterization and qualification analysis.

Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.

Abstract: Parameters associated with a distributed network are received. A topology of a virtual network that corresponds to the distributed network is generated in view of the received parameters. The topology of the virtual network is configured to simulate the distributed network and a simulation of the distributed network is executed using the configured virtual network.

Abstract: A system and method are provided to enable non-quantum experts to schematically represent, simulate and quantify the performance of physically realistic photonic quantum circuits. The framework offers the flexibility for users—not necessarily familiar with the fundamentals of quantum mechanics—to create circuits and work with simple inputs and outputs, while the complexities of manipulating high dimensionality quantum Hilbert spaces supporting photonic and physical quantum object states are handled with the use of purpose-built tools. The tools include a user-friendly method for defining classical photonic circuits which may be coupled to physical objects such as qubits, quantum input states, as well as classical and quantum measurement devices. The tools feature classical-to-quantum S-matrix conversion, quantum S-matrix extraction, as well as capabilities for defining and extracting quantum error parameters.

Abstract: A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

Abstract: A Method for simulating, on a computer processing unit including a semiconductor integrated circuit, the operation of a quantum circuit model, which includes the operations of: dividing the quantum circuit into d adjacent layers Lk intended to be successively traversed by the n qubits taken together, each layer including a single quantum gate Gk; and assigning a type to each quantum gate Gk of the circuit, among three predefined types of quantum gates. The three types are: Diagonal type gate, for which the transfer matrix is diagonal; Conventional type gate, for which the transfer matrix is non-diagonal and includes operators having a value of 0 or 1, with only one operator per row and per column; and Dense type gate, which is neither conventional nor diagonal in type.

Abstract: A hybrid electromagnetic transient simulation method for microgrid real-time simulation, wherein a traditional node analysis method (NAM) and a highly parallel latency insertion method (LIM) are combined, so that the microgrid is firstly divided from a filter of a distributed power generation system to form one latency insertion method (LIM) network containing a power distribution line and a plurality of node analysis method (NAM) networks containing the distributed power generation system respectively, the NAM network being simulated by traditional node analysis method, the LIM network being simulated by the latency insertion method, in an initialization stage, one correlation matrix and four diagonal matrixes containing line parameters used for LIM network simulation being formed according to line topology and parameters of the microgrid, in a main cycle of the simulation, the LIM network solved simultaneously with multiple NAM networks, a parallelism of a microgrid simulation being improved.

Abstract: An open market system includes: an information collection circuit that collects prediction information indicating details of a game predicted by prediction sellers; an entry acceptance circuit that accepts entry of tokens possessed by prediction purchasers; an information presentation circuit that presents, to the prediction purchasers who have entered the tokens, the prediction information collected by the information collection circuit and optimum prediction information based on the prediction information; and a distribution execution circuit that distributes, to one or more of the prediction sellers, the tokens entered by one or more of the prediction purchasers for the optimum prediction information.

Abstract: A system analysis support device includes a data acquisition part that obtains time series data (items) measured in a system that is to be analyzed, an overall abnormality degree calculation part that calculates transition of abnormality degree representing overall abnormality degree of the system that is to be analyzed, using a predictive model generated so that, with 2 or more time series data (items) as input, values representing a relationship between the 2 or more time series data (items) are outputted, and the time series data (items), and a representative index selection part that selects and presents time series data (items) indicating change similar to transition of the overall abnormality degree of the system that is to be analyzed, from among the time series data (items).

Abstract: Aspects of the disclosed technology relate to techniques of activity coverage assessment. Transistor-level circuit simulation is performed for a circuit design under a set of test stimuli, which determines values of one or more electrical properties for each of circuit elements of interest in the circuit design. The one or more electrical properties are selected based on information of the each of circuit elements of interest, which comprises what circuit element type the each of circuit elements of interest belongs to. Based on the values of the one or more electrical properties, activity coverage information comprising information about which circuit elements in the circuit elements of interest are active or inactive under the set of test stimuli is determined.

Abstract: A converter parameterized constant admittance modeling method based on a cross initialization including the following steps: (1) performing parameterized modeling on a converter, wherein switches are modeled using a parametric historical current source constant admittance model and other components are modeled using a traditional electromagnetic transient simulation integral model in the converter; (2) detecting whether state switching occurs, performing cross initialization correction when occurring; (3) determining model parameters, and establishing an equivalent admittance matrix and an injection current source of a whole grid, to obtain an electromagnetic transient simulation equivalent model; (4) solving a network tide according to a basic solving equation I=YU to obtain an electromagnetic transient model simulation result of the converter at current time; and (5) calculating an equivalent admittance matrix and an injection current source at next time through a current network state quantity, and returni

Abstract: An imaging device capable of detecting differences with low power consumption is provided. The imaging device includes a pixel including a photoelectric conversion element and a transistor; an analog processing circuit; and a digital processing circuit. The imaging device is operated in a first mode and a second mode. In the first mode, the analog processing circuit detects a difference between first imaging data taken by the pixel and second imaging data taken by the pixel and generates a trigger signal on the basis of the value of the difference. In the second mode, the digital processing circuit converts third imaging data taken by the pixel into digital data. Switching from the first mode to the second mode is performed on the basis of the trigger signal.

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

Abstract: A method related to authenticating a device may include accessing a plurality of hash values, wherein the plurality of hash values corresponds to a plurality of passwords of a plurality of devices. The method may also include generating a hash value corresponding to the device and authenticating the device by providing the plurality of hash values and the hash value to an authentication system.

Abstract: Disclosed herein are system, method, and computer program product embodiments for determining an appropriate FPGA for a particular computer program. An embodiment operates by a central processing unit's counter identifying a plurality of workload properties in processing a computer program, wherein the central processing unit is part of a first computer architecture. The central processing unit then sends the workload properties to a controller trained to identify a field-programmable gate array (FPGA) module based on the plurality of workload properties. The central processing unit thereafter receives a recommended FPGA module from the controller and implements the recommended FPGA module in a computer architecture for processing the computer program, whereby the second computer architecture is able to perform the computer program more efficiently than the first computer architecture.

Abstract: Systems and methods are described to create a comprehensive model from multiple input data sources in distributed manner for performing diagnostics and/or prognostics of a complex system/platform having its modules/parts implemented independent of each other. In an embodiment, the proposed system for creating a comprehensive connected model of a complex platform includes a input data receive module configured to receive data/content/information from one or more input data sources associated with different modules of the complex platform in a distributed manner, a dependency determination module configured to analyze a plurality of entities/variables retrieved from the data and determine dependency relationships between the plurality of entities by creating a edge list, and a connected model creation module configured to create a comprehensive connected model (connected graph) from the edge list.