Circuit Simulation Patents (Class 703/14)
  • Patent number: 10262093
    Abstract: A computer implemented system and method of computer implemented method of instrumentation of an electronic design comprising receiving by a computer a computer readable representation of said electronic design having at least in one part of said electronic design, an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is received and at least one set of valid states is generated based on said at least one specification. An analog verification coverage is determined utilizing said at least one instrumented netlist.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 16, 2019
    Assignee: Zipalog, Inc.
    Inventors: Felicia James, Michael Krasnicki
  • Patent number: 10263956
    Abstract: A physical level-based security system for data security of a security terminal and a method using the system. The security system includes at least one normal terminal corresponding to an external network, a security terminal corresponding to an internal network and storing sensitive data, and an interface device for transmitting input information of a user to any one of the at least one normal terminal and the security terminal, and providing unidirectional transmission service from the at least one normal terminal to the security terminal.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: April 16, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yunkoo Lee, Donggeon Lee, Minkyu Joo, Sangwoon Yang
  • Patent number: 10248581
    Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: April 2, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jan M. J. Janssen, Thorsten H. Grötker, Christoph Schumacher, Rainer Leupers
  • Patent number: 10247970
    Abstract: A display includes an integrated strain-gauge layer in or on the display for measuring the strain at a plurality of locations on the display. The display is deformable and secured to a display device by a first chassis. A method includes measuring, over a period of time, strain of the display of a first device at the plurality of locations and recording the strain measurements in a memory of the display device. Strain measurements associated with a failure of the display may be identified. The method may include simulating a dynamic system including a model of a second device. The model of the second device includes a model of a second chassis different than the first chassis and a model of the display associated with the failure. Simulating the dynamic system may include simulating deformation of the model of the display based on the identified strain measurements.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: April 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rohit Krishna Koppal, Chandrashekar Gernipalli Subba
  • Patent number: 10241958
    Abstract: A system includes operational circuit blocks associated with configurable counter circuits. A configurable counter circuit is configured to control event signal when counting expires and includes a mode input configured to receive a setting of a programmable control event asynchronous mode and a programmable control event synchronous mode. Depending on the programmed mode and whether a control event has occurred in a previous synchronization period, the configurable counter circuit processes an associated operation responsive to issuance of a synchronization instruction or to issuance of a subsequent control event.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: March 26, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Avdhesh Chhodavdia, Michael S. Fenton, Sheethal Somesh Nayak
  • Patent number: 10223485
    Abstract: Aspects of the disclosed technology relate to techniques of voltage-based reliability verification. Voltage values on nets of a circuit design are determined based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits. The one or more subcircuits are identified based on circuit topology recognition. The determined voltage values are analyzed to detect problems in the circuit design.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 5, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Mark E. Hofmann
  • Patent number: 10216879
    Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: February 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Shun Huang, Wai-Kit Lee, Ya-Chin Liang, Cheng Hsiao, Juan-Yi Chen, Li-Chung Hsu, Ting-Sheng Huang, Ke-Wei Su, Chung-Kai Lin, Min-Chie Jeng
  • Patent number: 10216552
    Abstract: Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jatin Bhartia, Matthias D. Heizmann, Ajit S. Honnungar, Parminder Singh
  • Patent number: 10216870
    Abstract: A computer-implemented method for evaluating a circuit design to protect a plurality of metal connections from current pulse damage, the method includes receiving a circuit design including the plurality of metal connections and evaluating a maximum peak current of one or more of the plurality of metal connections. The method further includes determining a peak current threshold for the plurality of metal connections based on physical characteristics of the plurality of metal connection and responsive to determining that the maximum peak current of the one or more of the plurality of metal connections exceeds the peak current threshold, performing a peak current design modification to modify the plurality of metal connections in the circuit design.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeanne P. S. Bickford, Nazmul Habib, Baozhen Li, Tad J. Wilder
  • Patent number: 10211993
    Abstract: An authenticating circuit includes a first and second challenge vector input, a first and second highly variable process-dependent circuit and a logic circuit. The first highly variable process-dependent circuit receives a first vector from the first challenge vector input and generates a first output that is a function of the first vector and at least one process-dependent feature of a component of the first highly variable process-dependent circuit. The second highly variable process-dependent circuit receives a second vector from the second challenge vector input and generates a second output that is a function of the second vector and at least one process-dependent feature of a component of the second highly variable process-dependent circuit. The logic circuit generates a response output that is a function of the first output and the second output. The function operates so that the response output is independent of environmental conditions of the authenticating circuit.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 19, 2019
    Assignee: Georgia Tech Research Corporation
    Inventors: Sabyasachi Deyati, Abhijit Chatterjee, Barry John Muldrey
  • Patent number: 10210064
    Abstract: Systems and methods for device compatibility testing and reporting are disclosed. An exemplary method includes outputting, by a testing computer station, instructions for executing a plurality of certification tests on a device under test. The method includes receiving result indications and corresponding certification test identifiers corresponding to each of the plurality of certification tests, and generating, by the testing computer station, compressed test results for each of the plurality of certification tests. The method includes combining at least a portion of the compressed test results into a reduced data report. The method includes sending, by a computer network in communication with the testing computer station and a remote server, the reduced data report to the remote server.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: February 19, 2019
    Assignee: Google LLC
    Inventor: Zhonglei Wang
  • Patent number: 10204196
    Abstract: A system and method are provided that reduce the amount of time required to perform transient circuit and envelope transient circuit simulations. The total simulation time is partitioned into n simulation segments of equal lengths of time and adjacent simulation segments are overlapped in time by a predetermined overlap time period, Tov. The simulation segments are then simulated in parallel and the simulation results are merged into a final simulation waveform. The predetermined overlap time period Tov is determined using a non-iterative process that can be performed very quickly. Consequently, the overall amount of time that is required to perform the simulation is greatly reduced.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: February 12, 2019
    Assignee: Keysight Technologies, Inc.
    Inventors: Philippe Torregrossa, Arnaud Soury
  • Patent number: 10204197
    Abstract: A coupled-domains method for generating disturbance matrices used in correcting topography proximity effects (TPE) for integrated circuit (IC) designs that include inhomogeneous substrates. The IC design is modeled and divided into domains (z-direction regions), each domain defined by upper/lower horizontal domain boundaries and optical properties generated by its associated geometry and material composition. Fourier-space representations are utilized to determine discrete electrical and magnetic field components for each domain that are integrated to derive domain transfer matrices, which are then multiplied to produce a total transfer matrix, which is then used to generate the disturbance matrix. The disturbance matrix may then be utilized by a model-based mask correction tool to calculate light intensity values in the photoresist layer. The corrected mask design is then used to generate a physical mask utilized in the subsequent fabrication of an IC device based on the IC design.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 12, 2019
    Assignee: Synopsys, Inc.
    Inventors: Nikolay B. Voznesenskiy, Ralf Juengling
  • Patent number: 10199077
    Abstract: A memory arrangement and method to arrange memories are disclosed. The memory arrangement comprises at least two memory chips (M1, M2) arranged on a Printed Circuit Board, PCB. A first memory chip (M1) is arranged on a first surface of the PCB, a second memory chip (M2) is arranged on a second surface of the PCB. The second memory chip (M2) is placed back to back to the first memory chip (M1) and oriented such that respective pins having the same function on the first memory chip (M1) and the second memory chip (M2) are placed opposite to each other and connected by vias to respective signal traces arranged between the first and second surfaces of the PCB.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: February 5, 2019
    Assignee: Axis AB
    Inventor: Henrik Hovmoller
  • Patent number: 10185795
    Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: January 22, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Praveen Ghanta, Arun Kumar Mishra
  • Patent number: 10185799
    Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: January 22, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
  • Patent number: 10176276
    Abstract: An apparatus and method for determining an optimal global quantum value for use in event-driven simulations of a device are disclosed herein. The device is simulated using information representative of a device design corresponding to the device, the simulation of the device comprising an event-driven simulation using a provisional global quantum value. Events included in a sequence chart corresponding to the simulation using the provisional global quantum value are compared against expected events. Based on the comparison detecting at least one of the expected events being absent in the sequence chart, providing the optimal global quantum value as being smaller than the provisional global quantum value. Based on the comparison detecting no difference between the events in the sequence chart and the expected events, providing the optimal global quantum value as being larger than the provisional global quantum value.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 8, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qizhang Chao, Neeti K. Bhatnagar, George F. Frazier, Tuay-Ling Kathy Lang, Andrew Wilmot
  • Patent number: 10169503
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Patent number: 10169507
    Abstract: An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Cheng Kuo, Wei-Yi Hu
  • Patent number: 10169526
    Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerim Kalafala, Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Adam P. Matheny, Jose L. Neves, Gregory M. Schaeffer
  • Patent number: 10152557
    Abstract: Systems and methods offer an efficient approach to computing similarity rankings in bipartite graphs. An example system includes at least one processor and memory storing a bipartite graph having a first set and a second set of nodes, with nodes in the first set being connected to nodes in the second set by edges. The memory also stores instructions that, when executed by the at least one processor, cause the system to assign each node in the second set to one of a plurality of categories and, for each of the plurality of categories, generate a subgraph. The subgraph comprises of a subset of nodes in the first set and edges linking the nodes in the subset, where the nodes in the subset are selected based on connection to a node in the second set that is assigned to the category. The system uses the subgraph to respond to queries.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: December 11, 2018
    Assignee: Google LLC
    Inventors: Seyed Vahab Mirrokni Banadaki, Silvio Lattanzi, Jonathan Ezra Feldman, Alessandro Epasto, Stefano Leonardi, Hugh Lynch, Varun Sharma
  • Patent number: 10146895
    Abstract: The present invention discloses a method for simulating a digital circuit comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hongwei Dai, Gongqiong Li, Jia Niu, Zhenrong Shi, Lei Wang
  • Patent number: 10146036
    Abstract: In the methods and systems, optical images of inspection care areas on a semiconductor wafer are acquired and analyzed to detect defects. However, during this analysis, the same threshold setting is not used for all inspection care areas. Instead, care areas are grouped into different care area groups, based on different design layouts and properties. Each group is associated with a corresponding threshold setting that is optimal for detecting defects in the inspection care areas belonging to that group. The assignment of the care areas to the different groups and the association of the different threshold settings with the different groups are noted in an index. This index is accessible during the analysis and used to ensure that each of the inspection care areas in a specific care area group is analyzed based on a corresponding threshold setting that is optimal for that specific care area group.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Parul Dhagat, Ananthan Raghunathan, Vikas Sachan, Dmitry A. Vengertsev
  • Patent number: 10140639
    Abstract: Technologies are generally provided to integrate hardware accelerators in datacenters. In some examples, a datacenter customer may provide a hardware accelerator configuration to be implemented at a datacenter. The hardware accelerator configuration may include, for example, one or more customer accelerator blocks and one or more accelerator blocks. The datacenter may retrieve the accelerator block(s), integrate the accelerator block(s) with the customer accelerator block(s) to form the hardware accelerator, and then implement the hardware accelerator. In other examples, the datacenter may charge the customer for use of the accelerator block(s), but refrain from providing the accelerator block(s) to the customer.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: November 27, 2018
    Assignee: Empire Technology Development LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 10131299
    Abstract: Disclosed is a method for controlling the voltage of an electrical apparatus of a motor vehicle. The method includes the steps of measuring (E2) the voltage at the terminals of the apparatus and measuring (E3) the strength of the output current of the apparatus, calculating (E4) the values of resistance, inductance and capacitance of the equivalent circuit on the basis of the measured current strength and the measured voltage, comparing (E7, E8, E9) the calculated values of resistance, inductance and capacitance with the values of resistance, inductance and capacitance, respectively, stored in a storage area of the electronic control unit, and initiating (E12) an action if the difference between at least one of the calculated values and the corresponding stored value is above a predetermined threshold.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: November 20, 2018
    Assignees: CONTINENTAL AUTOMOTIVE FRANCE, CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Arnaud Pinel, Stephane Vitali
  • Patent number: 10127339
    Abstract: When a communication unit of an FPGA receives emulated signals of a design under test that are to be transmitted to another FPGA, the communication unit analyzes each signal to determine whether a signal event has occurred for the signal. The communication unit transmits to the other DUT FPGA a packet indicating for which signals a signal event has occurred. Subsequently, the communication unit transmits a packet for each signal for which an event has occurred.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: November 13, 2018
    Assignee: Synopsys, Inc.
    Inventor: Ludovic Marc Larzul
  • Patent number: 10122608
    Abstract: Systems and methods are disclosed for routing messages to one or more of a plurality of user devices associated with a particular user to whom a particular message is to be provided. The message destination user device(s) may be determined by evaluating the user interactions on each of the plurality of user device. The message destination user device(s) may be selected as the user device(s) that are predicted to have a relatively high level of interaction and/or activity with the user to whom the message is to be provided or is in relative proximity of the user to whom the message is to be provided. When the message destination user device(s) are determined, the message may be transmitted to that/those message destination user device(s) for rendering to the user to whom the message is to be provided.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: November 6, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Adam Schott Riggs
  • Patent number: 10116520
    Abstract: According to an exemplary embodiment of the present disclosure, a method of generating a network-on-chip (NoC) in an electronic device includes clustering a plurality of cores based on total communication energy comprising first communication energy between a plurality of voltage-frequency-islands (VFIs) and second communication energy inside the plurality of VFIs.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 30, 2018
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Woo-Cheol Lee, Chang Lin Li, Tae Hee Han, Jinwoo Roh, Dongwook Suh
  • Patent number: 10102094
    Abstract: To address problems that arise due to differences in bus behavior when running a legacy application on a new device the new device may throttle bus performance in a way that emulates the bus behavior of a legacy device when executing the legacy application.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: October 16, 2018
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Mark Evan Cerny, David Simpson
  • Patent number: 10095886
    Abstract: A system for verifying applications for Real-Time Execution (RTE) devices is provided. The system includes a memory, at least one processor coupled to the memory, and a simulation component executable by the at least one processor. The simulation component may be configured to receive device simulation information for an RTE device, the device simulation information including device configuration information, application information, and targeted performance information, configure a virtual device simulator to simulate performance of the RTE device, run the virtual device simulator to process one or more simulated events, and output simulation results.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: October 9, 2018
    Assignee: SCHNEIDER ELECTRIC USA, INC.
    Inventors: John C. Van Gorp, Piotr Boleslaw Przydatek, Liam Somers
  • Patent number: 10083257
    Abstract: A method includes determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Cheng Kuo, Wei Min Chan, Wei-Yu Hu, Jui-Feng Kuan
  • Patent number: 10078715
    Abstract: Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 18, 2018
    Assignee: Synopsys, Inc.
    Inventors: Friedrich Gunter Kurt Sendig, Donald John Oriordan, Jonathan Lee Sanders, Salem Lee Ganzhorn, Barry Andrew Giffel, Hsiang-Wen Jimmy Lin
  • Patent number: 10073933
    Abstract: Analysis of a first verification test suite automatically generates properties that may be directly used in a subsequent verification test suite. For example, an IP module may be verified by executing a software simulation test suite. The resulting data is accessed and analyzed to detect a set of properties of the software simulation test suite. A set of emulator-synthesizable properties are selected from the set of detected properties. The emulator-synthesizable properties are suitable for incorporation in a hardware emulation test suite used to test the SoC.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: September 11, 2018
    Assignee: Synopsys, Inc.
    Inventors: Yuan Lu, Lawrence Vivolo, Nitin Mhaske
  • Patent number: 10073932
    Abstract: Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (DUT). In one aspect, a host system configures an emulator to implement the DUT. The DUT includes the embedded processing unit and a memory unit. The host system configures the emulator to execute design instructions for testing an operation of the DUT through the embedded processing unit. The host system receives a stream of values stored by the memory unit of the DUT. The values indicate execution results of the design instructions executed by the embedded processing unit. The host system stores the stream of the values and generates a log file for recreating one or more states of the embedded processing unit based on the stored stream of the values.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: September 11, 2018
    Assignee: Synopsys, Inc.
    Inventors: Alexander John Wakefield, Jefferry Phuong Vo, Joerg Horst Richter, Kai Thorsten Schuetz
  • Patent number: 10055318
    Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 21, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-hoon Jeong, Ho-young Kim, Soo-jung Ryu
  • Patent number: 10055520
    Abstract: According to an embodiment, a process simulator has a layout processing unit to extract vertex coordinates of a first graphic of a layout of a semiconductor device described in a layout file used for a simulation, an initial mesh generation unit to generate a first initial mesh passing through the vertex coordinates in a plane direction of the layout, and a simulator unit to execute a process simulation of the semiconductor device based on simulation data in which a process flow of the semiconductor device is described, the layout, and the first initial mesh.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: August 21, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mitsutoshi Nakamura
  • Patent number: 10044451
    Abstract: Method for testing multiple signal transceiver devices under test (DUTs), such as data packet signal transceivers, with a shared DUT testing resource, such as a tester having a single vector signal generator (VSG) and a single vector signal analyzer (VSA). Requests by the DUTs for access to tester resources (e.g., to receive signals from the signal generator or provide signals to the signal analyzer) are prioritized based upon tester availability and whether the requesting DUT requires sole access or can share access to the tester. If the tester is unavailable, DUT requests are queued according to their respective priorities to await tester availability. As a result, access to shared tester resources can be managed dynamically to minimize test time while testing multiple DUTs concurrently.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: August 7, 2018
    Assignee: LITEPOINT CORPORATION
    Inventors: Jonathan Barry Hirst, Adam Martin Smith
  • Patent number: 10031986
    Abstract: The present disclosure relates to a system and method for performing Path-Based Analysis (PBA) of an electronic circuit design. Embodiments may include receiving a command to create a spice deck of a timing path associated with the electronic circuit design. In response to receiving the command, embodiments may further include initiating PBA for the timing path and identifying one or more stages within the timing path. Embodiments may also include performing a delay calculation for each of the one or more stages and generating a stage spice deck for each of the one or more stages based upon, at least in part, information from the delay calculation, wherein the stage spice deck encapsulates all elements of the stage. Embodiments may further include connecting the stage spice deck for each of the one or more stages in series to form a complete path spice deck.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 24, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vishnu Kumar, Manuj Verma
  • Patent number: 10032497
    Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: July 24, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Alejandro F. Gonzalez
  • Patent number: 10024910
    Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: July 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Patent number: 10024904
    Abstract: An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having program instructions, are operable to: receive a number m of individual devices within an ensemble device; identify a sub-threshold slope; determine an uplift factor; separate random variation in logarithm of a leakage current into a correlated random component and an uncorrelated random component; determine a first standard deviation of correlated random component for the ensemble device; determine a second standard deviation of the uncorrelated random component for the ensemble device; generate a statistical model for electrical features of the ensemble device, based on the number m of individual devices, the sub-threshold slope, the uplift factor, the first and second standard deviation, and statistical random variables; and determine the electrical features of the ensembl
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: July 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Ning Lu
  • Patent number: 10025888
    Abstract: A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ui-Hui Kwon, Vasily Zabelin, Sachio Nagura, Keun-Ho Lee
  • Patent number: 10019545
    Abstract: A method includes receiving input information related to devices of an integrated circuit. A first simulation of the integrated circuit is performed over a first time period. Average temperature changes of the devices over the first time period are calculated. A second simulation of the integrated circuit is performed over a second time period using the average temperature changes of the devices. The first simulation and the second simulation are executed by a processor unit.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Min-Chie Jeng, Chung-Kai Lin, Ke-Wei Su, Yi-Shun Huang, Ya-Chin Liang, Cheng Hsiao, Juan Yi Chen, Wai-Kit Lee
  • Patent number: 10019540
    Abstract: A method is disclosed that includes performing a first simulation by applying first variations to identify at least one sample of an integrated circuit (IC), wherein the IC comprises at least one device; translating individual variables of split devices implementing the at least one device, to an equivalent variable for the split devices; and performing a second simulation, by applying at least a portion of second variations, with the equivalent variable for the split devices, to obtain a simulation result serving as a basis of modifying the layout for fabrication of the IC.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Cheng Kuo, Wei-Yi Hu, Kuang-Ming Wang
  • Patent number: 10002217
    Abstract: Methods and systems are disclosed related to region based device bypass in circuit simulation. In one embodiment, a computer implemented method of performing region based device bypass in circuit simulation includes receiving a subcircuit for simulation, where the subcircuit includes a plurality of devices, and determining node tolerance of the plurality of devices. The computer implemented method further comprises for each device in the plurality of devices, determining whether the device has entered into a bypass region using the node tolerance of the plurality of devices, performing model evaluation in response to the device has not entered the bypass region, and skipping model evaluation in response to the device has entered the bypass region.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: June 19, 2018
    Assignee: PROPLUS DESIGN SOLUTIONS, INC.
    Inventors: Bruce W. McGaughy, Zhenzhong Zhang, Jun Fang, Xinjun Niu
  • Patent number: 9996648
    Abstract: The present disclosure relates to customization of a circuit layout using information from a netlist, and more particularly, to customization of a circuit layout using embedded formulas and a netlist. The system includes a CPU, a computer readable memory, and a computer readable storage device. The system also includes first program instructions to generate a graphical layout of a circuit, second program instructions to place a text formula on the graphical layout of the circuit, and third program instructions to activate the text formula in order to customize the graphical layout of the circuit. The first program instructions, the second program instructions, and the third program instructions of the system are stored on the computer readable storage device for execution by the CPU via the computer readable memory.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: June 12, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Dale E. Pontius
  • Patent number: 9990458
    Abstract: A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: June 5, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Davinder Aggarwal, Vaibhav A. Ruparelia, Neha Singh, Janakiraman Viraraghavan
  • Patent number: 9978152
    Abstract: A method for a system to generate a recipe for performing wafer alignment, includes: generating first and second alignment data sets, the first alignment data set including image information regarding a first site on a wafer and coordinates of characteristic points at the first site, and the second alignment data set including image information regarding a second site different than the first site on the wafer and coordinates of characteristic points at the second site; and saving the generated first and second alignment data sets as a recipe for wafer alignment; wherein the generating of the first alignment data set includes: selecting, as the first site, a site including a characteristic pattern on the wafer; determining first and second characteristic points at the selected site; and recording coordinates of the determined first and second characteristic points.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: May 22, 2018
    Assignee: Raintree Scientific Instruments (Shanghai) Corporation
    Inventor: Jian Zhou
  • Patent number: 9977850
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 22, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Patent number: 9959377
    Abstract: Presented herein are systems, methods, and devices for analyzing a circuit. A netlist is obtained and parsed, where the netlist describes the circuit having one or more branches and one or more nodes. A linear system describing the circuit is obtained and compressed using a hierarchical approach. Compression involves storing off-diagonal sub-blocks in a dense matrix in a low-rank format to reduce the density of the matrix. The linear system is then solved using an iterative operation. An initial guess is used for the voltage at each node and the current through each branch. After performing the first iteration, an initial estimate for the voltage and current is stored and used as the initial guess for the second iteration. The iterative operation is continued until the estimate for the voltage at each node and the current through each branch is sufficiently accurate.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: May 1, 2018
    Assignee: Helic, Inc.
    Inventors: Konstantis Daloukas, Nestor Evmorfopoulos