Abstract: Approaches for managing a simulation model. A processor-implemented method includes simulating an electronic system using the simulation model and a simulator. The simulation model includes an assertion test that has an associated limit. The simulator counts a number of times the assertion test is evaluated during simulation, which is the evaluation count. When the simulator determines that the evaluation count has reached the limit, the simulation is stopped.

Abstract: A method for simulating a telecommunications network through objects that model a respective set of network modules or devices provides for the insertion, for every module or device of the set, of at least one respective interfacing object with the other modules of the set. The above interfacing object has an external side and an internal side with respect to the module or device. Such external side has a character that is independent of idiosyncrasies of such module or device and is therefore uniform for all modules or devices. When there are a plurality of different implementations of the same module or device, it is possible to provide both a unique interfacing object for all different implementations, and a respective interfacing object for every single implementation.

Abstract: According to one embodiment, a logical circuit to be simulated includes a timing network and a specific logical device. The timing network transmits a logical value change of an input signal in correspondence with an elapse of time or clock number increments. The specific logical device receives a timing network output signal that appears at an exit node of the timing network, and a logical value change or a logical value after change of the clock. When predetermined constraint information represents a constraint that a time period or the demanded number of clock cycles needed for a transition of a signal level change to pass through a signal path in the timing network is equal to or smaller than a predetermined numerical value (or equal to or larger than a predetermined numerical value), it is checked if the signal input to the specific logical device violates the predetermined constraint information.

Abstract: A method and tools for providing precise timing analysis scalable to industrial case studies with large numbers of tasks and messages are provided, including the capability to model and analyze task and message response times; ECU usage; bus usage; end-to-end latency of task/message chains; and timing synchronization problems in task/message graphs. System tasks and messages are modeled in a formalism known as calendar automaton. Models are written in a modeling language such as Promela and instrumented with code specific to the analysis specification. Models and instrumentation are automatically generated from the system description and analysis specification. The system model is subjected to exhaustive state space exploration by a compatible model checker, such as SPIN. During exploration, the instrumented code produces results for different timing analyses.

Abstract: An apparatus, method, and computer program product are provided for enabling interoperability between devices, such as a mobile terminal and some other remote device or remote environment. The apparatus may include at least one processor and at least one memory including computer program code. The at least one memory and the computer program code may be configured, with the processor, to cause the apparatus to maintain a terminal session between a server device and a client device in which the client device emulates at least a portion of a display presented at the server device; receive an indication of a user input received at the client device identifying a function to be performed at the server device; determine a corresponding input to elicit the identified function; and cause the identified function to be performed at the server device.

Abstract: The present invention comprises apparatus and systems for measuring, monitoring, tracking and simulating enterprise communications and processes. A central message repository or database is constructed, comprised of monitoring messages sent from process messaging systems. The database may then be accessed or queried as desired. A simulation tool assists in reviewing present and proposed processes and sub-processes before modifying existent systems or creating new systems.

Abstract: A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (?1) and the substrate is a second dielectric with a second permittivity (?2). The method models the capacitance (C1) for values of the first and second permittivity (?1, ?2) based on known capacitance (C2) computed for a basis structure with the same first permittivity (?1) and a different second permittivity (?2). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C1) through one or more known capacitances (C2).

Abstract: A mechanism to dynamically vary the amount of delay for an event-generated function call is discussed. The event causing the generation of the function call may be a signal-based event, function call event or some other type of event. A function call generating delay component is inserted into a DES model and dynamically adjusts the amount of delay to apply prior to generating and transmitting the function call to an intended target component. The function call generating component reads a value from an input port in determining the amount of delay. The identified value at the input port may be a signal value or an attribute associated with an event entity received at the port.

Abstract: There is provided with a software executing device co-operating with a hardware circuit or a hardware simulator, including: a software executing unit configured to execute a software; an execution monitoring unit configured to monitor execution of the software by the software executing unit to sequentially obtain an execution state of the software; a determining unit configured to determine whether the software executing unit and the hardware circuit or the hardware simulator are to be synchronized based on an obtained execution state of the software; and a synchronization controlling unit configured to control synchronization between the software executing unit and the hardware circuit or the hardware simulator.

Abstract: A system and method for integrated circuit emulation. One embodiment provides a system for in-circuit emulation of an integrated circuit device with program-controlled components. The system includes an integrated circuit device with program-controlled components used in a system for normal operation. The integrated circuit device having at least one program-controlled emulation unit emulating at least one of the program-controlled components of the integrated circuit device, and at least one statistics memory for storing statistical data of the program-controlled emulation unit during emulation.

Abstract: The invention is directed to a display and method for conducting sound system design. The display is configured to simultaneously show a sound system model comprising both audio components and sound environment components, a plurality of parameters and a graphic representation of a calculated sound system performance attribute. In response to receiving input from the user and without any additional user intervention, the display re-displays a newly-calculated sound system performance attribute such as, for example, a graphic representation in the sound system model of a sound path associated with a user-selected reflected sound identifier. A processor also simulates, based on the sound system configuration, the sound performance that a user would expect to hear positioned in an identified listening position of the sound system model.

Abstract: A computer-based simulator, separate from a computer process control system, that simplifies the electrical interconnection of the computer-based simulator to the computer control system and reduces the number of hardware components required to effect a computer-based simulator. The invention also facilitates remote configuration and operation of the control and simulator systems.

Abstract: An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system.

Abstract: A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.

Abstract: A plurality of sequential nodes in a design file for an electronic device are identified and one or more combinatorial power metric values are computed for the plurality of sequential nodes based upon an effective switching capacitance, a switching activity measure, and a power effort measure for at least a first device downstream from the each sequential node at a specified depth. The combinatorial power metric values for the plurality of sequential node are stored and compared to a target power metric value to determine if power consumption at the electronic device meets a predetermined power performance goal.

Abstract: A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein, and applying the test patterns with timing irregularities injected therein to input receivers of the DUT. A tester is configured to test loopback functionality of a device under test (DUT) utilizing a timing irregularities injection apparatus which receives timing irregularity data readable by the tester and test data generated by the DUT, and injects the timing irregularity data into the test data for application to the DUT.

Abstract: An incontinence management system for monitoring wetness in one or more absorbent articles, includes input for receiving one or more sensor signals indicative of a presence of wetness in an absorbent article, processor for processing the one or more sensor signals and for performing an analysis of the signals to characterise wetness events occurring in an absorbent article and user interface for communicating with a user of the system. A mathematical model is used to characterise wetness events, receiving as inputs variables derived from sensor signals and optionally, patient and demographic data. The mathematical model can be configured and/or re-configured utilising observation data obtained while monitoring a patient for wetness. A diaper for use with such as system is also disclosed.

Abstract: In a graphical modeling environment supporting a model having at least two different analysis frameworks operating therein, a system and corresponding method of processing the graphical model modify the model to group model portions together for processing in the same analysis framework. Model parts are identified and associated with the analysis framework in which they operate. Model parts are then grouped based on their association with their analysis framework to form model portions that operate in one of the different analysis frameworks. In instances where topological separation of model portions operating in the same analysis framework occurs, the system and method reconfigure intervening model portions to be amenable with operation in the analysis framework of the surrounding model portions to improve processing efficiency.

Abstract: An extension to a simulator (801) that allows the user to specify real numbers, voltages, and currents (808) on ports of an electrical net is presented. The computer using the analog wire functionality routines (805), the routines for determining nets (804), the net manager (803), and the pin manager (802) resolves unspecified values on said electrical nets. The user may specify at least one value on said port and may specify whether said port is driven. The extension includes additional math functions (1901).

Abstract: A method for creating entropy in a virtualized computing environment includes waking one or more samplers, each sampler having a sampling frequency; sampling a sample source with each of the one or more samplers; placing each of the samplers in an inactive state when not sampling; determining a difference between an expected value and a sampled value at each sampler; and providing a function of the difference from each of the one or more samplers to an aggregator.

Abstract: A hard/soft cooperative verifying simulator is based on a SystemC simulator, and provides the capability of reducing overhead of context switching control thereby to shorten processing time. Time keepers for controlling simulation times of a plurality of threads are provided corresponding to the threads generated as simulation models for hardware and software. Each of the time keepers has a variable which holds a simulation time for each thread, a variable which holds a summation time, and a break request queue which stores a break time and its corresponding break method therein. The time keeper manages both variables and the queue in response to six types of method invocations from the thread, and invokes a wait function of the SystemC simulator when necessary. It is thus possible to reduce the number of times that a wait function invocation is performed, and shorten the entire processing time.

Abstract: A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at least one storage unit, and simulating the segment in accordance with the state of the at least one storage unit; and the system including a memory for describing storage units of a circuit, maintaining states of the storage units, and identifying distributed segments comprising combinational logic separated by the storage units, and processing units, each for simultaneously simulating at least one of the segments in accordance with the maintained states.

Abstract: The present invention is directed to automatically analyzing software systems for identifying faults or bugs and/or detection of malicious code. In various embodiments, the present invention measures code coverage for high priority invocable program elements, uses a relaxed coverage estimation technique that, instead of guaranteeing which code units will be executed, guarantees that at least a certain number of code units will be executed, determines and solves constraints in code to identify infeasible paths containing one or more selected nodes, determines, for a composite data type, a range of values for each of at least two non-composite data fields, and/or translates, prior to code analysis complex code into simpler code having fewer operators.

Abstract: A system and a method for capturing, storing and replaying data describing application of an event-based process to an event are described. As an event processing engine processes an input event, specified data is captured by a store monitor included in the event processing engine. Hence, while the event processing engine processes an input event, data describing the event processing is contemporaneously captured without affecting processing of the input event. The captured data is then stored for later access and can be used later simulate or analyze the event processing. In one embodiment, the stored data is also classified or grouped based on one or more grouping criteria (e.g., event type, timestamp) to simplify later access to the data.

Abstract: A simulator of WBEM/CIM indication providers conforming to the CIM Indication Provider object specification simulates both the CIM indication provider and the means to drive the associated CIM events. The simulator comprises three functionally unique pieces: one or more CIM indication provider drivers, one or more CIM event trigger drivers, and a control application. This modularization creates flexibility in configuring the simulator to stress test different aspects of an operating system's underlying support for CIM indications. Modularization also makes the simulator design operating system independent. Provision is made in the simulation for generation of additional CIM events as background activity on the operating system.

Abstract: A method for modeling a system as a finite state machine in a modeling environment is discussed. Embodiments receive a representation of a finite state machine model and provide an interface for incorporating a temporal operator into the finite state machine model. The temporal operator may be a Boolean function that includes at least one event parameter and defines a temporal logic condition. Embodiments may also receive a definition of a first temporal operator that defines a logic condition related to a number of occurrences of two or more different base events.

Abstract: Method and apparatus for channel simulation is disclosed. The claimed invention provides method and apparatus 1200 to simulate a propagation channel, particularly a multiple-input-multiple-input (MIMO) channel. The claimed invention further provides a method and apparatus for efficient optimization of antenna by the enhanced channel simulation. The claimed invention takes both antenna characteristics and channel characteristics as inputs, and output time-varying channel realizations to generate the system metrics as the optimization target for antenna under optimization. The claimed invention advantageous provides enhanced channel simulation to meet the accuracy requirement of antenna evaluation.

Abstract: A system, method, and software program for facilitating the assignment of cell specifications to a plurality of cells of a system design. The methods include generating a plurality of candidate cell specifications that meet the specification for the system design. In one embodiment, the method entails using information related to intra-range preference for cell specifications to generate a set of alternative system pareto-optimal solutions which define a boundary of a region of candidate cell specifications. In another embodiment, the method entails generating a substantially uniform set of candidate cell specifications using a prediction-based performance model, such as support vector regression model or cluster-weighted model, an optimizing algorithm such as conjugate-gradient or Markov Chain Monte Carlo Method, and a sample density model.

Abstract: Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

Abstract: Methods, systems and computer products are provided for risk evaluation. A computer may assign a risk to an object which has an object estimation-value. The computer may also receive a risk estimation-value for the risk. The computer may re-calculate the object estimation-value based on the risk estimation-value.

Abstract: A method and corresponding equipment for emulation of a target programmable unit, which has at least one CPU, by means of an external emulation device, which is coupled to the target programmable unit by means of a communication link, comprising: transferring predetermined initialization data through the communication link to the emulation device for initializing the emulation; transferring through the communication link to the emulation device a CPU clock signal and emulation data; emulating the target programmable unit in the external emulation device using the transferred emulation data; ascertaining respective trace data from the emulation in the external emulation device and storing and/or outputting the trace data; deriving respective target integrity-control data and emulation integrity-control data from respective target-internal data and emulation-internal data; and transferring the derived target integrity-control data from the target programmable unit to the external emulation device.

Abstract: A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first data in synchronization with a second clock signal with a period longer than that of a first clock signal. The circuit verifying method includes detecting a change of the input data in synchronization with the first clock signal; outputting a data indicating a meta stable state during a period longer than one period of the first clock signal based on the change of the input data as the first data; storing the changed input data in a storage unit based on the change of the input data; and outputting the changed input data which has been stored in the storage unit as the first data after stop the output of the data indicating the meta stable state.

Abstract: A method of transactional simulation of a generic communication node model is proposed. The method includes steps, performed at each simulation step corresponding to transaction start events and transaction end events, including: calculating a remaining quantity of data to be transmitted for each transaction not completed in a list of current transactions; if the simulation step corresponds to the start of a new transaction, calculating a quantity of data to be transmitted for the new transaction and adding the new transaction to the list of current transaction; if the simulation step corresponds to the end of the transaction, removing the transaction from the list of current transactions; allocating throughputs to the current transactions, according to a predetermined node sharing policy; calculating a duration up to the closest end time of one of the current transactions; and assigning a wait for the duration before generation of the next transaction end event.

Abstract: A systems power distribution tool integrates the design of the power source and distribution network to provide a robust interconnect topology and power source. This is accomplished with a machine of one or more computing devices configured as a systems power distribution tool. The tool “pulls” load current from the source through interconnects to the loads. This allows the interconnects to be designed to satisfy derating conditions for worst case voltage and current conditions and the power source to be designed to source the loads under actual conditions without margin stacking.

Abstract: Based on common weather conditions, novel methods are disclosed for the prediction of electrical power distribution interruptions and for interruption risk assessment based on immediate weather conditions. Daily, hourly, and bi-hourly weather data are used to predict the number of interruptions and to normalize reliability indices for weather. Common weather conditions include, but are not limited to, rain, wind, temperature, lightning, humidity, barometric pressure, snow, and ice. These conditions do not occur simultaneously at any one place, and the range of combinations is great, therefore the invention allows broad application of the disclosed methods.

Abstract: High-order events may be generated and consumed in a cascading computing model. Low level information, such as changes in physical sensor readings, may be communicated to an application in the form of event messages that are generated by an operating system service. In one example, models that implement high level abstractions may also use events to communicate facts that have been inferred from lower level facts. For example, a program might generate events indicating that a particular type of motion (e.g., walking) has started or stopped, where the program infers the walking motion from sensor data about acceleration and position. Another program could consume those events and other data to draw higher level conclusions, such as “Joe is walking to a meeting”. Thus, events may be used in a cascading model in which events are generated and consumed at increasingly high levels of abstraction.

Abstract: A method and system for controlling an apparatus including receiving data indicative of an actual state of the apparatus, defining a first viewpoint relative to at least one of the environment and the apparatus, determining a first predicted state of the apparatus at time T, determining a first predicted state of the environment at time T, producing a first virtualized view from the first viewpoint, sending a first control signal to the apparatus after producing the first virtualized view, defining a second viewpoint relative to at least one of the apparatus and the environment, determining a second predicted state of the apparatus at time T+delta T, determining a second predicted state of the environment at time T+delta T, producing the second virtualized view from the second viewpoint, sending a second control signal to the apparatus after producing the second virtualized view, and changing the actual state of the apparatus based on the first control signal.

Abstract: The present invention provides an architecture for obtaining an analytical view of data. The invention includes a model service component for receiving an indication of a first object model and generating a dimensional model and a second object model from the first object model. The second object model is analytical in that it preserves relationships identified in the dimensional model, but allows the user to obtain information in terms of objects instead of specifying the data in terms of the dimensional model. The architecture also includes a navigational component that allows a user to navigate from the second object model to underlying data represented by the first object model.

Abstract: A non-transitory, computer-readable recording medium stores therein an analysis support program that causes a computer to execute receiving disposal position information indicative of respective disposal positions for jigs in information indicative of disposal positions set on a surface of an object model modeling an object; creating, using the object model and a jig model modeling a jig, an analytic model by modeling a state where the jigs are disposed respectively at the disposal positions that are on the surface of the object and indicated by the disposal position information; obtaining an analysis result for each of the disposal positions by executing strength analysis of the object using the analytic model; producing, by correlating the disposal positions and the analysis results for the disposal positions based on the obtained analysis results, a chart that displays at each of the disposal positions, a correlated analysis result; and outputting the chart.

Abstract: A computer-implemented method of scheduling a multi-rate, synchronous circuit design for simulation within a high-level modeling system. The method can include determining a component clocking rate for each of a plurality of synchronous components of the circuit design and classifying each of the plurality of synchronous components into a plurality of schedules according to component clocking rate. For each clock cycle during simulation, the method can include selecting one of the plurality of schedules and executing each synchronous component of the selected schedule. A value determined through execution of a synchronous component of the circuit design can be output.

Abstract: The embodiments described herein generally relate to a discrete event simulation (DES) tool which combines the process-driven model and the event-driven model. This integrated process (which uses entities) and event simulation framework according to the various embodiments provides a platform that is appropriate for all combinations of simulation model requirements and at the same time provides higher level of model abstraction. The DES tool instantiates a new paradigm that permits flow of entities at the event-driven model layer that is analogous to their treatment at the process-driven model layer.

Abstract: A method is provided for simulating a complex system including a scheduler hierarchy. The complex system includes at least one processor that executes a set of functions under the control of a hierarchical group of schedulers. The method includes a step of constructing an architectural model of the complex system comprising a hierarchical group of components, each of said components comprising an instance of an object class belonging to the group containing: a first class, known as the Processor class, which represents an abstract model of any processor included in the complex system, a second class, known as the Function class, which represents an abstract model of any function executed by the complex system; and a third class, known as the Scheduler class, which represents an abstract model of any scheduler. Each instance is initialized with at least one attribute that characterizes the behavior desired therefrom.

Abstract: The present invention is directed to automatically analyzing software systems for identifying faults or bugs and/or detection of malicious code. In various embodiments, the present invention measures code coverage for high priority invocable program elements, uses a relaxed coverage estimation technique that, instead of guaranteeing which code units will be executed, guarantees that at least a certain number of code units will be executed, determines and solves constraints in code to identify infeasible paths containing one or more selected nodes, determines, for a composite data type, a range of values for each of at least two non-composite data fields, and/or translates, prior to code analysis complex code into simpler code having fewer operators.

Abstract: A discrete event system (DES) modeling environment models the occurrence of events independent of continuous model time. In a DES modeling environment, state transitions depend not on time, but rather asynchronous discrete incidents known as events. A user may customize selected parameters of a block or other component able to support at least one entity passing therethrough holding a value of arbitrary data type in a DES modeling environment. For example, a user can enable and disable ports a discrete event execution block in a discrete event execution model using a graphical user interface, such as a dialog box. Based on user-selected dialog inputs, a discrete event execution program can automatically update a specification for a block, for example, by adding ports to the graphical representation of the block.

Abstract: The operation of an electronic system comprising a plurality of integrated circuits or other circuit elements is simulated using a software-based development tool that provides a generic framework for simultaneous simulation of multiple circuit elements having potentially different clock speeds, latencies or other characteristics. One or more interfaces provided in the software-based development tool permit registration of processing events associated with one or more of the circuit elements. The software-based development tool is further operative to determine a system clock for a given simulation, and to schedule execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks, so as to maintain consistency in the execution of the processing events relative to the determined system clock.

Abstract: The invention includes a method for predicting a scheduled downtime associated with a system. In one embodiment, a method includes determining a system model associated with the system according to a system type of the system, determining at least one scheduled system downtime event type associated with the system using the system model, selecting at least one scheduled system downtime event model according to the at least one scheduled system downtime event type, and predicting the scheduled system downtime using the at least one scheduled system downtime event model.

Abstract: A system and method for coordinating timing between simulation of a system and measurement and/or control of the system. A measurement/control loop comprising a measurement/control program, a simulation program, and an execution coordination kernel is described. The simulation program may be operable to simulate any of various types of systems. The measurement/control program may provide measurement/control logic for measuring various variables associated with the simulated system. The execution coordination kernel is responsible for coordinating the execution and time advancement of the measurement/control and simulation programs. The execution coordination kernel may be operable to intercept I/O calls produced by the measurement/control program and the simulation program. If the execution coordination kernel determines that the system is in simulation mode, the calls may be routed to software routines instead of to the I/O hardware.

Abstract: A method for detecting a defect in an electric link, which transmits, at a first moment, an electric signal having a predetermined propagation speed from an end of the electric link, and detects, at a second moment, reception of an echo of the electric signal. The method further establishes a model of the variation of the electric signal propagation speed in the electric link on the basis of the length of the link through which the signal flows, and estimates a first location of the defect based on the difference between the first and second moments, on the predetermined propagation speed at the start, and on the speed variation model in the link.

Abstract: A timing-control method of a hardware-simulating program can be applied to a software platform for facilitating control program development. The hardware-simulating program can be recorded in any suitable recording medium and defines therein a plurality of simulating elements which are automatically synchronized at intervals by setting specified time points as aligning points. The specified time points are set with adjustable intervals. By adjusting an interval between adjacent specified time points, the simulating speed between the adjacent specified time points can be changed to comply with practical requirements.

Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.