Abstract: An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated failure site and a non-failure site in the circuit. A detecting unit narrows down an estimated failure site using a fail address. It is determined whether an identifying unit has identified a failure site. If the failure site has not been identified, a delay failure simulation is performed and a comparing unit compares the comparison result of the tester measurement and the result in the delay failure simulation to determine consistency between the results. The identifying unit identifies the failure site based on the consistency.

Abstract: A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

Abstract: There is disclosed systems and processes for optimizing circuit descriptions by reducing clock skew, re-organizing and/or converting gated and generated clock circuits, and reconnecting clock nets and other related nets. A transformed circuit design may be produced from an initial circuit design and having a reduced number of secondary clocks and a reduced amount of clock skew.

Abstract: A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t0, increases to V1 during ?t1; and the one indicating that the voltage increases from V1 to E during ?t2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of ?t1, V1, and ?t2.

Abstract: The method evaluates a constraint of a sequential memory cell able to sample an input data item regulated by a clock signal. The constraint is dependent on the ramp of a first signal and on the ramp of a second signal. The method includes a characterization phase including a first step of determination in which a value of the second ramp is fixed, the value of the first ramp is made to vary so as to determine, a first set of values of the constraint. A second step of determination includes the value of the first ramp being fixed at one of its values taken during the first step of determination, the value of the second ramp is made to vary so as to determine for each value of the second ramp a deviation with respect to the value of the constraint belonging to the first set and corresponding to the fixed value of the first ramp.

Abstract: A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

Abstract: A reduced order model of a distributed time invariant system is produced by projecting system matrices onto smaller matrices, interpolating the matrices and placing into a state-space system. The system matrices are an internal representation of the distributed time invariant system which comprises a description of the system to be modeled, mainly, for example, its inputs and outputs. The method is applied to distributed systems and guarantees accuracy in complicated systems and produces well-behaved models appropriate for use in simulators and simulations.

Abstract: Mechanisms for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic adds delay to one or more clocks of an integrated circuit design to thereby place that clock out of phase with other clocks in the integrated circuit design. In one illustrative embodiment, delay is introduced into a clock net in an increasing manner with each enablement of the clock skewing logic. In another illustrative embodiment, the introduced delay is increased and decreased within a window from no phase shift of the clock net up to a maximum phase shift of the clock net. Once the maximum phase shift is reached, the amount of delay introduced is decreased with subsequent enablement of the clock skewing logic.

Abstract: Systems and methods for designing and generating integrated circuits using a high-level language are described. The high-level language is used to generate performance models, functional models, synthesizable register transfer level code defining the integrated circuit, and verification environments. The high-level language may be used to generate templates for custom computation logical units for specific user-determined functionality. The high-level language and compiler permit optimizations for power savings and custom circuit layout, resulting in integrated circuits with improved performance per watt of power consumption.

Abstract: A digital circuit simulation method. The method starts with a digital circuit design which includes: a first source latch, a destination latch, a logic cone, a first WAM circuit electrically coupling an output of the first source latch to a first input of the logic cone, and a WAGG circuit electrically coupling an output of the logic cone and an input of the first source latch. Then, a zero-delay simulation is performed in which if a first situation of (a) the first WAM circuit entering an uncertainty state in which the first WAM circuit generates a random value of 1 or 0 at the first input of the logic cone, (b) the logic cone being vulnerable to a positive glitch, and (c) the output of the logic cone being at logic 0, the WAGG circuit generates a random value of 0 or 1 at the input of the destination latch.

Abstract: Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common multiple (LCM) clock signal is generated, for example from a clock module. A control signal is generated at least partially responsive to the LCM clock signal and the lock signal. The control signal may be generated from a state machine and applied to select circuitry, where the control signal is used to mask application of the output clock signal responsive to the control signal.

Abstract: A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump file is converted into an RTL dump file indicating how signals of the RTL design behave. A debugger processes the RTL dump file to produce displays depicting the RTL design and behavior of signals indicated by the RTL dump file. Thus while the IC is simulated or emulated at the gate level of the design to produce waveform data for a debugger, the gate level-to-RTL dump file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results. file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results.

Abstract: Systems, methods and media for simulation of integrated hardware and software designs are disclosed. More particularly, hardware and/or software for synchronizing cycle timers of an integrated hardware and software design are disclosed. One embodiment provides a system for simulating an integrated design. Embodiments may include one or more software components each having a single cycle timer and one or more hardware components each having a single cycle timer. Embodiments may also include a cycle synchronizer in communication with the one or more software components and the one or more hardware components that is adapted to call once per cycle the single cycle timers of the one or more software components and the one or more hardware components. In a further embodiment, the cycle synchronizer may be further adapted to call the single cycle timers of the components on the falling edge of the cycle.

Abstract: A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.

Abstract: A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.

Abstract: Methods and systems for automatically reporting delay incurred in a model is disclosed. The delay may be incurred in a part or in an entire portion of the model. Delay incurred in each component of the model is determined and reported to users before executing the model. The delay of each component of the model may be determined based on intrinsic information of the component. If the intrinsic information of the component does not provide information on the delay of the component, the component may be simulated to determine the delay of the components. The model may be automatically compensated for the delay. The delay is reported prior to the execution of the model, and compensated for without executing the model.

Abstract: A method and computer product is provided to generate a signal model for use in analyzing a model system including imposing an explicit time assumption for each time instant of the system model. The time assumptions are defined so that any two assumptions contradict each other, thereby separating all inferences into the respective times. A non-monotonic rule is applied to instantiate component models of the model system. Results are defined as not depending on the existence of a previous time instant and, a simplified signal model is generated, wherein the signal model represents the evolution of a value in the model system over time.

Abstract: Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified.

Abstract: A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in the same hierarchical layer. The method includes matching the tolerance for when a timing error occurs for a cell in each layout block with a worst condition of one of the corresponding cells in the layout blocks, and inserting a timing adjustment cell within a range of the matched tolerance of each cell to adjust the timing error. This method ensures the correction of hold errors and setup errors in an integrated circuit designed with a hierarchical design technique.

Abstract: A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from multiple stimulation results. Each of these extracted building block events or “tags” are created from a slice of a graphical stimulation view, which slice is converted into a coded stimulus written in a high-level language code that represents the condition(s) that created the graphical simulation view. These coded stimuli (representing the tags) are stored in a library. To create a corner case scenario or sequence in the DUT, a user utilizes a graphical interface to select the different extracted tags from the library and combines them together.

Abstract: A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy and generating a local timing constraint specific to the physical portion. The method also can include creating a software representation of the physical portion of the IC. The software representation can specify the local timing constraint and a shell netlist for the physical portion. The method further can include performing a timing analysis upon, at least part of, the circuit design using the software representation.

Abstract: A method and a device determine a time response of a digital circuit. The time response is determined as a time difference between a data delay of a data path of the digital circuit, and a clock delay of a clock signal, which causes storage of a data item on the data path, taking into account a check. The check is determined dependent on a data slew of a signal on the data path and a clock slew of the clock signal in such a way that a positive time difference ensures the correct saving of the data item.

Abstract: A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of each other. The independent clock domains are grouped together, within said chip design, to form clock domain groups. A timing analysis is performed on the design of the chip by clocking the clock domain groups each with an independent scan test clock. The scan test clocks originate externally to the design and by-pass, within the chip design, the corresponding internal clocks. Capture mode violations are recorded from the timing analysis and are used to go back and form new clock domain groups, thereby repeating the method until no capture mode violations are generated.

Abstract: A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data.

Abstract: A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and computing a difference between the maximum clock path delay and the minimum clock path delay for a destination register of the circuit design. The method further can include adjusting a register timing parameter for the destination register according to the difference and performing a timing verification on the destination register using the adjusted register timing parameter.

Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock.

Abstract: A system and method of verifying the format of a simulated signal produced during the simulation of an electronic circuit is disclosed. One aspect of the present invention includes a method of extracting timing information from a single simulated serial digital audio signal that comprises both data and clock. An embodiment of the present invention may verify operation of the simulated electronic circuit by setting the value of a first simulated signal according to predetermined events that occur in a second simulated signal. The second simulated signal may be parsed using timing information extracted from the second simulated signal, and the format of the second simulated signal may be matched against a predetermined format based upon the results of the parsing.

Abstract: A transient simulation system, methods and program product that implement an adaptive piecewise constant (PWC) model are disclosed. The invention evaluates an error criteria to determine a maximum allowable change in one of a current and a voltage; and simulates the transient conditions by implementing an adaptive step in the PWC model according to the maximum allowable change. The invention allows dynamic or static adaptation of a PWC model according to an error criteria.

Abstract: Systems and methods for implementing voltage supply noise analysis for electronic circuits are disclosed. In an exemplary embodiment a computer program product executes a computer process. The computer process generates at least one spatial profile for the electronic circuit, generates at least one temporal profile for the electronic circuit, merges the at least one temporal profile and the at least one spatial profile, and determines if the electronic circuit is operating within acceptable voltage noise margins based on the merged temporal and spatial profiles.

Abstract: A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded.

Abstract: A design-change-target-circuit detecting unit inputs circuit information including an element model describing an electronic circuit to detect an electronic circuit using a changed element model. A determining unit compares a characteristic of an element model before change and that of the element model after change. An analysis-necessity deciding unit decides whether waveform analysis is necessary, and when determining that waveform analysis is necessary, makes an instruction for waveform analysis of the electronic circuit using the element model after change.

Abstract: A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when performing circuit analysis by partitioning a circuit into blocks, the SPICE deck generating section generates a SPICE deck by interconnecting the blocks, for a path that needs analysis, by using a result of static timing analysis and using simulation conditions for the each block. The feedback-based static timing analyzing section causes a result of the simulation performed using the generated SPICE deck to be reflected in the static timing analysis.

Abstract: Provided is a black box timing modeling method for a digital circuit comprising synchronous elements including latches. The method includes: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous element with respect to an input connected to the synchronous element and forming the setup time arc using the extracted setup time; and characterizing a clock-to-output delay arc by providing information on an output departure time from an output based on a rising or falling edge of a clock of a closest synchronous element connected to the output, at least partially based on the setup time arc and forming the clock-to-output delay arc. Accordingly, the method can be efficiently used for a latch-based design without re-verifying internal components of the latch-based design during an upper-level verification, thereby reducing verification time and model size.

Abstract: A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.

Abstract: Method and apparatus for timing modeling is described. More particularly, wire information, including wire lengths, is obtained from a routing output. Signals associated with such wire information are classified as input or output signals from an embedded core. Respective templates are automatically selected for the input signals and the output signals, respectively, at least in partial response to the wire lengths. Furthermore, timing information for the embedded core is obtained and classified according to condition, and the input signals and the output signals from the embedded core are determined to obtain rise and fall timing information for such signals.

Abstract: A method and an apparatus to perform logic synthesis preserving high-level specification and to check that a common specification (CS) of two circuits is correct have been disclosed. In one embodiment, the method includes building a circuit N2 that preserves a predefined specification of a circuit N1. In some embodiments, the method includes verifying that N2 and N1 indeed implement the same specification and so they are functionally equivalent.

Abstract: A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality of instances to a selected software construct. Each of the plurality of instances can be from a different logic hierarchy. The method further can include automatically adding at least one input/output buffer and port to the selected software construct to accommodate the plurality of instances and creating nets connecting the plurality of instances and the at least one input/output buffer and port within the selected software construct.

Abstract: The present invention provides an electronic circuit analyzing apparatus for evaluating the reliability value of an analysis result, an electronic circuit analyzing method, and an electronic circuit analyzing program. The electronic circuit analyzing apparatus comprises an input information storage unit 1 that stores input information, an analytic model creation unit 12 that creates an analytic model of an electronic circuit on the basis of the input information, an analysis unit 3 that calculates an analysis result of the electronic circuit using the analytic model, a partial model reliability value database 21 that defines the accuracy of each part of the analytic model and stores the accuracy value as a partial model reliability value, a partial model influence database 22 that defines the magnitude of influence of each part of the analytic model and stores the influence value as a partial model influence, a reliability value evaluation unit 23 that calculates an analysis result reliability value, i.e.

Abstract: Systems and methods for designing and generating integrated circuits using a high-level language are described. The high-level language is used to generate performance models, functional models, synthesizable register transfer level code defining the integrated circuit, and verification environments. The high-level language may be used to generate templates for custom computation logical units for specific user-determined functionality. The high-level language and compiler permit optimizations for power savings and custom circuit layout, resulting in integrated circuits with improved performance per watt of power consumption.

Abstract: A method of delay change determination in an integrated circuit design including a stage with a victim net and one or more aggressor nets capacitively coupled thereto, the method comprising: determining a nominal (noiseless) victim net signal transition; determining a noisy victim net signal transition; and determining a delay change based upon nominal and noisy victim signal transition arrival times at a victim net receiver output.

Abstract: Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be associated with input ports, output ports, internal pins, or hierarchical pins and can even span multiple blocks. This disclosed approach allows for application of assertions associated with timing models when the model is instantiated and detachment of assertions when the model is de-instantiated, and thus removes one of main problems associated with timing models.

Abstract: A system and method for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic adds delay to one or more clocks of an integrated circuit design to thereby place that clock out of phase with other clocks in the integrated circuit design. In one illustrative embodiment, delay is introduced into a clock net in an increasing manner with each enablement of the clock skewing logic. In another illustrative embodiment, the introduced delay is increased and decreased within a window from no phase shift of the clock net up to a maximum phase shift of the clock net. Once the maximum phase shift is reached, the amount of delay introduced is decreased with subsequent enablement of the clock skewing logic.

Abstract: To perform a simulation, a design can be divided into “blocks” described by models. To ensure that data is efficiently transferred from an source model to a destination model, a dynamic first-in first-out (FIFO) can be placed between these models. The initial size of the dynamic FIFO can be set to a relatively small value. To prevent deadlock, the size of the FIFO can be automatically increased in size by increments. In this manner, the memory resources of the FIFO can be tightly controlled. Advantageously, the size of the optimized dynamic FIFO can be used as the desired size of the FIFO implemented in silicon, thereby also ensuring efficient use of silicon resources.

Abstract: Various approaches for controlling simulation of an electronic system are disclosed. In one approach, at least one breakpoint block is instantiated in a high-level design. The breakpoint block has an associated breakpoint condition driven by at least one signal of the design, and the design further includes at least one simulation block and at least one co-simulation block. The simulation block is simulated on a software-based simulation platform, and the co-simulation block and the breakpoint block are co-simulated on a hardware-based co-simulation platform. Advancement of a clock signal to the co-simulation block on the hardware-based co-simulation platform is inhibited in response to satisfaction of the breakpoint condition. After inhibiting the clock signal, advancement of steps of the clock signal is controlled on the co-simulation platform in one of a plurality of user-selectable clock advancement modes.

Abstract: Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least some others of the latches are enabled by the other phase of the clock signal. Accordingly, these latches collectively have two-phase operation. These two-phase latches may replace at least some single-phase, edge-triggered flip-flops in a user's logic design, and may thereby increase the speed at which the user's logic can be operated. Methods for converting a single-phase, edge-triggered flip-flop design to a logically equivalent design using at least some two-phase latches are disclosed.

Abstract: There is provided a set of methods for generating state space models of general VLSI interconnect and transmission lines, trees and nets by closed forms with exact accuracy and low computation complexity. The state space model is built by three types of models: the branch model, the connection model and the non-connection model, that are block matrices in closed forms, arranged with topology. The main features are the topology structure, simplicity and accuracy of the closed forms of the state space models {A,B,C,D} or {A,B,C}, computation complexity of O(N) in sense of scalar multiplication times, where N is the total system order, practice of the modeling, ELO model simplification, and their optimization. For evenly distributed interconnect and transmission lines, trees and nets, the closed forms of state space model have the computation complexity of O(1), i.e., only a fixed constant of scalar multiplication times.

Abstract: A method to obtain configuration data for a data processing apparatus by calculating (110) a time interval between the commencement of a mode (104) and a subsequent event (108). The calculated time interval is then compared (112) with one or more reference values (114). The result of the comparison is used to derive configuration data (116). The method may be further refined by including a calibration stage to reduce the error in the calculated time interval, thereby allowing comparison with a larger set of reference values (114), which in turn permits more configuration data to be derived from the calculated time interval.

Abstract: A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment in which the electronic device is to be tested. A virtual calibration of the virtual test environment may be performed, to more closely emulate the actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal that is applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated.

Abstract: A system and method for optimizing placement of network equipment and information load in a network over a period of time. A demand input structure having a plurality of demands organized by their time points is provided as an input to a model generator and an optimization processor associated therewith. Starting with the earliest demand set to be serviced by the network, a directed graph network model is obtained by using appropriate transformation techniques. A cost function associated with the network model is constructed using a flow cost term and an equipment cost term. Appropriate constraints are imposed on the cost function for optimization. A solution set comprising network placement information and demand routing information is obtained for a current time point. When the next demand set is taken up for optimization, the network model and associated cost function are recursively updated by using the solution set obtained for the demand set at a prior time point.