Abstract: A trusted computer system that offers Linux® compatibility and supports contemporary hardware speeds. It is designed to require no porting of common applications which run on Linux, to be easy to develop for, and to allow the use of a wide variety of modern development tools. The system is further designed to meet or exceed the Common Criteria EAL-5 or higher rating through incorporation of required security features, as well as a very high level of assurance for handling data at a wide range of sensitivity (e.g., classification) levels in a wide range of operational environments. This is achieved through the implementation of a well-layered operating system which has been designed from the ground up to enforce security, but which also supports Linux operating system functions and methods.

Abstract: A simulation system is provided for simulating operation of a plurality of hardware devices in combination with an instruction set simulator simulating execution of program instructions by a program core. A test scenario manager acts as a master and serves to command the hardware devices and the instruction set simulator with stimulus signals to simulate various specified activity.

Abstract: A combined in-circuit emulation system and device programmer. A pod assembly used in an in-circuit emulation system has both a real microcontroller used in the In-Circuit Emulation and debugging process as well as a socket that accommodates a microcontroller to be programmed (a program microcontroller). Programming can be carried out over a single interface that is shared between the microcontroller and the program microcontroller and which is also used to provide communication between the real microcontroller and the In-Circuit Emulation system to carry out emulation functions. In order to assure that the emulation microcontroller does not interfere with the programming process for a microcontroller placed in a programming socket, a special sleep mode is implemented in the emulation microcontroller. This sleep mode is activated by a process that takes place at power on in which the a reset line is released with a specified data line held in a logic high state.

Abstract: In the calculation or simulation of technical components for use in a technical system wherein calculation programs are provided for various physical variables which are taken into account on a case-to-case basis, a preprocessing method is provided in order to couple programs for physically and geometrically calculating such a component without the need for the creation of a tailor-made calculation program for a specific component. The procedural setup of the processing steps permits a modular composition of the calculation process for the simulation of any type of component subjected to physical influences.

Abstract: A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.

Abstract: A bus simulation apparatus for simulating a bus connecting a plurality of devices. Each of a plurality of simulated bus slot application interfaces prepares a receive task in response to a call from a simulated device corresponding to each of the plurality of the devices. The receive task obtains a communication handle for an application name of the simulated device. A communication handle management table relates the communication handle to the application name. A simulated bus manager, in response to a request for data transfer between the simulated devices along with the application name, sends data to the receive task of destination using the communication handle obtained by searching the communication handle management table based on the received application name.

Abstract: A method is disclosed for modeling and processing an asynchronous functional specification to provide an input to an architecture synthesis engine. The method includes the step of generating an initial task graph from the specification, the task graph having a number of executable tasks. Selected data and control connections are established between respective tasks in accordance with a specified set of rules to define some of the tasks to be deterministic, and other of the tasks to be non-deterministic. Each of the control connections is then marked, to provide an annotated task graph for use as an input to the architecture synthesis engine, the annotated task graph enabling the engine to employ specified scheduling techniques.

Abstract: Circuit synthesis is performed utilizing an optimizer that selects design parameters for a synthesis model of a circuit based on desired performance characteristics and performance characteristics/design parameters of previously synthesized circuits. Performance characteristics and design parameters of each synthesized circuit are maintain in conjunction with the synthesis model of the circuit being synthesized. A synthesis plan identifies the synthesis model and specific instructions on how to perform optimized selection of design parameters, how to set up test benches, and how to perform the simulation.

Abstract: If it becomes necessary to add, to a past device information list (past list), a record of device information of a target removed from a network, and if the number of records in the past list is already at its maximum so that it is impossible to store any more records in the past list, a microprocessor of a controller decides the priority of the removed target, based on device information of the removed target and on information of the kind of controller as stored in a configuration ROM in the controller. From records stored in the past list, the microprocessor searches for a record having a priority lower than the priority of the removed target, one by one in order from the first record therein. If the microprocessor finds a record having such a lower priority, the microprocessor deletes from the past list such record having been first found, and adds to the past list a record of the device information regarding the removed target.

Abstract: A system and method for simulating a networked system for testing of embedded software on an emulated hardware device. The system provides for automated generation of a simulated hardware and facilitates testing of embedded software response to simulated error conditions created by the simulated hardware. Communications from the embedded software are intercepted at a low software level and redirected from the emulated hardware device to the simulated hardware.

Abstract: A system and method for testing a parameterizable logic core are provided in various embodiments. A test controller is configured and arranged to generate a set of random parameter values for the logic core. A netlist is created from the parameterized logic core, and circuit behavior is simulated using the netlist. In other embodiments, selected parameter values are optionally weighted to increase the probability of generating those values, and the parameter set is cloned and mutated when simulation fails.

Abstract: Applications software can be rapidly tested and developed for a multi-processor chip even though the hardware of new processors of the multi-processor chip is not yet available. This can be accomplished by executing software simulations of the new processor designs and corresponding applications software either on a previously designed processor that is hardware on the multi-processor chip or on a workstation development platform. The execution of the previously designed processor is typically much faster than the execution on a simulator running on a personal workstation development platform, and therefore the execution time is quicker. Furthermore, the processor simulation and application software can be configured to take advantage of the platform most appropriate for execution and avoid simulation of portions of the new processors that are not necessary for testing the applications software.

Abstract: An initial condition (IC) behavior module is described for use in a hardware definition language simulation system which operates in two phases. In the first phase, the IC module sets an initial logic condition onto a user-selected node which is to be monitored. The IC module will release the initial condition and then test the node value to determine if the simulation system is able to resolve the node. Alternatively, the IC module may release the node if a user-defined IC time period passes. In the second phase, the IC module monitors the node and reports an error message if the simulated node value becomes unacceptable.

Abstract: The present invention is an apparatus for multi-level loopback test in a community network system and method therefor, in which a loopback test device is installed between an Ethernet switch in a community and a central office so that the loopback test device can be utilized by network management system in central office to perform a three-level loopback test on the community network system to easily obtain the information of whether there is a fault between central office and loopback test device, whether the connection of Ethernet switch is good, and whether loopback test device operates normally.

Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.

Abstract: An apparatus for verifying the functionality of a production line electronics safety tester such as the hipot tester/ground continuity tester. The apparatus simulates a product to be tested by a safety tester and can be configured to simulate a passing or failing product for each of a plurality of separate tests.

Abstract: A system design support system is disclosed, which handles specifications at system level, e.g., a specification of software executed by a computer, specification of hardware implemented by combining semiconductor devices and the like, a specification of an incorporated system implemented by combining software and hardware, and a specification of a business process such as a workflow. This apparatus searches for an advertisement in accordance with an query specification. The apparatus also creates a communication procedure between the query specification and a specification of an advertisement part obtained by a search.

Abstract: A method and system for categorizing non-textual subject data, such as digital images, content-based data and meta-data to determine outcomes of classification tasks. The meta-data is indicative of the operational conditions of a recording device during the capturing of the content-based data. For example, the non-textual subject data may be a digital image captured by a digital camera, and the meta-data may include automatic gain setting, film speed, shutter speed, aperture/lens index, focusing distance, date and time, and flash/no flash operation. The subject image is tagged with selected classifiers by subjecting the image to a series of classification tasks utilizing both content-based data and meta data to determine classifiers associated with the subject image.

Abstract: A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wide area network (wherein the host site contains the core logic and the customer site contains customer logic, the core logic and the customer logic forming the circuit), comparing test output signals with the desired output signals, and altering the customer logic until the test output signals are consistent with the desired output signals.

Abstract: A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.

Abstract: A method and system for constructing a structural model of a memory for use in ATPG (Automatic Test Pattern Generation). According to an embodiment of the present invention, behavioral models of memories of the simulation libraries are re-coded into simplified behavioral models using behavioral hardware description language (e.g., Verilog). Then, the simplified behavioral models are automatically converted into structural models that include ATPG memory primitives. The structural models are then stored for subsequent access during pattern generation. In one embodiment, for modeling random access memories (RAMs), the ATPG memory primitives include memory primitives, data bus primitives, address bus primitives, read-port primitives and macro output primitives. In another embodiment, for modeling content addressable memories (CAMs), the ATPG memory primitives include memory primitives, compare port primitives and macro output primitives.

Abstract: A universal programmable remote control device has programmability functions that enable the end-user to customize the device through editing or programming the device's control functionalities. The programming can be achieved via a PC. The control configuration created via an editor on the PC can be downloaded into the device. The PC has emulator software to test the configuration before downloading. The emulator software and the remote's control software are made identical as a consequence of a software layer that abstracts from the remote's hardware. The emulator for the end-user is thus obtained as an almost free byproduct of the software development phase at the manufacturer.

Abstract: A method of and apparatus for determining whether a multi-component target system meets a given multi-part performability requirement is provided. A description of the target system, failure probabilities for components of the target system and a multi-part performability requirement for the target system are obtained. The multi-part performability requirement indicates desired performance levels and corresponding fractions of time. One or more failure-scenarios are successively computed that represent one or more states of the target system having zero or more components failed and a corresponding probability of occurrence of the one or more of the states of the target system. Performance of the target system is modeled under the failure scenarios using a performance predictor module for generating a multi-part performability function.

Abstract: An element for carrying out and documenting a program or test sequence allows specific functions to be carried out. The element has at least one control input to which an external control signal can be supplied, and a variable can be varied in the element as a function of the external control signal. The process of carrying out a particular function can be varied by the element in such a manner that, when the variable has a specific value (“0”) and the external control signal is at a first signal level, the variable assumes a value (not equal to “0”) which differs from the specific value; and when the variable is at that specific value and an external control signal which is at the first signal level is once again applied, the variable remains at that specific value.

Abstract: A method is provided to facilitate configuration of one of a plurality of different products from a set of components (TABLE 2) which can be selectively combined in different ways to form a plurality of different component combinations that each serve as a respective one of the products. An inventory list is prepared (191, TABLE 2), and then a component information package is prepared (192, TABLE 3). A determination is then made (193, TABLE 4) as to whether each component in the inventory list corresponds to one or more of first, second and third component classes (TABLE 1) that are different. One or more criteria sets (196) are then developed to define a plurality of criteria states which each correspond to a valid combination of components from the second and/or third classes that represents a respective product. Then, a flowchart is prepared (197, FIG. 8) to diagrammatically represent the criteria set and the combinations of components which correspond to the respective states of the criteria set.

Abstract: A computer system for simulating an ASP comprises first processor means including execution means for simulating a functional model in a high level language and output means for outputting the state of the functional model at the end of a predetermined simulation phase, means for converting the functional model, including its state at the end of the predetermined simulation phase, into a simulation language for simulating the ASP at circuit level, and second processor means arranged to execute the simulation language to simulate the ASP at circuit level for a subsequent simulation phase.

Abstract: A system and method for analyzing the effectiveness of a computer cache memory. A bus with memory transactions is monitored. A subset of addresses, along with associated transaction data, on the bus is captured and stored in a memory. The captured addresses are applied to a software model of a computer cache. The capture process is repeated multiple times, each time with a different subset of the address space. Statistical estimates of hit rate and other parameters of interest are computed based on the software model. Multiple cache configurations may be modeled for comparison of performance. Alternatively, a subset of addresses along with associated transaction data is sent to a hardware model of a cache. The contents of the hardware model are periodically dumped to memory or statistical data may be computed and placed in the memory. Statistical estimates of hit rate and other parameters of interest are computed based on the contents of the memory.

Abstract: The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a network identify a new message flow, they determine the proper processing for packets in that message flow and cache that information for that message flow. Thereafter, when routers in a network identify a packet which is part of that message flow, they process that packet according to the proper processing for packets in that message flow. The proper processing may include a determination of a destination port for routing those packets and a determination of whether access control permits routing those packets to their indicated destination.

Abstract: A system and method of verifying an electronic system. A verification kernel is provided and the electronic system is expressed as a logic design. A wrapper is defined, wherein the wrapper is an interface between the logic design and the verification kernel. Tests to be run against the logic design are placed within a diagnostic program and an interface between the diagnostic program and the verification kernel is defined. The tests are then executed against the logic design. The results of the tests are captured and validated against expected results.

Abstract: A method for the automatic design of processor datapaths operates on an abstract input specification of desired processor operations and their instruction level parallelism and synthesizes a datapath design in machine readable form. A datapath synthesizer automatically designs and synthesizes the processor datapath including the number and types of functional units, the number of read/write ports of the various register files, and the exact connectivity between the register files and the functional units. The heuristics used in the implementation maximize resource sharing and minimize the overall cost in by customizing and sharing functional units and minimizing the number of read/write ports on the register files subject to the specified ILP among operations.

Abstract: A system for detecting/avoiding memory usage conflicts when generating and merging multi-threaded software test cases. Initially, a test case generator is given a unique segment of memory which it can use. A plurality of test cases are generated, one at a time, by the test case generator. When the first test case is generated, the memory segment used is noted. When each of the second through Nth test cases is generated, a memory segment of the same size as the first test case, but not overlapping that of the previously assigned test case(s), is assigned to each subsequent test case.

Abstract: An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path.

Abstract: Haptic rendering of three-dimensional soft bodied objects for virtual interactions implemented by forming a three dimensional occupancy map of voxels, forming the surface of and bounding an object, forming a multi-dimensional coordinate system, defining minimum and maximums distances of one voxel neighboring voxels defining multi-dimensional maximum offsets that an occupied point can maintain relative to its center, detecting when the minimums or maximums of distance and/or offsets are violated, and in response thereto adjusting to satisfy minimum and maximum for distance and offsets, and repeating the detecting and adjustment steps for the entire occupancy map until there are essentially no violations.

Abstract: This invention discloses a method and system to search for a critical path which allows a quick and reliable search for a critical path by using an actual semiconductor device. When the number of the operating clock pulses between the input of a predetermined data to a semiconductor device and the output of the corresponding data is n pulses, each period of the n pulses is changed from a failing period T1 to a passing period T2 in order to search for a critical path.

Abstract: A method is provided for quantifying circuit design complexity. Conclusions regarding the time and effort to implement a circuit design are thereby derived and historical and predictive analyses prepared. Common circuit design parameters are determined using a computer-implemented Normalization Method. In the Normalization Method, the effort required to implement circuitry is quantified by evaluating each one of a set of complexity factors. The total transistor count of a circuit is then adjusted according to these complexity factors to produce a “normalized transistor” count. Design characteristics or factors that influence complexity are identified from among raw data in a database of integrated circuit design project data. These factors are then incorporated into a Normalization Equation such that normalized transistor count is a statistically significant predictor of required design project effort.

Abstract: An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.

Abstract: A data collection system for transmitting data from user equipment to a user application server over a GSM network is provided. According to an aspect of the invention, a data terminal apparatus is configured to simulate a circuit switched call link to the user equipment, while providing a communications call link to the GSM network over a non-circuit switched call link. According to embodiments described herein, the non-circuit switched call link is achieved via packetizing serial data from the user equipment into short message service messages, or alternatively via general packet radio service messages. As a result of the methods and apparatuses of the present inventions, legacy serial communications equipment can be integrated into a data collection network and remotely monitored without the costs associated with deploying service personnel or more costly circuit switched type equipment and services.

Abstract: Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of gate and drain voltages is performed. Drain currents are measured in this two dimensional region and are used to create a piecewise, linear IV model of device. The process is repeated for the highest body voltage. This process differs significantly from prior art bulk device characterization techniques, which did not have to initialize body voltage or perform a transient analysis. The body voltage is modulating during the switching event due to the gate-to-body and diffusion-to-body coupling; and thus only a transient analysis can properly model these coupling effects.

Abstract: A method for efficiently simulating memory structures of a sequential circuit for design verification of the sequential circuit. The method is implemented by an computer system having a processor coupled to a memory via a bus, the memory storing computer readable code which when executed by the processor cause the computer system to perform the steps of the memory structure simulation method. The method includes accessing a netlist description of a sequential circuit, wherein the description is for realizing the sequential circuit in a physical form. Memory elements included within the description are identified. For these memory elements, inputs to the memory elements and outputs from the memory elements are identified. Using this information, the memory elements are grouped into at least one group of functionally related memory elements. Subsequently, the memory elements of the one or more groups are collectively addressed as a group.

Abstract: An apparatus enables development and debugging of a control program for controlling a relatively small product having rapid response without using an actual mechanism. A simulation unit simulates an operation of a mechanism, in a simulation cycle shorter than a control cycle, for a time corresponding to the control cycle, and outputs a state variable of the mechanism to a holding circuit. When the state variable is held in the holding circuit, a simulation control unit makes the simulation unit shift to a response waiting state and makes a control program executing unit calculate a controlled variable. When the controlled variable is held in the holding circuit, the simulation control unit makes the control program execution unit shift to a response waiting state and makes the simulation unit initiate a simulating operation. The apparatus is applied when a control program for every product requiring a precise servo control is developed.

Abstract: Subject matter includes an exemplary flexible network simulator and related methods for testing the ability of electronic devices to communicate with each other on a network, especially in real-time. The exemplary flexible network simulator can establish different connectivity protocols between multiple electronic devices and test the electronic devices using customized sets of network conditions.

Abstract: A technique for determining performance characteristics of electronic systems is disclosed. In one exemplary embodiment, the technique may be realized as a method for determining performance characteristics of electronic systems. The method includes the steps of measuring a first response on a transmission medium from a falling edge transmitted on the transmission medium, and measuring a second response on the transmission medium from a rising edge transmitted on the transmission medium. The method also includes the step of determining worst case bit patterns for transmission on the transmission medium based upon the first response and the second response.

Abstract: Classes of cognition models which may include: 1) Radio Environment models, 2) Mobility models and 3) Application/User Context models are utilized in a wireless communications network. Radio Environment models represent the physical aspects of the radio environment, such as shadowing losses, multi-path propagation, interference and noise levels, etc. Mobility models represent users motion, in terms of geo-coordinates and/or logical identifiers, such as street names etc. as well as speed of user terminal etc. The context model represents the present state and dynamics of each of these application processes within itself and between multiple application processes. These data are employed to optimize network performance.

Abstract: A storage medium is disclosed. The storage medium having stored on it a set of programming instructions defining a number of data objects and operations on the data objects for use by another set of programming instructions to enable the other set of programming instructions to be compilable into either a version suitable for use in a hardware/software co-simulation that effectively includes calls to hardware simulation functions that operate to generate bus cycles for a hardware simulator, or another version without the effective calls, but explicitly expressed instead, suitable for use on a targeted hardware.

Abstract: An interactive computer-based training (ICBT) system operable over a computer network for training users. The ICBT system is provided with inter-dependent, state-machine-based hardware and software simulators for emulating hardware and software functionality associated with a piece of equipment on which the users are to receive interactive training. The state transition method effectuated in a computer-readable memory system includes the steps of: identifying a current state of the state machine wherein a transition is to be effectuated; determining if there is a state immediately prior to the current state, and if so, determining whether there is a dependency of the current state on the immediately prior state, the dependency being characterized as a first order dependency; inferring a reference value associated with the current state based on the first order dependency; and determining a future state of the state machine based on the inferred reference value.

Abstract: A hardware abstraction layer operates as a system architectural layer between a real-time operating system and an underlying configurable processor. The hardware abstraction layer provides an abstraction of processor-specific functionality to the operating system. In particular, it abstracts configurable processor features visible to the operating system to provide a uniform, standardized interface between the operating system and the configurable processor on which it runs. Thus, an operating system running on top of the hardware abstraction layer will work on all configurations of the processor which differ from one another only in the configuration parameters covered by the hardware abstraction layer. The hardware abstraction layer may be generated using the same information that is used to describe the features being configured in the configurable processor.

Abstract: First characteristic values (SS, FF) which fluctuate most of the characteristic of a device composing a semiconductor device are obtained according to a fluctuation of manufacturing process for the semiconductor device. Next, the width (optimized K value) of a fluctuation width of manufacturing process which matches second characteristic values (C1, C16) of the worst cases of the characteristic of this device with the first characteristic values (SS, FF) is determined. Finally, a third characteristic value of the worst case of the circuit characteristic of the semiconductor device is determined based on this fluctuation width (optimized K value).

Abstract: A co-simulation design system to simulate on a host an electronic system that includes target digital circuitry and a target processor with an accompanying user program. The system includes a processor simulator to simulate execution of the user program by executing host software that includes an analyzed version of the user program. The system further includes a hardware simulator to simulate the target digital circuitry and an interface mechanism that couples the hardware simulator with the processor simulator. The user program is provided in binary form. Determining the analyzed version of the user program includes decomposing the user program into linear blocks, translating each linear block of the user program into host code that simulate the operations of the linear block, storing the host code of each linear block in a host code buffer for the linear block, and adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program.

Abstract: A method for modeling digital signal processors (DSP) in a C++ environment is disclosed. In particular, the method models and converts an operation (or function) from a floating-point model to a given DSP fixed-point processor model. The invention defines a vector space for each DSP fixed-point processor, as a direct sum of each distinct fixed bit length data representation sub-space. The direct sum of all DSP fixed-point processor vector sub-spaces forms a working vector space. Furthermore, the invention defines an operator projection to be performed on the working vector space such that redundancy in the operational behavior of the DSP's to be modeled may be exploited. In the preferred embodiment, the working vector space is in a C++ environment. A C++ class is defined for each distinct fixed bit length data representation of a given DSP fixed-point processor.

Abstract: A method and apparatus of analyzing a target system comprises receiving information relating to an environment of the target system and storing cost data based on the environment information. The plan and its estimated performance for a query may be determined based on the cost data. The environment information may pertain to the environment of a parallel system (e.g., a multi-node parallel system, a single-node parallel system having plural central processing units or a system running plural virtual processors) that is running a parallel database. The cost data may identify a number of nodes in the target system, a number of central processing units in each node of the target system, and other types of system information. The cost data may be stored in a relational table having a plurality of rows. Each row of the relational table may correspond to a different target system.