Abstract: A debugging environment for a multi-processor simulator or emulator is disclosed. The simulator or emulator is ideally suited for the development of embedded software. The simulator can contain multiple processor models, with each processor model representing a processor. The simulator or emulator also includes a scheduler which controls the execution of the processor models. Each processor also communicates with a debugger via a debug adapter. The debug adapter acts as a pass-through filter for non-control commands which are communicated between a processor and its attached debugger. However, the debug adapter routes control commands to the scheduler. The scheduler ensures that all of the processors and debuggers maintain synchronization. Other modules can also be included in the multi-processor simulation environment, for example, clock gate modules.

Abstract: A modelling tool for use in defining an ASP which receives as its input an input file which for each of a set of peripherals defines the functional attributes of that peripheral in a high level language with an input data structure and which generates from the input file, (i) an interface functions file, which defines the communication attributes of the peripheral with the processor and the functional attributes of the peripheral in a manner independent of any particular data structure, (ii) a test functions file which defines the communication attributes of the processor with the peripheral in a manner independent of any particular data structure, and (iii) a register definition file by allocating specific elements of the input data structure to predefined sectors of a register definition table.

Abstract: A spacecraft emulation system that can emulate both the attitude control subsystem and the non-attitude control subsystem is integrated into a single compact unit. The unit includes an emulated spacecraft control processor for processing attitude control information and an emulated central command and telemetry unit for interfacing simulated spacecraft data. The inlet also includes a first simulation engine that is operative to simulate the spacecraft attitude control system and a second simulation engine that is operative to simulate the spacecraft power, thermal, propulsion and payload subsystems. Both the first and second simulation engines are connected to the emulated spacecraft control processor via a respective bus. A host computer provides the command data and receives the telemetry data from the emulated spacecraft control processor.

Abstract: A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].

Abstract: Integrated circuit models having associated timing and tag information therewith for use with electronic design automation to effectively model timing exception information. The present invention includes a circuit block model which allows automated circuit optimization to be performed on extremely large circuits without the need to load all of the details of the circuit into computer memory. The circuit models of the present invention effectively model timing including timing exception information. The model of the present invention is associated with command information, e.g., textual commands, that describe tags (which model exceptions) and arrival and required times associated with the tags. Specifically, for the input pins of a circuit to be modeled, the present invention writes out a command defining each unique required tag associated with an input pin and also writes out commands associating each required tag with its input pin.

Abstract: An MDES extractor automatically extracts a machine description (MDES) for re-targeting a compiler from a structural representation of a datapath of an explicitly parallel instruction computing (EPIC) processor. The datapath is a machine readable data structure that specifies the functional unit instances and an interconnect of the functional unit instances to registers. The MDES extractor structurally traverses the interconnect, identifying resource conflicts among the operations in the processor's opcode repertoire. Latencies and internal resources of the opcodes associated with the functional unit instances are obtained from a macrocell library. The MDES extractor then identifies external resource conflicts by preparing reservation tables for the functional units.

Abstract: A flexible and reliable state machine and a semiconductor device using the state machine are provided. A state machine includes a memory circuit (1), a comparator circuit (2), an analyzer circuit (3) and an arithmetic circuit (4). The memory circuit (1) receives and holds data (5-1a) indicative of the next state, and outputs it as data (5-1b) indicative of present state. The comparator circuit (2) compares the date (5-2a) indicative of the present or next state and generates a state flag (6-2b). The analyzer circuit (3) decodes a state flag (6-3a) and generates the control signal (7-3b) for controlling operation of the arithmetic circuit (4). Based on a control signal (7-4a), the arithmetic circuit (4) operates on the data (5-4a) indicative of the present state and generates data (5-4b) indicative of the next state.

Abstract: Clock cycle simulation involves modeling of clock cycles in a hardware module with a software model. Each simulated clock cycle involves several individual stages: Start, Execute, and End. During the start stage, output pin values for the model are calculated from an initial state of the module being simulated. Between the start stage and the execution stage, a combinatorial function of the modules outputs can be calculated. These calculated functions may be used as inputs to the modules in the execution stage. Afterwards, during the execute stage, input pin values are received by the model and the next state of the module is calculated based upon the current module state and the input pin values. Finally, during the last stage, i.e., the end stage, the internal state is updated; the internal state is defined as a set of the module's internal register and memory values.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: A method for operating a data processing system to simulate a mixer having an RF port, a LO port, and an IF port.

Abstract: A system and method is provided for simulating computer network devices. The method executes a user interface which presents a scenario which includes tasks a user is to perform by interacting with one or more simulated network devices. A network diagram having icons displays a network topology. By selecting an icon a simulated network device is executed and a communication interface to the simulated network device is opened. Commands to the simulated network device issued through the communication interface are interpreted and responded to in substantially the same manner as a corresponding actual network device. In addition, for each simulated network router a routing table is generated and maintained to allow the simulated network devices to respond to commands as realistically as possible. Tasks completed by a user are monitored and evaluated to determine whether the user successfully completed the required tasks.

Abstract: A mechanism is disclosed for determining a voltage at a device in a power delivery network. The mechanism includes determining an impulse response for the power delivery network, and tracking the current consumed by the device as it operates over a sequence of clock cycles. The activity profile is filtered using a representation of the impulse response to provide a profile of the voltages at the device.

Abstract: The present invention includes simulation system devices and methods. The invention can be used to collect information describing a desired data exchange between simulated devices and can assist in the generation of simulation model control programs that implement the desired data exchange. The disclosed methods feature generating simulation control code by interacting with a user to receive an address constraint and by generating a collection of data transfer instructions. Each data transfer instruction includes a data transfer address selected from a collection of addresses. The disclosed systems feature a simplified simulation data entry system including means for receiving address constraint information delimiting a collection of data transfer address values and means for generating a collection of simulation data transfer instructions. Each data transfer instruction may include an address selected from the collection of data transfer address values.

Abstract: Provided are test systems, methods, and media which allow a user to script any type of test or model scenario based on a particular type of network traffic (e.g., protocol interaction). In preferred embodiments, the script provides for the generation of packets (stimuli) which are used to provoke responses in order to model or test proper operation of one or more network protocols. The invention includes a scripting language, also referred to as a stimulus/response engine, which includes commands specifying a state change of a network device, and provides for the establishment of packet filters based on expected network traffic, receiving and matching arriving packets with packet filters, and, where there is a match, conducting actions specified by the user in the script. A stimulus/response engine (SRE) in accordance with the present invention is dynamic it that it accommodates patterns (packet filters) which are modified during test runs.

Abstract: An integrated support tool set that allows a programmer to design an efficient pipelined FPGA.

Abstract: A system, method and article of manufacture are provided for network-based configuration of a programmable logic device. A default application is initiated on a programmable logic device. A file request for configuration data from the logic device is sent to a server located remotely from the logic device utilizing a network. The configuration data is received from the network server. The configuration data is used to configure the logic device to run a second application. The second application is run on the logic device.

Abstract: The system level simulation method of the present invention comprises the steps of: dividing the simulation target device into a first circuitry portion and a second circuitry portion; emulating the first circuitry portion by an emulation subject circuit constructed by a rewritable hardware; simulating the second circuitry portion by a partial circuit process substitute section constructed by software; and allowing communication of data between the emulation subject circuit and the partial circuit process substitute section.

Abstract: An apparatus and method for hardware logic verification data transfer checking are implemented. Data for transfer is generated in response to a decoded bus transaction instruction using a pseudorandom number generator. The seed for the generator includes a predetermined portion provided to each bus device. The predetermined portion is combined with the address of the target device, obtained from the decoded instruction, to form the seed input to the random number generator. For write transactions, the bus master generates the data to be transferred using the seed, and sends the data to the target. The target independently generates the data by a call to the random number generator and compares the value received via the data transfer with the independently generated value. Similarly, for read transactions, the slave device generates the data to be transferred in response to the read request.

Abstract: A method for displaying the results of predicted wireless communication system performance as a three-dimensional region of fluctuating elevation and/or color within a three-dimensional computer drawing database consisting of one or more multi-level buildings, terrain, flora, and additional static and dynamic obstacles (e.g., automobiles, people, filing cabinets, etc.). The method combines computerized organization, database fusion, and site-specific performance prediction models. The method enables a design engineer to visualize the performance of any wireless communication system as a three-dimensional region of fluctuating elevation, color, or other aesthetic characteristics with fully selectable display parameters, overlaid with the three-dimensional site-specific computer model for which the performance prediction was carried out.

Abstract: A test bench generation technique is described in which a simulation of test operation is performed using a full subsystem circuit model 2 and full surrounding circuit models 4, 6, and 8. The input and output signals are recorded as a print on change file 10. This print on change file is used in combination with a classification of whether signals are inputs, outputs or bidirectional and associated rules for outputs and bidirectional signals when outputs to establish a reduced model concentrating on the interaction between the subsystyem circuit under test and the surrounding circuit elements. This reduced model 34 replays input data and applies rules to output data rather than actually modelling the full behaviour of the surrounding circuits. The rules associated with output signals can involve time windows, strobing relationships, settling times and settled times amongst other characteristics.

Abstract: A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell “library” within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition.

Abstract: This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability on multiprocessor systems. Furthermore, the invention includes a unique remote logic simulation and job scheduling capabilities.

Abstract: An electronic system (L) has a configurable electronic circuit (38) for replicating an output signal from a respective known electronic system replaceable sub-component module (32) of a known electronic master system (L). The output signal (68) from the electronic system sub-component (32) is generated as the result of the function of the electronic system sub-component (32). An input/output interface (30) electronically mates the configurable electronic circuit (38) to the electronic master system (L). A configuration controller element (40) is electronically connectable with the configurable electronic circuit (38), and configures the configurable electronic circuit (38) to replicate a selected function and operational characteristics of the known electronic system sub-component (32).

Abstract: A method and system of emulating an input/output (I/O) device in a mainframe environment. A started task executing as part of the operating system gains control of I/O instructions directed to virtual devices by insuring that such I/O instructions cause interrupts. The started task then hooks the branch point for such interrupts. Upon obtaining control, the started task causes the I/O source to believe a transaction with a predefined data space in a general storage area on board the mainframe is actually a transaction with a physical device.

Abstract: A method and system for simulation of a communications bus. A simulation arrangement is configured with a behavioral agent and an application agent coupled to the bus. Bus commands are selectively loaded in the behavioral and application agent in accordance with a desired simulation sequence. The behavioral agent is configurable with phase behavior instructions that specify assertion and deassertion times for selected signals by the behavioral agent. Compliant and non-compliant bus behavior can be simulated with the phase behavior instructions.

Abstract: A system and method for circuitry design verification testing using a structure of interface independent classes to provide for rapid prototyping and design modification while maximizing test code re-use. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class for collecting common routines and pointers to device transactions. One or more configuration transaction classes derived from the system transaction class define transactions between functional models within the simulation subsystem and cause instantiation of the respective functional models. Operations are performed on the functional models via pointers to interface independent transaction classes which define interfaces to the devices. The operations are mapped to the current designs of the functional models by subclasses of the interface independent transaction classes.

Abstract: A system and method which examines a user information resource and transforms data objects and object relationships from the resource into optimization metrics for storage in a problem solver database. A resource optimization system comprises a problem modeler having an interface for retrieving user data objects and object relationships describing a user application from a user information resource, a solver database to which the problem modeler has an interface for storing optimization metrics derived from the user data objects and object relationships by the problem modeler, and a problem solver having an interface to the solver database for retrieving the optimization metrics for solving resource optimization problems for the user application.

Abstract: A waveform generator embodied in a single tester unit. The hardware includes an integrated high frequency digital/analog signal generator that allows “infinite” length of signals, integrated colored noise source with thermal asperity generator and a PC style computer including standard storage systems and connectors that are custom configurable. Optionally, additional hardware such as an oscilloscope can be integrated to further centralize all the tools required by the engineer without adding interconnectivity problems for the engineer to deal with. The software includes a generic or standard operating system, GUI (graphical user interface), and specialized interface software for easy input/definition of sequences, waveform, and drive configuration. The software also includes a mathematical model of the head/disk system used in drives, with customization options, and the ability to do monte-carlo analysis to study distributions of signal waveforms.

Abstract: An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators. A software debugger interface permits a software application to be loaded and executed on the virtual embedded system. A virtual test bench may be coupled to the simulation to serve as a human-machine interface. In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project. IP components, such as processor cores, may be evaluated using a virtual embedded system. In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system.

Abstract: An image-sensor emulating device establishing a link with a host system by using peripheral interface bus. The image-sensor emulating device emulates the functions of image-sensors by programmably generating the relevant image-sensor and timing signals. Alternatively, the timing signals can also be generated from the timing signals outputted by an outside image-sensor. Therefore, the emulating device can generate predetermined image-sensor signals and timing signals such that the debugging process is simplified and the developing efficiency is improved. Moreover, the emulating device according to the present invention can also generate a timing signal serving as a reference timing signal for emulating an image-sensor. The reference timing signal can be used to compare with the actual timing signals of an image-sensor.

Abstract: A network's components are represented in the form of data signals arranged into a hierarchical tree structure. A population comprising a large number of randomly created tree structures, each relating to an individual network, is generated. The tree structures undergo a process of evolution through successive generations, by selectively breeding the most successful tree structures. Through the process of breeding, one or a plurality of optimal tree structures emerges. A network is constructed in accordance with the data signals represented by the optimal tree structure. The network may be any network comprising a set of nodes and links, e.g. a gas pipeline network, an electricity supply network, a water pipeline network or the like, but the disclosure is particularly relevant to a telecommunications network or a computer network.

Abstract: A system and method perform a two-pass fault simulation on an original design representation including a software-modeled design element and a hardware-modeled design element. Logic simulation generates input stimulus for a port on the boundary of the software-modeled design element and the hardware-modeled design element, where such ports are output ports of the software-modeled design element and input ports of the hardware-modeled design element. The input stimulus is merged with test patterns for the original design representation. A modified design representation is generated by replacing the software-modeled design element with a nonfunctional block. Most or all possible faults in the hardware-modeled design representation are seeded. The modified design representation is fault simulated in a first pass using the merged input stimulus and test patterns.

Abstract: An apparatus for verifying the functionality of a production line electronics safety tester such as the hipot tester/ground continuity tester. The apparatus simulates a product to be tested by a safety tester and can be configured to simulate a passing or failing product for each of a plurality of separate tests.

Abstract: In the emulation of a target system utilizing a multiprocessor (12) host system (10) with a longer word length than the target system, processor, memory, and cache overhead are minimized by utilizing a locked compare-exchange to update fill words in memory. The old contents of a word (48) in memory are loaded (80) into a first register (52). A loop is then entered. The contents of the first register (52) are copied (82) into a second (54). The contents of the second register (54) are then appropriately modified (84), depending on the instruction being emulated. After a lock (90), the two registers are compare-exchanged (86) with the memory word (48), resulting in the modified second register (54) being written to the memory word (48) if the contents of the first register (52) match. Otherwise, the compare-exchange instruction (86) loads the current copy of the word (48) into the first register (52), and the loop repeats.

Abstract: In an intelligent object oriented agent system, a computer implemented or user assisted method of decision making in at least one situation. The method includes the step of configuring at least one tactical agent implemented by at least one tactical agent object that includes a plurality of resources corresponding to immediate certainties, near certainties, and longer-term possibilities characterizing the at least one situation. The method also includes the steps of processing the at least one situation using the at least one tactical agent, and implementing the decision making, by at least one user or independently by at least one intelligent agent responsive to the processing step. A computer readable tangible medium stores instructions for implementing the user assisted or computer implemented method of decision making, which instructions are executable by a computer. In a preferred embodiment, the situation comprises an aerial combat situation, or other situation with moving resources.

Abstract: Hardware and software of a system is co-verified with synchronization events generated in the respective hardware and software verifications being accumulated and provided to the other verification on a periodic basis. The faster verification is halted to allow the slower verification to catch up, upon expiration of a synchronization window. Once caught up, the accumulated synchronization events are provided to the respective other verification. The transferred synchronization events are then in turn injected into the other verification at the same offset time into a synchronization period the synchronization events occurred in the previous synchronization period.

Abstract: Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for the integrated circuit is specified, including specifying the locations of multiple androgynous interfaces in the integrated circuit. In another step, one or more component blocks to comprise the integrated circuit are identified for use. In another step, the component blocks to form a layout of the integrated circuit are positioned in a manner that minimizes connection distances between functional blocks and between functional blocks and the androgynous interfaces. In another step, the androgynous interfaces are set to perform as targets (slaves) or initiators (masters) based on the layout.

Abstract: A method for evaluating and correcting a model of an electronic circuit. A list is created which comprises the minimum number of components that must be specified by the operator in order to be able to compute values for the remaining circuit components. Correction of circuit models can be performed even in cases of limited accessibility to the circuit's nodes.

Abstract: A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters. Specifically, an embodiment of the present invention provides a method and/or computer program product for determining optimal values for the design parameters of a circuit block, which result in optimally assigned delay targets for datapath blocks at the minimum power/area point. The problem/solution space is extended to solve the problem of figuring out the best possible implementation, for example, static vs dynamic, for each datapath block. Based on parameter functions, which relate to the design parameters for circuits in the circuit block, the design parameters are optimized to satisfy the design constraints.

Abstract: It is an object of the present invention to provide a simulation apparatus capable of easily evaluating dynamic characteristics of a circuit including a ferroelectric device quantitatively. Means 30 and 32 calculate dynamic capacitance of a without-polarization reversal term, Cp, and a with-polarization reversal term, Cr, respectively, by differentiating the without-polarization reversal term fQp and the with-polarization reversal term fQr, respectively, representing simple saturation functions with the voltages applied to the ferroelectric part. Means 34 calculates dynamic capacitance Cd of the ferroelectric part by composing both the dynamic capacitance Cp and the dynamic capacitance Cr. Means 36 determines dynamic time constants &tgr; of the circuit including the ferroelectric part in accordance with the dynamic capacitance Cd. Means 38 determines both transient charge response q(t) and transient current response i(t) and the like in accordance with the time constants &tgr;.

Abstract: A technique for system-wide emulation of an embedded system. The technique includes the addition of emulation software and an intermediary operating system. The intermediary operating system is used to avoid modification of system software. The emulation software is used to generate objects that simulate hardware features of the embedded system and to signal when control features of these objects have been selected.

Abstract: The system for simulating user input to control the operation of an application includes a processor and software operable on the processor to enable the selection of application specification information and execution input information. The selected application specification information is indicative of execution parameter information to facilitate the identification of application parameter information. The selected application specification information and execution input information is maintained on a storage device, and is indicative of a desired operation of the application. In order to simulate user input, the software provides the execution input information to the application parameter information when the execution parameter information corresponds substantially to the application parameter information to achieve the desired application operation.

Abstract: A system for testing an embedded system containing a target processor executing a target program and target hardware that may be partially physical and partially simulated. A target monitor determines when the target processor is attempting to access the simulated hardware. This determination is made by monitoring the address bus of the microprocessor to detect an address in the address space of the simulated hardware. An attempt to access the simulated hardware may also be detected by detecting the lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware. In the event of an access to the simulated hardware, a bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator.

Abstract: A method determines a random permutation of input lines that produced a permuted set of bits in a bitstream. In a source design, the method replaces a logic element whose input lines are permutable with a test function. The source design is processed by a design tool to generate the bitstream including the permuted set of bits. The test function is probed with test values, and the probe results are compared with the permuted set of bits to discover the permutation of the set of bits. The test values can include a message.

Abstract: A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit.

Abstract: A computer system including computer resources, an operating system operative to control said computer resources; and a 3D interface enabling a user to interact with the operating system and operative to provide a plurality of display representations of at least a portion of the computer resources from a corresponding plurality of different viewpoints.

Abstract: A verification engine for verifying the design of a target system having a plurality of components interconnected by a plurality of target system buses is disclosed. The verification engine comprises a first hardware model and a second hardware model, both configured as a component and having a set of hardware model input/output pins. In addition, a first bus wrapper is connected to the first hardware model and a second bus wrapper is connected to the second hardware model. Further, a set of bus lines are each connected to the first bus wrapper and the second bus wrapper. Each bus wrapper also has switchable communicative circuitry that switchably communicatively connects each hardware model input/output pin to a bus line and has a control block controlling the switchable communicative circuitry. A system controller is connected to at least some of the bus lines and is adapted to transmit a sequence of time synchronization information to each bus wrapper control block by way of the bus lines.

Abstract: A system for viewing and monitoring the operation of an embedded processor in which a single computer program, e.g., a Microsoft C/C++3 program, is used to test the scan chain, check the link to the target device, set up the target devices on the scan chain, load the program into the device, run the program, and display the results of the program. The present invention monitors the target processor activity, such as data flow in and out of the target processor, tracking of routines running on the target processor, and the like. Instead of relying on fixed breakpoints, the present invention utilizes breakpoints embedded in the program, enabling the user to use as many breakpoints as desired and to place them and move them wherever they are needed. The breakpoints are defined and set up in the target code (e.g. a diagnostic program) and not by the host. This allows runtime flexibility because the number and location of the breakpoints can be changed easily.

Abstract: The invention refers to a device for monitoring the application of a neutral electrode in unipolar HF surgery, having an impedance sensor with a resonant circuit comprising a secondary coil of a transformer and HF input capacitors of preferably two partial electrode surfaces. The impedance sensor detects the transient impedances of two partial electrode surfaces connected in series with the patient's tissues by application of a patient auxiliary current and is moderated by the transition impedances. The invention is characterized in that the resonant circuit is excited by alternating voltages of variable frequencies in the range of a resonant frequency, and in that a peak value detector is provided which detects an alternating voltage peak value at the resonant frequency. The disclosed device excites the resonant circuit in such a manner that a faultless measurement of the transition impedance at the level of the patient's tissues is made possible.

Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator. The analysis also adds hooks to the user program such that executing the analyzed user program on the host computer system invokes a cache simulator that simulates operation of the cache.