Target Device Patents (Class 703/20)
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Patent number: 6766311Abstract: An interactive computer-based training (ICBT) system operable over a computer network for training users. The ICBT system is provided with inter-dependent, state-machine-based hardware and software simulators for emulating hardware and software functionality associated with a piece of equipment on which the users are to receive interactive training. The state transition method effectuated in a computer-readable memory system includes the steps of: identifying a current state of the state machine wherein a transition is to be effectuated; determining if there is a state immediately prior to the current state, and if so, determining whether there is a dependency of the current state on the immediately prior state, the dependency being characterized as a first order dependency; inferring a reference value associated with the current state based on the first order dependency; and determining a future state of the state machine based on the inferred reference value.Type: GrantFiled: November 9, 1999Date of Patent: July 20, 2004Assignee: WorldCom, Inc.Inventors: Robert S. Wall, Donald R. Warner, Jackie R. Closson, Patrick J. Doggett
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Patent number: 6763327Abstract: A hardware abstraction layer operates as a system architectural layer between a real-time operating system and an underlying configurable processor. The hardware abstraction layer provides an abstraction of processor-specific functionality to the operating system. In particular, it abstracts configurable processor features visible to the operating system to provide a uniform, standardized interface between the operating system and the configurable processor on which it runs. Thus, an operating system running on top of the hardware abstraction layer will work on all configurations of the processor which differ from one another only in the configuration parameters covered by the hardware abstraction layer. The hardware abstraction layer may be generated using the same information that is used to describe the features being configured in the configurable processor.Type: GrantFiled: February 17, 2000Date of Patent: July 13, 2004Assignee: Tensilica, Inc.Inventors: Christopher Mark Songer, Pavlos Konas, Marc E. Gauthier, Kevin C. Chea
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Patent number: 6757873Abstract: First characteristic values (SS, FF) which fluctuate most of the characteristic of a device composing a semiconductor device are obtained according to a fluctuation of manufacturing process for the semiconductor device. Next, the width (optimized K value) of a fluctuation width of manufacturing process which matches second characteristic values (C1, C16) of the worst cases of the characteristic of this device with the first characteristic values (SS, FF) is determined. Finally, a third characteristic value of the worst case of the circuit characteristic of the semiconductor device is determined based on this fluctuation width (optimized K value).Type: GrantFiled: September 26, 2001Date of Patent: June 29, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Tetsuya Yamaguchi
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Hardware and software co-simulation including simulating a target processor using binary translation
Patent number: 6751583Abstract: A co-simulation design system to simulate on a host an electronic system that includes target digital circuitry and a target processor with an accompanying user program. The system includes a processor simulator to simulate execution of the user program by executing host software that includes an analyzed version of the user program. The system further includes a hardware simulator to simulate the target digital circuitry and an interface mechanism that couples the hardware simulator with the processor simulator. The user program is provided in binary form. Determining the analyzed version of the user program includes decomposing the user program into linear blocks, translating each linear block of the user program into host code that simulate the operations of the linear block, storing the host code of each linear block in a host code buffer for the linear block, and adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program.Type: GrantFiled: August 20, 2001Date of Patent: June 15, 2004Assignee: VaST Systems Technology CorporationInventors: Neville A. Clarke, James R. Torossian -
Patent number: 6741958Abstract: A method for modeling digital signal processors (DSP) in a C++ environment is disclosed. In particular, the method models and converts an operation (or function) from a floating-point model to a given DSP fixed-point processor model. The invention defines a vector space for each DSP fixed-point processor, as a direct sum of each distinct fixed bit length data representation sub-space. The direct sum of all DSP fixed-point processor vector sub-spaces forms a working vector space. Furthermore, the invention defines an operator projection to be performed on the working vector space such that redundancy in the operational behavior of the DSP's to be modeled may be exploited. In the preferred embodiment, the working vector space is in a C++ environment. A C++ class is defined for each distinct fixed bit length data representation of a given DSP fixed-point processor.Type: GrantFiled: November 15, 2000Date of Patent: May 25, 2004Inventors: Anastasios S. Maurudis, John O. Della Morte, Jr., James T. Della Morte
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Patent number: 6738756Abstract: A method and apparatus of analyzing a target system comprises receiving information relating to an environment of the target system and storing cost data based on the environment information. The plan and its estimated performance for a query may be determined based on the cost data. The environment information may pertain to the environment of a parallel system (e.g., a multi-node parallel system, a single-node parallel system having plural central processing units or a system running plural virtual processors) that is running a parallel database. The cost data may identify a number of nodes in the target system, a number of central processing units in each node of the target system, and other types of system information. The cost data may be stored in a relational table having a plurality of rows. Each row of the relational table may correspond to a different target system.Type: GrantFiled: June 30, 2000Date of Patent: May 18, 2004Assignee: NCR CorporationInventors: Douglas P. Brown, Paul Sinclair
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Patent number: 6718294Abstract: A debugging environment for a multi-processor simulator or emulator is disclosed. The simulator or emulator is ideally suited for the development of embedded software. The simulator can contain multiple processor models, with each processor model representing a processor. The simulator or emulator also includes a scheduler which controls the execution of the processor models. Each processor also communicates with a debugger via a debug adapter. The debug adapter acts as a pass-through filter for non-control commands which are communicated between a processor and its attached debugger. However, the debug adapter routes control commands to the scheduler. The scheduler ensures that all of the processors and debuggers maintain synchronization. Other modules can also be included in the multi-processor simulation environment, for example, clock gate modules.Type: GrantFiled: May 16, 2000Date of Patent: April 6, 2004Assignee: Mindspeed Technologies, Inc.Inventor: Ulrich Bortfeld
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Patent number: 6697774Abstract: A modelling tool for use in defining an ASP which receives as its input an input file which for each of a set of peripherals defines the functional attributes of that peripheral in a high level language with an input data structure and which generates from the input file, (i) an interface functions file, which defines the communication attributes of the peripheral with the processor and the functional attributes of the peripheral in a manner independent of any particular data structure, (ii) a test functions file which defines the communication attributes of the processor with the peripheral in a manner independent of any particular data structure, and (iii) a register definition file by allocating specific elements of the input data structure to predefined sectors of a register definition table.Type: GrantFiled: June 28, 1999Date of Patent: February 24, 2004Assignee: STMicroelectronics LimitedInventor: Gajinder Singh Panesar
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Patent number: 6684182Abstract: A spacecraft emulation system that can emulate both the attitude control subsystem and the non-attitude control subsystem is integrated into a single compact unit. The unit includes an emulated spacecraft control processor for processing attitude control information and an emulated central command and telemetry unit for interfacing simulated spacecraft data. The inlet also includes a first simulation engine that is operative to simulate the spacecraft attitude control system and a second simulation engine that is operative to simulate the spacecraft power, thermal, propulsion and payload subsystems. Both the first and second simulation engines are connected to the emulated spacecraft control processor via a respective bus. A host computer provides the command data and receives the telemetry data from the emulated spacecraft control processor.Type: GrantFiled: March 20, 2000Date of Patent: January 27, 2004Assignee: Hughes Electronics CorporationInventors: Jeffrey J. Gold, David L. Koza, Michael J. Surace, Steven R. Zammit
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Patent number: 6678645Abstract: A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].Type: GrantFiled: October 28, 1999Date of Patent: January 13, 2004Assignee: Advantest Corp.Inventors: Rochit Rajsuman, Hiroaki Yamoto
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Patent number: 6678644Abstract: Integrated circuit models having associated timing and tag information therewith for use with electronic design automation to effectively model timing exception information. The present invention includes a circuit block model which allows automated circuit optimization to be performed on extremely large circuits without the need to load all of the details of the circuit into computer memory. The circuit models of the present invention effectively model timing including timing exception information. The model of the present invention is associated with command information, e.g., textual commands, that describe tags (which model exceptions) and arrival and required times associated with the tags. Specifically, for the input pins of a circuit to be modeled, the present invention writes out a command defining each unique required tag associated with an input pin and also writes out commands associating each required tag with its input pin.Type: GrantFiled: September 13, 1999Date of Patent: January 13, 2004Assignee: Synopsys, Inc.Inventor: Russell B. Segal
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Patent number: 6629312Abstract: An MDES extractor automatically extracts a machine description (MDES) for re-targeting a compiler from a structural representation of a datapath of an explicitly parallel instruction computing (EPIC) processor. The datapath is a machine readable data structure that specifies the functional unit instances and an interconnect of the functional unit instances to registers. The MDES extractor structurally traverses the interconnect, identifying resource conflicts among the operations in the processor's opcode repertoire. Latencies and internal resources of the opcodes associated with the functional unit instances are obtained from a macrocell library. The MDES extractor then identifies external resource conflicts by preparing reservation tables for the functional units.Type: GrantFiled: August 20, 1999Date of Patent: September 30, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventor: Shail Aditya Gupta
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Patent number: 6625572Abstract: Clock cycle simulation involves modeling of clock cycles in a hardware module with a software model. Each simulated clock cycle involves several individual stages: Start, Execute, and End. During the start stage, output pin values for the model are calculated from an initial state of the module being simulated. Between the start stage and the execution stage, a combinatorial function of the modules outputs can be calculated. These calculated functions may be used as inputs to the modules in the execution stage. Afterwards, during the execute stage, input pin values are received by the model and the next state of the module is calculated based upon the current module state and the input pin values. Finally, during the last stage, i.e., the end stage, the internal state is updated; the internal state is defined as a set of the module's internal register and memory values.Type: GrantFiled: December 22, 1999Date of Patent: September 23, 2003Assignee: LSI Logic CorporationInventors: Boris Zemlyak, Ronen Perets, Brian F. Schoner
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Patent number: 6625783Abstract: A flexible and reliable state machine and a semiconductor device using the state machine are provided. A state machine includes a memory circuit (1), a comparator circuit (2), an analyzer circuit (3) and an arithmetic circuit (4). The memory circuit (1) receives and holds data (5-1a) indicative of the next state, and outputs it as data (5-1b) indicative of present state. The comparator circuit (2) compares the date (5-2a) indicative of the present or next state and generates a state flag (6-2b). The analyzer circuit (3) decodes a state flag (6-3a) and generates the control signal (7-3b) for controlling operation of the arithmetic circuit (4). Based on a control signal (7-4a), the arithmetic circuit (4) operates on the data (5-4a) indicative of the present state and generates data (5-4b) indicative of the next state.Type: GrantFiled: October 10, 2001Date of Patent: September 23, 2003Assignee: Logic Research Co., Ltd.Inventor: Kei Yamanaka
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Patent number: 6618698Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.Type: GrantFiled: August 12, 1999Date of Patent: September 9, 2003Assignee: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, N. James Tomassetti
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Publication number: 20030144827Abstract: A method for operating a data processing system to simulate a mixer having an RF port, a LO port, and an IF port.Type: ApplicationFiled: January 30, 2002Publication date: July 31, 2003Inventor: Jianjun Yang
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Publication number: 20030125924Abstract: A system and method is provided for simulating computer network devices. The method executes a user interface which presents a scenario which includes tasks a user is to perform by interacting with one or more simulated network devices. A network diagram having icons displays a network topology. By selecting an icon a simulated network device is executed and a communication interface to the simulated network device is opened. Commands to the simulated network device issued through the communication interface are interpreted and responded to in substantially the same manner as a corresponding actual network device. In addition, for each simulated network router a routing table is generated and maintained to allow the simulated network devices to respond to commands as realistically as possible. Tasks completed by a user are monitored and evaluated to determine whether the user successfully completed the required tasks.Type: ApplicationFiled: December 26, 2002Publication date: July 3, 2003Applicant: TestOut CorporationInventors: Vardell Lines, Don Whitnah
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Publication number: 20030125923Abstract: A mechanism is disclosed for determining a voltage at a device in a power delivery network. The mechanism includes determining an impulse response for the power delivery network, and tracking the current consumed by the device as it operates over a sequence of clock cycles. The activity profile is filtered using a representation of the impulse response to provide a profile of the voltages at the device.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Inventors: Edward T. Grochowski, David J. Ayers, Vivek Tiwari
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Patent number: 6571204Abstract: The present invention includes simulation system devices and methods. The invention can be used to collect information describing a desired data exchange between simulated devices and can assist in the generation of simulation model control programs that implement the desired data exchange. The disclosed methods feature generating simulation control code by interacting with a user to receive an address constraint and by generating a collection of data transfer instructions. Each data transfer instruction includes a data transfer address selected from a collection of addresses. The disclosed systems feature a simplified simulation data entry system including means for receiving address constraint information delimiting a collection of data transfer address values and means for generating a collection of simulation data transfer instructions. Each data transfer instruction may include an address selected from the collection of data transfer address values.Type: GrantFiled: August 4, 1998Date of Patent: May 27, 2003Assignee: Micron Technology, Inc.Inventor: James W. Meyer
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Patent number: 6549882Abstract: Provided are test systems, methods, and media which allow a user to script any type of test or model scenario based on a particular type of network traffic (e.g., protocol interaction). In preferred embodiments, the script provides for the generation of packets (stimuli) which are used to provoke responses in order to model or test proper operation of one or more network protocols. The invention includes a scripting language, also referred to as a stimulus/response engine, which includes commands specifying a state change of a network device, and provides for the establishment of packet filters based on expected network traffic, receiving and matching arriving packets with packet filters, and, where there is a match, conducting actions specified by the user in the script. A stimulus/response engine (SRE) in accordance with the present invention is dynamic it that it accommodates patterns (packet filters) which are modified during test runs.Type: GrantFiled: December 21, 1998Date of Patent: April 15, 2003Assignee: Cisco Technology, Inc.Inventors: Huei-Ping Chen, Ting Chuan Tan
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Publication number: 20030069723Abstract: An integrated support tool set that allows a programmer to design an efficient pipelined FPGA.Type: ApplicationFiled: July 3, 2002Publication date: April 10, 2003Applicant: DATACUBE, INC.Inventor: Uday M. Hegde
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Publication number: 20030036895Abstract: A system, method and article of manufacture are provided for network-based configuration of a programmable logic device. A default application is initiated on a programmable logic device. A file request for configuration data from the logic device is sent to a server located remotely from the logic device utilizing a network. The configuration data is received from the network server. The configuration data is used to configure the logic device to run a second application. The second application is run on the logic device.Type: ApplicationFiled: January 29, 2001Publication date: February 20, 2003Inventors: John Appleby-Alis, Alex Wilson
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Publication number: 20030033131Abstract: The system level simulation method of the present invention comprises the steps of: dividing the simulation target device into a first circuitry portion and a second circuitry portion; emulating the first circuitry portion by an emulation subject circuit constructed by a rewritable hardware; simulating the second circuitry portion by a partial circuit process substitute section constructed by software; and allowing communication of data between the emulation subject circuit and the partial circuit process substitute section.Type: ApplicationFiled: April 27, 1999Publication date: February 13, 2003Inventor: YOSHIYUKI ITO
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Patent number: 6507808Abstract: An apparatus and method for hardware logic verification data transfer checking are implemented. Data for transfer is generated in response to a decoded bus transaction instruction using a pseudorandom number generator. The seed for the generator includes a predetermined portion provided to each bus device. The predetermined portion is combined with the address of the target device, obtained from the decoded instruction, to form the seed input to the random number generator. For write transactions, the bus master generates the data to be transferred using the seed, and sends the data to the target. The target independently generates the data by a call to the random number generator and compares the value received via the data transfer with the independently generated value. Similarly, for read transactions, the slave device generates the data to be transferred in response to the read request.Type: GrantFiled: June 23, 1999Date of Patent: January 14, 2003Assignee: International Business Machines CorporationInventor: Peter Dean LaFauci
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Patent number: 6499006Abstract: A method for displaying the results of predicted wireless communication system performance as a three-dimensional region of fluctuating elevation and/or color within a three-dimensional computer drawing database consisting of one or more multi-level buildings, terrain, flora, and additional static and dynamic obstacles (e.g., automobiles, people, filing cabinets, etc.). The method combines computerized organization, database fusion, and site-specific performance prediction models. The method enables a design engineer to visualize the performance of any wireless communication system as a three-dimensional region of fluctuating elevation, color, or other aesthetic characteristics with fully selectable display parameters, overlaid with the three-dimensional site-specific computer model for which the performance prediction was carried out.Type: GrantFiled: July 14, 1999Date of Patent: December 24, 2002Assignee: Wireless Valley Communications, Inc.Inventors: Theodore S. Rappaport, Roger R Skidmore
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Publication number: 20020188432Abstract: A test bench generation technique is described in which a simulation of test operation is performed using a full subsystem circuit model 2 and full surrounding circuit models 4, 6, and 8. The input and output signals are recorded as a print on change file 10. This print on change file is used in combination with a classification of whether signals are inputs, outputs or bidirectional and associated rules for outputs and bidirectional signals when outputs to establish a reduced model concentrating on the interaction between the subsystyem circuit under test and the surrounding circuit elements. This reduced model 34 replays input data and applies rules to output data rather than actually modelling the full behaviour of the surrounding circuits. The rules associated with output signals can involve time windows, strobing relationships, settling times and settled times amongst other characteristics.Type: ApplicationFiled: May 15, 2001Publication date: December 12, 2002Inventors: Thomas Sean Houlihane, Richard David Ellis
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Patent number: 6480815Abstract: A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell “library” within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition.Type: GrantFiled: May 10, 1999Date of Patent: November 12, 2002Assignee: Synopsys, Inc.Inventors: Janet Olson, James Sproch, Yueqin Lin, Ivailo Nedelchev, Ashutosh S. Mauskar
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Patent number: 6466898Abstract: This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability on multiprocessor systems. Furthermore, the invention includes a unique remote logic simulation and job scheduling capabilities.Type: GrantFiled: January 12, 1999Date of Patent: October 15, 2002Inventor: Terence Chan
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Publication number: 20020143518Abstract: An electronic system (L) has a configurable electronic circuit (38) for replicating an output signal from a respective known electronic system replaceable sub-component module (32) of a known electronic master system (L). The output signal (68) from the electronic system sub-component (32) is generated as the result of the function of the electronic system sub-component (32). An input/output interface (30) electronically mates the configurable electronic circuit (38) to the electronic master system (L). A configuration controller element (40) is electronically connectable with the configurable electronic circuit (38), and configures the configurable electronic circuit (38) to replicate a selected function and operational characteristics of the known electronic system sub-component (32).Type: ApplicationFiled: March 28, 2001Publication date: October 3, 2002Inventor: Carl K. Abrahamson
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Patent number: 6453277Abstract: A method and system of emulating an input/output (I/O) device in a mainframe environment. A started task executing as part of the operating system gains control of I/O instructions directed to virtual devices by insuring that such I/O instructions cause interrupts. The started task then hooks the branch point for such interrupts. Upon obtaining control, the started task causes the I/O source to believe a transaction with a predefined data space in a general storage area on board the mainframe is actually a transaction with a physical device.Type: GrantFiled: January 28, 1999Date of Patent: September 17, 2002Assignee: Computer Associates Think, Inc.Inventors: David L. Helsley, Michael R. Chase
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Patent number: 6442514Abstract: A method and system for simulation of a communications bus. A simulation arrangement is configured with a behavioral agent and an application agent coupled to the bus. Bus commands are selectively loaded in the behavioral and application agent in accordance with a desired simulation sequence. The behavioral agent is configurable with phase behavior instructions that specify assertion and deassertion times for selected signals by the behavioral agent. Compliant and non-compliant bus behavior can be simulated with the phase behavior instructions.Type: GrantFiled: December 4, 1998Date of Patent: August 27, 2002Assignee: Xilinx, Inc.Inventor: Tony Viet Nam Le
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Patent number: 6421634Abstract: A system and method for circuitry design verification testing using a structure of interface independent classes to provide for rapid prototyping and design modification while maximizing test code re-use. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class for collecting common routines and pointers to device transactions. One or more configuration transaction classes derived from the system transaction class define transactions between functional models within the simulation subsystem and cause instantiation of the respective functional models. Operations are performed on the functional models via pointers to interface independent transaction classes which define interfaces to the devices. The operations are mapped to the current designs of the functional models by subclasses of the interface independent transaction classes.Type: GrantFiled: March 4, 1999Date of Patent: July 16, 2002Assignee: Sun Microsystems, Inc.Inventors: Glenn A. Dearth, George R. Plouffe, Jr., David M. Kaffine, Janet Y. Zheng
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Patent number: 6411922Abstract: A system and method which examines a user information resource and transforms data objects and object relationships from the resource into optimization metrics for storage in a problem solver database. A resource optimization system comprises a problem modeler having an interface for retrieving user data objects and object relationships describing a user application from a user information resource, a solver database to which the problem modeler has an interface for storing optimization metrics derived from the user data objects and object relationships by the problem modeler, and a problem solver having an interface to the solver database for retrieving the optimization metrics for solving resource optimization problems for the user application.Type: GrantFiled: December 30, 1998Date of Patent: June 25, 2002Assignee: Objective Systems Integrators, Inc.Inventors: Douglas Patrick Clark, Donald Martin, Jr.
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Patent number: 6397173Abstract: A waveform generator embodied in a single tester unit. The hardware includes an integrated high frequency digital/analog signal generator that allows “infinite” length of signals, integrated colored noise source with thermal asperity generator and a PC style computer including standard storage systems and connectors that are custom configurable. Optionally, additional hardware such as an oscilloscope can be integrated to further centralize all the tools required by the engineer without adding interconnectivity problems for the engineer to deal with. The software includes a generic or standard operating system, GUI (graphical user interface), and specialized interface software for easy input/definition of sequences, waveform, and drive configuration. The software also includes a mathematical model of the head/disk system used in drives, with customization options, and the ability to do monte-carlo analysis to study distributions of signal waveforms.Type: GrantFiled: May 3, 1999Date of Patent: May 28, 2002Assignee: Astec International LLCInventors: Robert Owen Campbell, Chitra Seshan
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Publication number: 20020059054Abstract: An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators. A software debugger interface permits a software application to be loaded and executed on the virtual embedded system. A virtual test bench may be coupled to the simulation to serve as a human-machine interface. In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project. IP components, such as processor cores, may be evaluated using a virtual embedded system. In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system.Type: ApplicationFiled: June 1, 2001Publication date: May 16, 2002Inventors: Stephen L. Bade, Shay Ben-Chorin, Paul Caamano, Marcelo E. Montoreano, Ani Taggu, Filip C. Thoen, Dean C. Wills
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Patent number: 6377910Abstract: An image-sensor emulating device establishing a link with a host system by using peripheral interface bus. The image-sensor emulating device emulates the functions of image-sensors by programmably generating the relevant image-sensor and timing signals. Alternatively, the timing signals can also be generated from the timing signals outputted by an outside image-sensor. Therefore, the emulating device can generate predetermined image-sensor signals and timing signals such that the debugging process is simplified and the developing efficiency is improved. Moreover, the emulating device according to the present invention can also generate a timing signal serving as a reference timing signal for emulating an image-sensor. The reference timing signal can be used to compare with the actual timing signals of an image-sensor.Type: GrantFiled: May 14, 1999Date of Patent: April 23, 2002Assignee: Mustek Systems Inc.Inventors: Adolf T. R. Hsu, Ching-Chih Fan
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Patent number: 6374202Abstract: A network's components are represented in the form of data signals arranged into a hierarchical tree structure. A population comprising a large number of randomly created tree structures, each relating to an individual network, is generated. The tree structures undergo a process of evolution through successive generations, by selectively breeding the most successful tree structures. Through the process of breeding, one or a plurality of optimal tree structures emerges. A network is constructed in accordance with the data signals represented by the optimal tree structure. The network may be any network comprising a set of nodes and links, e.g. a gas pipeline network, an electricity supply network, a water pipeline network or the like, but the disclosure is particularly relevant to a telecommunications network or a computer network.Type: GrantFiled: March 10, 1998Date of Patent: April 16, 2002Assignee: British Telecommunications public limited companyInventor: Gerald Robinson
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Patent number: 6370492Abstract: A system and method perform a two-pass fault simulation on an original design representation including a software-modeled design element and a hardware-modeled design element. Logic simulation generates input stimulus for a port on the boundary of the software-modeled design element and the hardware-modeled design element, where such ports are output ports of the software-modeled design element and input ports of the hardware-modeled design element. The input stimulus is merged with test patterns for the original design representation. A modified design representation is generated by replacing the software-modeled design element with a nonfunctional block. Most or all possible faults in the hardware-modeled design representation are seeded. The modified design representation is fault simulated in a first pass using the merged input stimulus and test patterns.Type: GrantFiled: December 8, 1998Date of Patent: April 9, 2002Assignee: LSI Logic CorporationInventor: Michelle R. Akin
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Publication number: 20020038205Abstract: An apparatus for verifying the functionality of a production line electronics safety tester such as the hipot tester/ground continuity tester. The apparatus simulates a product to be tested by a safety tester and can be configured to simulate a passing or failing product for each of a plurality of separate tests.Type: ApplicationFiled: June 18, 2001Publication date: March 28, 2002Inventors: Jeffrey Ross Gray, Jeffrey Douglas Lind
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Patent number: 6360194Abstract: In the emulation of a target system utilizing a multiprocessor (12) host system (10) with a longer word length than the target system, processor, memory, and cache overhead are minimized by utilizing a locked compare-exchange to update fill words in memory. The old contents of a word (48) in memory are loaded (80) into a first register (52). A loop is then entered. The contents of the first register (52) are copied (82) into a second (54). The contents of the second register (54) are then appropriately modified (84), depending on the instruction being emulated. After a lock (90), the two registers are compare-exchanged (86) with the memory word (48), resulting in the modified second register (54) being written to the memory word (48) if the contents of the first register (52) match. Otherwise, the compare-exchange instruction (86) loads the current copy of the word (48) into the first register (52), and the loop repeats.Type: GrantFiled: September 8, 1998Date of Patent: March 19, 2002Assignee: Bull HN Information Systems Inc.Inventor: David A. Egolf
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Patent number: 6360193Abstract: In an intelligent object oriented agent system, a computer implemented or user assisted method of decision making in at least one situation. The method includes the step of configuring at least one tactical agent implemented by at least one tactical agent object that includes a plurality of resources corresponding to immediate certainties, near certainties, and longer-term possibilities characterizing the at least one situation. The method also includes the steps of processing the at least one situation using the at least one tactical agent, and implementing the decision making, by at least one user or independently by at least one intelligent agent responsive to the processing step. A computer readable tangible medium stores instructions for implementing the user assisted or computer implemented method of decision making, which instructions are executable by a computer. In a preferred embodiment, the situation comprises an aerial combat situation, or other situation with moving resources.Type: GrantFiled: March 29, 1999Date of Patent: March 19, 2002Assignee: 21st Century Systems, Inc.Inventor: Alexander D. Stoyen
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Patent number: 6356862Abstract: Hardware and software of a system is co-verified with synchronization events generated in the respective hardware and software verifications being accumulated and provided to the other verification on a periodic basis. The faster verification is halted to allow the slower verification to catch up, upon expiration of a synchronization window. Once caught up, the accumulated synchronization events are provided to the respective other verification. The transferred synchronization events are then in turn injected into the other verification at the same offset time into a synchronization period the synchronization events occurred in the previous synchronization period.Type: GrantFiled: September 24, 1998Date of Patent: March 12, 2002Inventor: Brian Bailey
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Publication number: 20020016706Abstract: Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for the integrated circuit is specified, including specifying the locations of multiple androgynous interfaces in the integrated circuit. In another step, one or more component blocks to comprise the integrated circuit are identified for use. In another step, the component blocks to form a layout of the integrated circuit are positioned in a manner that minimizes connection distances between functional blocks and between functional blocks and the androgynous interfaces. In another step, the androgynous interfaces are set to perform as targets (slaves) or initiators (masters) based on the layout.Type: ApplicationFiled: January 18, 2001Publication date: February 7, 2002Applicant: Cadence Design Systems,Inc.Inventors: Laurence H. Cooke, Alexander Lu
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Patent number: 6334100Abstract: A method for evaluating and correcting a model of an electronic circuit. A list is created which comprises the minimum number of components that must be specified by the operator in order to be able to compute values for the remaining circuit components. Correction of circuit models can be performed even in cases of limited accessibility to the circuit's nodes.Type: GrantFiled: October 9, 1998Date of Patent: December 25, 2001Assignee: Agilent Technologies, Inc.Inventors: Cherif Ahrikencheikh, Rodney A. Browen, William P. Darbie, Kay C. Lannen, John E. McDermid, Jamie P. Romero
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Patent number: 6327558Abstract: It is an object of the present invention to provide a simulation apparatus capable of easily evaluating dynamic characteristics of a circuit including a ferroelectric device quantitatively. Means 30 and 32 calculate dynamic capacitance of a without-polarization reversal term, Cp, and a with-polarization reversal term, Cr, respectively, by differentiating the without-polarization reversal term fQp and the with-polarization reversal term fQr, respectively, representing simple saturation functions with the voltages applied to the ferroelectric part. Means 34 calculates dynamic capacitance Cd of the ferroelectric part by composing both the dynamic capacitance Cp and the dynamic capacitance Cr. Means 36 determines dynamic time constants &tgr; of the circuit including the ferroelectric part in accordance with the dynamic capacitance Cd. Means 38 determines both transient charge response q(t) and transient current response i(t) and the like in accordance with the time constants &tgr;.Type: GrantFiled: July 23, 1998Date of Patent: December 4, 2001Assignee: Rohm Co., Ltd.Inventor: Kiyoshi Nishimura
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Patent number: 6327552Abstract: A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters. Specifically, an embodiment of the present invention provides a method and/or computer program product for determining optimal values for the design parameters of a circuit block, which result in optimally assigned delay targets for datapath blocks at the minimum power/area point. The problem/solution space is extended to solve the problem of figuring out the best possible implementation, for example, static vs dynamic, for each datapath block. Based on parameter functions, which relate to the design parameters for circuits in the circuit block, the design parameters are optimized to satisfy the design constraints.Type: GrantFiled: December 28, 1999Date of Patent: December 4, 2001Assignee: Intel CorporationInventors: Mahadevamurty Nemani, Franklin Baez
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Patent number: 6317706Abstract: A technique for system-wide emulation of an embedded system. The technique includes the addition of emulation software and an intermediary operating system. The intermediary operating system is used to avoid modification of system software. The emulation software is used to generate objects that simulate hardware features of the embedded system and to signal when control features of these objects have been selected.Type: GrantFiled: March 31, 1998Date of Patent: November 13, 2001Assignees: Sony Corporation, Sony Electronics, Inc.Inventor: Joseph Saib
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Patent number: 6308146Abstract: The system for simulating user input to control the operation of an application includes a processor and software operable on the processor to enable the selection of application specification information and execution input information. The selected application specification information is indicative of execution parameter information to facilitate the identification of application parameter information. The selected application specification information and execution input information is maintained on a storage device, and is indicative of a desired operation of the application. In order to simulate user input, the software provides the execution input information to the application parameter information when the execution parameter information corresponds substantially to the application parameter information to achieve the desired application operation.Type: GrantFiled: October 30, 1998Date of Patent: October 23, 2001Assignee: J. D. Edwards World Source CompanyInventors: Leo J. La Cascia, Jr., James E. Downum
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Patent number: 6298320Abstract: A system for testing an embedded system containing a target processor executing a target program and target hardware that may be partially physical and partially simulated. A target monitor determines when the target processor is attempting to access the simulated hardware. This determination is made by monitoring the address bus of the microprocessor to detect an address in the address space of the simulated hardware. An attempt to access the simulated hardware may also be detected by detecting the lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware. In the event of an access to the simulated hardware, a bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator.Type: GrantFiled: February 17, 1998Date of Patent: October 2, 2001Assignee: Applied Microsystems CorporationInventors: Michael R. Buckmaster, Arnold S. Berger
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Patent number: 6292762Abstract: A method determines a random permutation of input lines that produced a permuted set of bits in a bitstream. In a source design, the method replaces a logic element whose input lines are permutable with a test function. The source design is processed by a design tool to generate the bitstream including the permuted set of bits. The test function is probed with test values, and the probe results are compared with the permuted set of bits to discover the permutation of the set of bits. The test values can include a message.Type: GrantFiled: July 13, 1998Date of Patent: September 18, 2001Assignee: Compaq Computer CorporationInventors: Laurent Rene Moll, Michael David Mitzenmacher, Andrei Z. Broder, Mark Alexander Shand