Abstract: An simulator particularly suited for simulating the hardware/software behavior of embedded systems. The architecture of the simulator permits the hardware and software systems to be modeled as modules with well characterized behaviors. A concise module definition syntax is used to describe module behaviors, and a translator operates upon the module to abstract operations of module behaviors at a level which does not require cycle-based, direct interaction of each module with the underlying simulation engine.

Abstract: A software development supporting system of the ROM emulation type is provided, which facilitates the electrical connection to a target system equipped with no ROM socket. This system is comprised of a ROM controller electrically connectable to a PCI bus of a target system, a ROM emulator for emulating an operation of a target ROM mounted on the target system, and a host computer electrical connected to the ROM emulator. The ROM controller receives a control signal for controlling the target ROM, in which the control signal is transmitted through the PCI bus of the target system. The ROM controller transfers the received control signal to the ROM emulator, thereby controlling the ROM emulator. Preferably, the ROM controller is designed to output an access assertion signal to the PCI bus before a ROM controller of the target system outputs an access assertion signal of the target ROM. Thus, the ROM emulator serves to emulate the target ROM using the control signal.

Abstract: An improved hybrid flow control protocol for providing FIFO capacity to prevent overflow due to bytes arriving after the FIFO indicates it is not ready to receive any more bytes utilizes a combination of a high/low watermark and credit based system. In one embodiment, when the byte count exceed the high watermark fixed credits are sent when N bytes are pulled from the FIFO. In a second embodiment, variable credits are sent depending on the difference between the number of bytes received in and pulled from the FIFO.

Abstract: An improved maintenance system and interface for use in a large-scale data processing system is provided. Within the data processing system, logic is partitioned into multiple logical groups. Each of the groups is associated with a bi-directional port, and each group may be intercoupled to other groups via the associated port. Within each of the groups, an internal condition detection circuit selectively monitors selected logic circuits to detect the presence of certain predetermined conditions or events. When an internal condition is detected, a notification is provided to the bi-directional port and broadcast over the interface to all other logic groups simultaneously. Each logic group further includes an external condition detection circuit interconnected to the respective bi-directional port whereby condition indicators are received from other logic groups as an external condition indicator.

Abstract: The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a network identify a new message flow, they determine the proper processing for packets in that message flow and cache that information for that message flow. Thereafter, when routers in a network identify a packet which is part of that message flow, they process that packet according to the proper processing for packets in that message flow. The proper processing may include a determination of a destination port for routing those packets and a determination of whether access control permits routing those packets to their indicated destination.

Abstract: The monitoring control apparatus according to the present invention performs a test on each integrated circuit that supports the boundary scan test method loaded on CPU board 4 and control board 5, and on the connection relationships of these integrated circuits, by a boundary scan controller board 7 like that shown, for example, in FIG. 1. If an abnormality is detected in CPU board 4 or control board 5, an alarm apparatus 9 is activated which emits an alarm. Moreover, if the type of abnormality is such that there is the risk of it having a significant effect on the operation of a robot 3, which is the target of this monitoring and control, from the viewpoint of safety, main power supply apparatus 6 of robot 3 is interrupted to prevent in advance robot 3 from running out of control.

Abstract: A microcontroller software testing tool is disclosed for testing and debugging software for a semiconductor circuit. The microcontroller software testing tool includes a simulator for simulating the execution of the software program on the target semiconductor circuit and an emulator to permit emulation before the actual silicon exists. The emulator utilizes the same high definition language specification, such as VHDL models, that define the silicon during the fabrication process plus additional logic to model behavior of the emulated processor. In a simulation mode, the microcontroller software testing tool simulates the target semiconductor circuit on a general purpose computing device, by interpreting the instructions in the software using an instruction set of the target semiconductor circuit, and otherwise behaving like the target semiconductor circuit; and executes and evaluates the software on the simulated semiconductor circuit.

Abstract: A circuit extracting apparatus or method of the present invention extracts circuit information which allows a drain current and a gate capacitance in an actual device to be reproduced with high fidelity in circuit simulation. Transistor-portion-configuration recognizing means recognizes the configuration of a transistor portion in the mask layout of a semiconductor circuit so as to generate transistor-portion-configuration data. Transistor-size calculating means calculates an equivalent transistor size based on the transistor-portion-configuration data, such that a drain current in the circuit simulation coincides with the drain current in the actual device. Corrective-capacitance generating means obtains the difference between a gate capacitance in the circuit simulation using the equivalent transistor size and the gate capacitance in the actual device so as to virtually generate a corrective capacitance having a capacitance value corresponding to the obtained difference.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation.

Abstract: The present invention relates to a diagnostic system for complex systems such as avionics systems. The diagnostic system acquires a description of the system from a variety of design tools and creates a causal network model as an intermediate step. From the causal network model, the diagnostic system builds and compiles a Q-DAG model of the system, which is then embedded in the central maintenance computer of the aircraft. The present invention integrates two elements, a graphical user interface (GUI), which acts as a data capture tool and graphical display of the avionics system and an inference system, which acts as a diagnostic tool with a presenter. The presenter permits diagnosis of faulty sub-systems and a report may be relayed to remotely located maintenance crews to minimize repair time upon arrival of the aircraft.

Abstract: A method and apparatus for sequencing the execution of a simulation system comprising at least two subsystem simulators. The simulation system further comprises a first and second simulator, a processor for executing program instructions of a control program stored in a memory coupled to the processor, a router for coupling first simulator inputs and outputs to second simulator outputs and inputs respectively, and an input device including a control and monitor panel for controlling said sequencing.

Abstract: A method for modeling digital signal processors (DSP) in a C++ environment is disclosed. In particular, the method models and converts an operation (or function) from a floating-point model to a given DSP fixed-point processor model. The invention defines a vector space for each DSP fixed-point processor, as a direct sum of each distinct fixed bit length data representation sub-space. The direct sum of all DSP fixed-point processor vector sub-spaces forms a working vector space. Furthermore, the invention defines an operator projection to be performed on the working vector space such that redundancy in the operational behavior of the DSP's to be modeled may be exploited. In the preferred embodiment, the working vector space is in a C++ environment. A C++ class is defined for each distinct fixed bit length data representation of a given DSP fixed-point processor.

Abstract: A test system in a communication system provides for a simulation of a test telephone call to a switching system under test. A test controller is integrated with the system under test for simulating the telephone call to the system under test. A high speed interface card with a processor is interfaced with the computer on the system under test through a computer bus interface for gathering call processing event data, A high speed interface communicates with the test controller to convey the simulated call processing event data to the controller computer.

Abstract: The design of logic for implementation in programmable logic array integrated circuit devices is facilitated by allowing various characteristics of modules in the logic design to be parameterized. Specific values for a parameter can be “inherited” by a logic module from other logic higher in the hierarchy of the logic design. Default values for parameters can also be provided. The user can design his or her own parameterized modules, and logic designs can be recursive, meaning that a logic module can make use of other instances of itself.

Abstract: An operating system is simulated to run in conjunction with a native operating system, allowing processes originally developed for the operating system being simulated to be ported to the environment of the native operating system with a minimum of effort. In the event a ported process attempts to communicate with a terminated process before the simulated operating system is notified of the termination, the attempt at communication will return an error. In response, a series of checks are performed to determine if the error was the result of termination of the process with which communication was attempted, or a more serious error that should be reported to the native operating system for action to protect the integrity of data.

Abstract: The invention provides an apparatus and a method for accurately and rapidly estimating a performance of an integrated circuit in the design at a register transfer level. A parsing member converts an HDL description of the integrated circuit at the register transfer level into a representation by using parse trees, and a parse tree allocation member allocates elements of the integrated circuit to respective nodes of the parse trees. A trade-off estimation member predicts a minimum area which can satisfy a timing constraint by applying estimation models stored in an estimation library to the respective elements of the integrated circuit represented by using connections between the elements, and by appropriately changing application of driver models stored in a driver library.

Abstract: Methods and apparatus are described for generating circuit parameters for a plurality of interconnect line circuit models. The plurality of circuit models represent a plurality of interconnect lines in a programmable logic device (PLD). Design description data corresponding to the PLD are generated at least in part from spreadsheet representations of the plurality of interconnect lines. A device model for the PLD is generated using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models. Operation of the PLD is simulated using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters. The modeled delay data are compared with measured delay data corresponding to the plurality of interconnect lines.

Abstract: A simulation model for a digital system comprises a number of functional units, interconnected by a number of interface units for transmitting messages between the functional units. Each interface unit includes a mechanism for automatically composing and decomposing messages into higher and lower levels of design. The interface thus provides a general mechanism which allows units at any level to communicate with units at any other level, for mixed-level modelling.

Abstract: A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.

Abstract: In an illustrative embodiment, the AC power line network simulator includes an enclosure for containing elements of the system. An AC coupling network coupled to the network simulator implements the functions relating to a particular simulation. A distribution panel connected to a power feed distributes power and includes outgoing circuits and circuit breakers for protecting the outgoing circuits. A plurality of outlets are connected to the breakers of the panel. Through the use of the simulator, with the AC coupling network, simulation of an AC power line network, such as measuring electrical signals, recording electrical signals, simulating electrical signals and inserting electrical signals, can be easily performed. The measured, recorded, simulated and inserted signals correspond to electrical characteristics of elements found in an AC power line network, and can be stored for later analysis. In addition, once simulation information has been stored, it can be reproduced as desired.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: A telecommunications exchange comprises a switching device (1201) of a first type through which telecommunications connections are routed. An access unit (1202) connects the switching device to a telecommunications network. The telecommunications exchange includes an exchange main processor (1200) which generates switch control messages for a switching device of a second type but which translates the switch control messages for use by the switching device of the first type. Preferably, the switching device of the second type is a group switch, and the exchange main processor is an open platform processor. The exchange main processor emulates portions of a telecommunications exchange which control the switching device of the first type the emulated portions including a central processor (1234), regional processors, and a switching subsystem (1230).

Abstract: A method and device for automatically verifying results of a simulation is disclosed. External stimuli are applied to a device under test and observed output is generated in response thereto. The observed output is applied to a non-cycle accurate model of the device comprising procedures which simulate significant events corresponding to the significant events of the observed output. Verification conditions are set according to the aspects of the device under test which are being tested and the verification conditions are applied to the output from the non-cycle accurate model. The verification conditions are associated with a procedure of the model such that the verification condition is verified before or after execution of the procedure. In addition, the verification conditions may be executed at the end of the simulation to ensure that all events which should have occur, have occurred.

Abstract: A dynamic hardware emulation model (10) to be used with a hardware simulator for testing a user device (26) under test. A programming interface (12) controls a memory pool (14) and a command processor/bus manager (16) such that a command cycle is initiated to read and write data through a computer bus (24), to and from the user device (26). The programming interface (12) and the user device (26) can act in a master or slave mode. When the user device (26) is in slave mode, a slave memory (18) contains expected data for comparison purposes, and an arbiter (20) determines which device will have access to the computer bus (24).

Abstract: A method for designing an integrated circuit comprises the step of selecting a system-level parameterized module that performs a specified type of function. The method also includes the steps of specifying values for parameters of the selected system-level module and generating a netlist file from the selected system-level module. In one embodiment, the system-level parameterized module is selected from a family of system-level parameterized modules that each perform a particular function within different parameter ranges.

Abstract: Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost, reliability, and availability goals. The present invention addresses the problem of hardware-software co-synthesis of fault-tolerant real-time heterogeneous distributed embedded systems. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. The reliability and availability of the architecture are evaluated during co-synthesis. On embodiment of the present invention, called COFTA, allows the user to specify multiple types of assertions for each task. It uses the assertion or combination of assertions that achieves the required fault coverage without incurring too much overhead.

Abstract: A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit.

Abstract: An arrangement for designing a testing modeling system provides a testing hierarchy, where non-standard device elements having internal memory and logic structures are modeled by partitioning the device element into a recognizable memory model and a recognizable logic model separate from the memory model. The segregated models are then verified for accuracy using existing design and simulation tool and with comparison to existing hardware implementations. Once the revised models have been verified, the new models can be stored in a model library for future use.

Abstract: A method and system for an automata-based approach to state reachability of an interacting extended finite state machine. The present invention comprises a computer system having a processor, and a memory coupled to the processor via a bus, the memory containing computer readable instructions which when executed by the processor cause the processor to implement a process in accordance with the present invention. A digital system is modeled as an extended finite state machine. Automata operations are applied to the extended finite state machine to efficiently compute a set of reachable states from an initial state. The design of the system is verified by determining whether the set of reachable states includes an undesirable state.

Abstract: A computer system including a memory model of a memory circuit. The computer system comprises a processor coupled to receive and manipulate the memory model, and a memory including the memory model. The memory model includes: a number of address bits corresponding to a number of address bits of the memory circuit; a number of data bits corresponding to a number of data bits of the memory circuit; and a memory type parameter corresponding to a type of the memory circuit.

Abstract: Emulation modules containing an increased number of emulation processors are logically reconfigured into a plurality of planes which are interconnected by means of multiplexors to avoid I/O pinout complexities introduced by the increase in the number of emulation processors. The emulation processors present on an emulation module chip or board are partitioned into a plurality N of different planes or arrays which are interconnected with one another and with off-chip or off-board components via N-way multiplexors. One set of multiplexors provides an input function for each of the planes. Another N-way multiplexor provides output functionality for these same set of planes. An output driver for off-board or chip communication is connected to an N-way output multiplexor. Likewise, an input receiver receives input from off-chip or off-board sources and supplies this signal to all of the N-way multiplexors which provide input signals to the various arrays of emulation processors.