Of Instruction Patents (Class 703/26)
  • Patent number: 11494170
    Abstract: A proxy compiler may be used within a native execution environment to enable execution of non-native instructions from a non-native execution environment as if being performed within the native execution environment. In particular, the proxy compiler coordinates creation of a native executable that is uniquely tied to a particular non-native image at the time of creation of the non-native image. This allows a trusted relationship between the native executable and the non-native image, while avoiding a requirement of compilation/translation of the non-native instructions for execution directly within the native execution environment.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: November 8, 2022
    Assignee: Unisys Corporation
    Inventors: Andrew Ward Beale, Anthony P. Matyok, Clark C. Kogen, David Strong
  • Patent number: 11288361
    Abstract: The disclosed computer-implemented method for restoring applications may include (i) detecting an indication to restore a previous version of an application installed within a mobile operating system environment, (ii) retrieving the previous version of the application from a protected location within the mobile operating system environment where a sandboxing security component stored the previous version of the application, and (iii) executing the previous version of the application within a security sandbox managed by the sandboxing security component. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 29, 2022
    Assignee: NortonLifeLock Inc.
    Inventors: Jonathon Salehpour, Radoslav Stanev, Somard Kruayatidee
  • Patent number: 11231931
    Abstract: A processor includes a first core and a second core to execute computer instructions. Each of the cores includes its own private memory cache and speculative load queue. The speculative load queue stores cachelines for the computer instructions and data when the core is operating in a speculative state with respect to a process or thread. The processor includes a state tracking buffer having a state field to store a speculative exclusive ownership state for each cacheline in the speculative load queue when present therein.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 25, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Sooraj Puthoor
  • Patent number: 11194756
    Abstract: Systems and methods for facilitating interactions with remote memory are disclosed. An observing task can execute in a first environment allocated to a first memory space, and a second memory space can be remote from the observing task. An interposition system proxy can invoke at least one function implemented using an ad hoc polymorphic programming language feature to facilitate requests from the observing task to the second memory space. This can include traversing a data structure for at least one target object, resolving an address in the second memory space based on the traversal, and at least one of reading data from and writing data to the resolved address in the second memory space.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: December 7, 2021
    Assignee: Zentific LLC
    Inventor: Steven Maresca
  • Patent number: 11120106
    Abstract: The present disclosure relates to a system and method for monitoring system calls to an operating system kernel. A performance monitoring unit is used to monitor system calls and to gather information about each system call. The information is gathered upon interrupting the system call and can include system call type, parameters, and information about the calling thread/process, in order to determine whether the system call was generated by malicious software code. Potentially malicious software code is nullified by a malicious code counter-attack module.
    Type: Grant
    Filed: July 30, 2016
    Date of Patent: September 14, 2021
    Assignee: Endgame, Inc.
    Inventor: Matthew D. Spisak
  • Patent number: 11113058
    Abstract: Instructions to be executed by a processing unit that is configured to handle a predefined instruction set are prefetched. A set of instructions in the prefetched instructions to be combined as a macro instruction to be executed by a reconfigurable logic unit is identified. The macro instruction is issued to the reconfigurable logic unit rather than issuing the identified set of instructions to the processing unit.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 7, 2021
    Assignee: Facebook, Inc.
    Inventor: Ahmad Byagowi
  • Patent number: 11099851
    Abstract: Examples of techniques for branch prediction for indirect branch instructions are described herein. An aspect includes detecting a first register setting instruction in an instruction pipeline of a processor, wherein the first register setting instruction stores a target instruction address in a first register of the processor. Another aspect includes looking up the first register setting instruction in a first table. Another aspect includes, based on there being a hit for the first register setting instruction in the first table, determining instruction address data corresponding to a first indirect branch instruction that is associated with the first register setting instruction in a first entry in the first table. Another aspect includes updating a branch prediction for the first indirect branch instruction in a branch prediction logic of the processor based on the target instruction address.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wolfgang Gellerich, Peter M. Held, Gerrit Koch, Martin Schwidefsky
  • Patent number: 11086647
    Abstract: A system configured to emulate a correlithm object processing system, includes a first input node, a second input node, and an output node. The first input node receives a first correlithm object and generates a first amplitude component of a frequency domain signal associated with the first correlithm object. The second input node receives a second correlithm object and generates a first phase component of the frequency domain signal associated with the second correlithm object. The output node receives the first amplitude component and the first phase component and generates a first real-world numeric value comprising the first amplitude component and the first phase component.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 10, 2021
    Assignee: Bank of America Corporation
    Inventor: Patrick N. Lawrence
  • Patent number: 11086908
    Abstract: Computer technology for the provision and use of a computer code based ontology to index a repository of container images (for example, Docker container images). The ontology can then be used as an indexing mechanism to search the repository to find the best container image to use for a given set of needs and/or specifications.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Wagner Lindberg Baccarin Arnaut, Zalkind Lincoln Dantas Rocha
  • Patent number: 11074114
    Abstract: The described system provides one or more processors and memory, coupled to the one or more processors, storing thereon a first OS kernel that receives a system call to access a second OS kernel function from a subsystem of the second OS retransmits the system call to one or more drivers of the first OS, support the subsystem. The system further comprises a subsystem of the second OS, comprising one or more user space components executing natively in a non-privileged mode of the one or more processors, a set of drivers associated with the second OS, the set of support components, and the one or more drivers of the first OS. The one or more drivers of the first OS receive the system call originating from the subsystem, wherein the system call is retransmitted by the first OS kernel and process the system call.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 27, 2021
    Assignee: VIRTUOZZO INTERNATIONAL GMBH
    Inventors: Alexey Kostyushko, Alexey Kobets
  • Patent number: 11010165
    Abstract: A network processor provides for buffer allocation in a manner supporting virtual machines. Each memory allocation request is associated with an aura and a pool, which can be assigned to distinct virtual functions. When parsing a request, lookup tables for the auras and pools are generated and expanded as needed to accommodate any number of concurrent functions. Based on the identified pool of the request, a corresponding stack of pointers is accessed, and a pointer is returned to enable access to the memory.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: May 18, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Wilson P. Snyder, II, Shahe H. Krakirian
  • Patent number: 10970383
    Abstract: In an embodiment, an operating system includes a device manager that is a central repository of device information. Device drivers may communicate with the device manager over respective channels, and may request channel identifiers (Cids) to communicate with resources related to the respective devices. The device manager may provide values for resource access (or handles that the resources may use to access values). In an embodiment, the device drivers do not have the ability to allocate resources for a peripheral device. Accordingly, the security of the system may be increased. Furthermore, the resource allocation may be centrally located, simplifying the process of updating resource allocation when needed. Additionally, the device manager may delay response to requests from a given device driver until its dependencies are clear (e.g. other device drivers and hardware initializations). Thus, startup scripts may be avoided in some embodiments.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 6, 2021
    Assignee: Apple Inc.
    Inventors: Andrew C. Boyd, Denis J. Palmans, Peter H. van der Veen, Stephen J. McPolin, Gilberto Gemin, Stephane Couture, Joseph A. Sarlo
  • Patent number: 10956133
    Abstract: Methods, computer program products, and systems are presented. The methods include, for instance: obtaining a native code having a large number of counters embedded for profiling. Use cases that is serviced by the native code is identified and respective use case profiles representing performance characteristics of a corresponding use case are created. Best predictors identifying one of the use case profiles are determined and variants for a production code is created with only the best predictors instead of the large number of counters. The variants are produced with the use case profiles to to a production environment for performing the use cases.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Geza Geleji, Martin A. Ross, Craig Stirling, Christopher J. Poole, Fiona M. Crowther
  • Patent number: 10896118
    Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ophir Erez, Bodo Hoppe, Divya K. Joshi, Gerrit Koch, Parminder Singh
  • Patent number: 10839628
    Abstract: An access control system for a building or campus includes an access control host and a mobile device. The access control host is configured to interact with one or more physical control panels to monitor and control physical access to one or more locations of the building or campus. The mobile device includes a virtual panel configured to emulate one or more of the physical control panels to the access control host and perform one or more access control functions of the physical control panels. The virtual panel configures the mobile device to operate as a portable control panel in the access control system.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 17, 2020
    Assignee: Johnson Controls Technology Company
    Inventors: Timothy S. Berg, Michael J. Kuzminski, Trivikram R. Ravada, Richard C. Sample, Jonathan L. Polack, David C. Haxton
  • Patent number: 10812362
    Abstract: A client device and method for analysis of a predetermined set of parameters associated with a radio coupling to a WLAN is provided. The client device includes a memory and a radio coupled to at least one processor. The at least one processor executes in the memory a first client Wireless Local Area Network (WLAN) stack having a plurality of layers configured to couple the radio to a WLAN. The at least one processor also executes in the memory a second client WLAN stack emulating the plurality of layers of the first client WLAN stack. The at least one processor is configured to receive, at the second client WLAN stack, data from the plurality of layers of the first client WLAN stack and analyze a predetermined set of WLAN parameters of the client device based on the data received from the plurality of layers of the first client WLAN stack.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: October 20, 2020
    Assignee: Symbol Technologies, LLC
    Inventors: Ohad Shatil, Subramani Rajendiran
  • Patent number: 10776217
    Abstract: Scalable architectures, systems, and services are provided herein for creating manifest-based snapshots in distributed computing environments. In some embodiments, responsive to receiving a request to create a snapshot of a data object, a master node identifies multiple slave nodes on which a data object is stored in the cloud-computing platform and creates a snapshot manifest representing the snapshot of the data object. The snapshot manifest comprises a file including a listing of multiple file names in the snapshot manifest and reference information for locating the multiple files in the distributed database system. The snapshot can be created without disrupting I/O operations, e.g., in an online mode by various region servers as directed by the master node. Additionally, a log roll approach to creating the snapshot is also disclosed in which log files are marked. The replaying of log entries can reduce the probability of causal consistency in the snapshot.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 15, 2020
    Assignee: Cloudera, Inc.
    Inventors: Jonathan Ming-Cyn Hsieh, Matteo Bertozzi
  • Patent number: 10768930
    Abstract: A method provides for decoding, in a microprocessor, an instruction into data identifying a first register, a second register, an immediate value, and an opcode identifier. The opcode identifier is interpreted as indicating that an arithmetic operation is to be performed on the first register and the second register, and that the microprocessor is to perform a change of control operation in response to the addition of the first register and the second register causing overflow or underflow. The change of control operation is to a location in a program determined based on the immediate value. A processor can be provided with a decoder and other supporting circuitry to implement such method. Overflow/underflow can be checked on word boundaries of a double-word operation.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: September 8, 2020
    Assignee: MIPS Tech, LLC
    Inventor: Ranganathan Sudhakar
  • Patent number: 10754732
    Abstract: A storage system may include an interface configured to connect with a mainframe computing system. The interface converts the protocol used by the mainframe computing system to another protocol. Once the data, which may be present in a backup data stream, from the mainframe computing system is converted, the storage system may direct or transmit the backup data stream for further processing such as deduplication and/or compression. The de-duplicated and/or compressed backup data stream is then stored to storage of the storage system.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 25, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Ian Wigmore, Bruce Ferjulian, Stephen Smaldone, Arieh Don
  • Patent number: 10733103
    Abstract: A computer implemented method for managing cache requests includes creating a transient table including records corresponding to one or more participant caches in a system, receiving a new request with respect to an address, wherein the request includes one or more controller actions to be executed, and wherein the request corresponds to one of the one or more participant caches in the system, determining whether an entry exists in the directory table corresponding to the address indicated by the received request, determining whether an entry exists in the transient table for the address indicated by the received request, processing the transient entry indicated by the index in the directory entry to provide a current state of the address indicated by the received request, and appropriating requested controller actions according to the directory table entry, the transient entry, and the received request.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • Patent number: 10698472
    Abstract: A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 30, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Elliot H. Mednick, Edward McLellan
  • Patent number: 10693736
    Abstract: A method for monitoring at least one simulation program includes capturing, by a computer, a plurality of simulation data from the at least one simulation program, the capturing is performed in real time while the at least one simulation program is continuously streaming the plurality of simulation data, analyzing, by the computer, the captured plurality of simulation data using a streaming data software, identifying a plurality of predefined criteria within the analyzed plurality of simulation data, the plurality of predefined criteria includes at least one of an event, a result and a variable, and providing feedback to the at least one simulation program to modify a plurality of simulation parameters according to the at least one identified event, result and variable.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alain E. Biem, Bruce G. Elmegreen, Tayfun Gokmen
  • Patent number: 10671400
    Abstract: A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions; in response to executing an instruction to commit inserted into the plurality of instructions units, incrementally commit a portion of the one or more memory modification instructions that have been atomically executed so far; and subsequent to incrementally committing the portion of the memory modification instructions that have been atomically executed so far, continue atomic execution of the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 2, 2020
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf, Cliff N. Click, Jr.
  • Patent number: 10664287
    Abstract: Disclosed embodiments relate to systems and methods for implementing chained tile operations. In one example, a processor includes fetch circuitry to fetch one or more instructions until a plurality of instructions has been fetched, each instruction to specify source and destination tile operands, decode circuitry to decode the fetched instructions, and execution circuitry, responsive to the decoded instructions, to: identify first and second decoded instructions belonging to a chain of instructions, dynamically select and configure a SIMD path comprising first and second processing engines (PE) to execute the first and second decoded instructions, and set aside the specified destination of the first decoded instruction, and instead route a result of the first decoded instruction from the first PE to be used by the second PE to perform the second decoded instruction.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Alexander F. Heinecke, Robert Valentine, Bret Toll, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 10649787
    Abstract: A data processing system includes exception handling circuitry to detect attempted execution of an exception-triggering processing operation which includes transfer of a data value with a given register of a register bank. Upon detection of such an exception-triggering processing operation, syndrome data is stored within a syndrome register characterising the exception-triggering processing operation with that syndrome data including the data value. The value may be stored into the syndrome register upon occurrence of the exception in the case of an aborting write instruction. The data value may be stored into the syndrome register by emulating code triggered by exception in the case of an aborting read instruction.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: May 12, 2020
    Assignee: ARM Limited
    Inventors: Jason Parker, Richard Roy Grisenthwaite
  • Patent number: 10641609
    Abstract: A route extraction apparatus includes a processor, a position measurement unit that measures a position, and a storage unit. The processor executes storage processing of storing, in the storage unit, a moving history, from a starting position to a current position, measured by the position measurement unit, and route extraction processing of extracting, based on the moving history stored in the storage unit, an actually passed shortest route among a plurality of routes from the current position to the starting position.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 5, 2020
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Masao Sambongi
  • Patent number: 10635452
    Abstract: A vehicle system virtualizing add-on device hardware for a vehicle application. The system includes a computer-readable storage device comprising a client application, middleware components, kernel-space components, and a vehicle application. The client application communicates with an add-on-device server application for virtualizing the add-on-device hardware component at the vehicle. The middleware, in various embodiments, includes an emulated system-call application-program-interface module that receives add-on-device-hardware data from the client application, sends the data to the kernel-space components after processing, and receives the data having been processed at the kernel space. The middleware includes a frameworks-and-abstraction module that receives add-on-device-hardware data, having been processed at the kernel space and the emulated system-call-application-program-interface module and after processing sends the data for use at the vehicle application.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 28, 2020
    Assignee: GM Global Technology Operations LLC
    Inventors: Fan Bai, John Sergakis, Lakshmi V. Thanayankizil, David P. Pop, Xin Yu
  • Patent number: 10635465
    Abstract: Methods and apparatuses relating to preventing the execution of a modified instruction. In one embodiment, an apparatus includes a hardware binary translator to translate an instruction to a translated instruction, and a consistency hardware manager to prevent execution of the translated instruction by a hardware processor on detection of a modification to a virtual to physical address mapping of the instruction after the translation.
    Type: Grant
    Filed: March 28, 2015
    Date of Patent: April 28, 2020
    Assignee: INTEL CORPORATION
    Inventors: Polychronis Xekalakis, Jamison D. Collins, Jason M. Agron
  • Patent number: 10586047
    Abstract: Securely sending a complete initialization package in one example implementation can include adding a resource identifier that includes a mapping of a driver to a hardware component included in a physical machine hosting VMs to an initial random-access memory (RAM) file system (INITRAMFS) stored in memory of the physical machine to form a complete initialization package, sending the complete initialization package from read-only memory (ROM) of the physical machine to a location in RAM of the physical machine accessible by a hypervisor, and authenticating that the complete initialization package is secure.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: March 10, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Richard A. Bramley, Jr.
  • Patent number: 10579753
    Abstract: A method implemented by a data processing system for processing data items of a stream of data items, including: accessing a specification that represents the executable logic, wherein a state of the specification for a particular value of the key specifies one or more portions of the executable logic that are executable in that state; receiving, over an input device or port, data items of a stream of data; for a first one of the data items of the stream, identifying a first state of the specification for a value of the key associated with that first one of the data items; processing, by the data processing system, the first one of the data items according to one or more portions of executable logic that are represented in the specification as being associated with the first state.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 3, 2020
    Assignee: Ab Initio Technology LLC
    Inventors: Joel Gould, Scott Studer, Craig W. Stanfill
  • Patent number: 10559055
    Abstract: A programmable execution unit of a graphics processor that executes program instructions to perform graphics shading operations can use at least two different register file mapping configurations for mapping registers to execution threads. When a shader program is to be executed, how the shader program will use the registers is considered and the register file mapping configuration to use for the shader program is then selected based on the assessment of the register use by the shader program. Appropriate state information is then set to cause the threads being executed by the programmable execution unit to use the registers according to the selected register file mapping configuration when executing the shader program.
    Type: Grant
    Filed: July 23, 2016
    Date of Patent: February 11, 2020
    Assignee: Arm Limited
    Inventor: Jorn Nystad
  • Patent number: 10514926
    Abstract: A microprocessor implemented method for performing early dependency resolution and data forwarding is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each current guest branch instruction in the native address space fetched during execution, performing (a) determining a youngest prior guest branch target stored in a guest branch target register, wherein the guest branch register is operable to speculatively store a plurality of prior guest branch targets corresponding to prior guest branch instructions; (b) determining a current branch target for a respective current guest branch instruction by adding an offset value for the respective current guest branch instruction to the youngest prior guest branch target; and (c) creating an entry in the guest branch target register for the current branch target.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: December 24, 2019
    Assignee: INTEL CORPORATION
    Inventor: Mohammad A. Abdallah
  • Patent number: 10509877
    Abstract: Systems, methods, and products having pipelined inputs to and outputs from an emulator are disclosed. Using a pipeline may allow the round trip cable delay (RTCD) to be spread across two or more clock cycles. In an embodiment, an emulation system may store input data received from a target device during a first clock cycle at a target timing domain interfacing component (TTD), and transmit the stored input data during a second clock cycle after the first clock cycle. In another embodiment, the emulation system may delay transmitting the input data received at the TTD during the first clock cycle such that that the input data reaches the emulator at a predetermined time during the second clock cycle. As the RTCD is spread across multiple clock cycles, the emulation system may implement faster clocks.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 17, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Viktor Salitrennik, Gavin Zawalski
  • Patent number: 10509707
    Abstract: Described are techniques for mirroring data that may include issuing, by an application on a host, a write operation that writes first data to a primary storage entity having data stored in accordance with a first format and first structure; intercepting, on the host, the write operation; and performing, on the host, first processing to process the write operation. The first processing may include: sending the write operation to a data storage system including the primary storage entity; determining whether the primary storage entity is mirrored as a second storage entity having data stored in a second format and second structure different from the first format and first structure; and responsive to determining the primary storage entity is mirrored as the second storage entity, issuing one or more second write operations to mirror the first data on the second storage entity in accordance with the second format and second structure.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 17, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Paul A. Linstead
  • Patent number: 10445928
    Abstract: A system and method for generating a high-density three-dimensional (3D) map are disclosed. The system comprises acquiring at least one high density image of a scene using at least one passive sensor; acquiring at least one new set of distance measurements of the scene using at least one active sensor; acquiring a previously generated 3D map of the scene comprising a previous set of distance measurements; merging the at least one new set of distance measurements with the previous set of upsampled distance measurements, wherein merging the at least one new set of distance measurements further includes accounting for a motion transformation between a previous high-density image frame and the acquired high density image and the acquired distance measurements; and overlaying the new set of distance measurements on the high-density image via an upsampling interpolation, creating an output 3D map.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: October 15, 2019
    Assignee: VAYAVISION LTD.
    Inventors: Youval Nehmadi, Shmuel Mangan, Shahar Ben-Ezra, Anna Cohen, Ronny Cohen, Lev Goldentouch, Shmuel Ur
  • Patent number: 10437998
    Abstract: A combination of hardware monitoring and binary translation software allow detection of return-oriented programming (ROP) exploits with low overhead and low false positive rates. Embodiments may use various forms of hardware to detect ROP exploits and indicate the presence of an anomaly to a device driver, which may collect data and pass the indication of the anomaly to the binary translation software to instrument the application code and determine whether an ROP exploit has been detected. Upon detection of the ROP exploit, the binary translation software may indicate the ROP exploit to an anti-malware software, which may take further remedial action as desired.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: October 8, 2019
    Assignee: McAfee, LLC
    Inventors: Palanivelrajan Rajan Shanmugavelayutham, Koichi Yamada, Vadim Sukhomlinov, Igor Muttik, Oleksandr Bazhaniuk, Yuriy Bulygin, Dmitri Dima Rubakha, Jennifer Eligius Mankin, Carl D. Woodward, Sevin F. Varoglu, Dima Mirkin, Alex Nayshtut
  • Patent number: 10432459
    Abstract: A method for the automatic configuration of portable terminals, comprises the steps of detecting the geographical position of at least two portable terminals (T1-T7) and configuring said at least two portable terminals (T1-T7) on the basis of the respective geographical position which has been detected. The configuration of said at least two portable terminals (T1-T7) comprises: configuring at least one first terminal (T1; T7) with predetermined configuration parameters selected on the basis of the respective geographical position, detecting a condition of geographical proximity of at least one second terminal (T2-T6) with respect to said at least one first terminal (T1; T7) and at least partially cloning said at least one first terminal (T1; T7) into said at least one second terminal (T2-T6).
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: October 1, 2019
    Assignee: DATALOGIC IP TECH, S.R.L.
    Inventors: Marco Guerrero, Stefano Amorosi, Elva Martinez-Ballesteros
  • Patent number: 10425279
    Abstract: Example methods are provided for a network management entity to implement distributed network emulation in a virtualized computing environment. The method may comprise: generating a translated network emulation rule by translating a source identifier and a destination identifier in a network emulation rule to respective source network address and destination network address, and configuring a source host or destination host to apply the translated network emulation rule to emulate a desired network condition for one or more first packets from the source network address to the destination network address. The method may further comprise: in response to detecting that the source network address or destination network address has been updated, updating the source network address or destination network address in the translated network emulation rule; and reconfiguring the source host or destination host to apply the updated translated network emulation rule.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 24, 2019
    Assignee: NICIRA, INC.
    Inventors: Ziyou Wang, Hua Wang, Jianjun Shen, Donghai Han
  • Patent number: 10372622
    Abstract: Mechanisms are provided, in a data processing system having a processor and a cache subsystem, for providing software controlled cache segmentation and cache segment utilization. The mechanisms segment a cache memory of the cache subsystem such that the cache memory comprises a plurality of cache segments. Each cache segment in the plurality of cache segments is associated with a different data property of data stored in the cache segment. The mechanisms configure software executing on the data processing system to direct cache accesses to one of the cache segments based on a corresponding data property of the cache accesses by the software. The mechanisms process, by the processor, a data access operation from software executing on the processor, based on an identifier of a cache segment in one of an effective address provided by the software or a page table entry corresponding to the effective address provided by the software.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventor: Shajith Chandran
  • Patent number: 10362053
    Abstract: A computer security threat sharing technology is described. A computer security threat is recognized at an organization. A partner network graph is queried for security nodes connected to a first security node representing the organization. The first security node is connected to at least a second security node representing a trusted security partner of the organization. The second security node is associated with identification information. The computer security threat recognized by the organization is communicated to the trusted security partner using the identification information associated with the second security node.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 23, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas Charles Stickle, Carl Jay Moses, Ryan Christopher Holland
  • Patent number: 10339533
    Abstract: At least some of the illustrative embodiments are methods including: executing a test program on a computer system coupled to a server, the test program emulating virtual users by instantiating a first user instance by calling a first reentrant function, the first user instance exiting the first reentrant function upon encountering a blocking statement in the first reentrant function; instantiating a second user instance by calling the first reentrant function, the second user instance exiting the first reentrant function upon encountering a blocking statement in the first callable function; reentering the first user instance by again calling the first reentrant function, the first reentrant function resuming execution within the reentrant function after the first blocking statement; and reentering the second user instance by calling the first reentrant function, the first reentrant function resuming execution within the reentrant function after the second blocking statement.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: July 2, 2019
    Assignee: Spirent Communications, Inc.
    Inventor: Jin J. Qian
  • Patent number: 10338943
    Abstract: Computer-implemented systems, methods, and media are provided for emulating microprocessor instructions. The computer-implemented systems, methods, and media may, for example, identify an instruction of a first software application using a second software application that emulates instructions of a type of microprocessor, add an additional bit to a length of an operation code of the instruction to create an extended operation code, wherein the extended operation code is represented in an operation code table of the second software application, and emulate execution of the instruction using the second software application and the extended operation code.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: July 2, 2019
    Assignee: SYMANTEC CORPORATION
    Inventors: Mircea Ciubotariu, Costin Ionescu
  • Patent number: 10318292
    Abstract: Systems and methods may process a single atomic operation. An instruction set may be generated to replace a plurality of atomic operations with a single atomic operation. The instruction set may include an accumulation instruction to compute a prefix sum for a plurality of initial values associated with a plurality of processing lanes to generate a plurality of accumulated values. The instruction set may also include a broadcast instruction to return a pre-existing value to be added with each of the plurality of accumulated values to generate a plurality of intermediate accumulated values. In one example, a graphics processor may execute the instruction set to process the single atomic operation.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Satyajit Sarangi, Thomas F. Raoux, Guei-Yuan Lueh, Subramaniam Maiyuran
  • Patent number: 10310854
    Abstract: A compute instruction to be executed is to use a memory operand in a computation. An address associated with the memory operand is to be used to locate a portion of memory from which data is to be obtained and placed in the memory operand. A determination is made as to whether the portion of memory extends across a specified memory boundary. Based on the portion of memory extending across the specified memory boundary, the portion of memory includes a plurality of memory units and a check is made as to whether at least one specified memory unit is accessible and whether at least one specified memory unit is inaccessible.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Brett Olsson
  • Patent number: 10310840
    Abstract: Provided is a computer system capable of managing the performance of processing upon transmitting software to terminals. The present invention is a computer system comprising a plurality of modules which sequentially execute processing up to transmitting the software to the terminal, a controller which collects an operation log of each of the plurality of modules, and a memory which stores the operation logs collected by the controller, wherein the controller generates an operating performance of a prescribed module among the plurality of modules based on the operation logs stored in the memory.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 4, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Soki Sakurai, Atsushi Katou, Noboru Kiyama, Hiroshi Mine
  • Patent number: 10268462
    Abstract: An emulation device 3 includes a storage unit 70 which stores information in which instruction information 710 including a type of an instruction 711 and an operand 712 included in emulation-execution-target-software 71, compiled instruction information 72 obtained by compiling the instruction information 710 capable of being emulated, and information 73 indicating a storage address of the compiled instruction information 72 are associated with, and a generation unit 80 which generates compiled software 81 that is compiled for the emulation-execution-target-software 71 capable of being emulated by converting the instruction information 710 into the subroutine-read-instruction-information which calls the compiled instruction information 72 associated with the instruction information 710 from the storage address.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: April 23, 2019
    Assignee: NEC PLATFORMS, LTD.
    Inventor: Dai Kunugi
  • Patent number: 10228950
    Abstract: A microprocessor implemented method for maintaining a guest return address stack in an out-of-order microprocessor pipeline is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each function call instruction in the native address space fetched during execution, the method also comprises performing the following: (a) pushing a current entry into a guest return address stack (GRAS) responsive to a function call, wherein the GRAS is maintained at the fetch stage of the pipeline, and wherein the current entry comprises information regarding both a guest target return address and a corresponding native target return address associated with the function call; (b) popping the current entry from the GRAS in response to processing a return instruction; and (c) fetching instructions from the native target return address in the current entry after the popping from the GRAS.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventor: Mohammad A. Abdallah
  • Patent number: 10223141
    Abstract: A system is provided for monitoring, regenerating and replacing the code of running applications with semantically equivalent, specialized code versions that reflect the demands of the execution environment. The system includes a co-designed compiler and runtime system that virtualizes a selected set of edges in a host program, where these edges provide hooks through which the runtime system may redirect execution into an intermediate representation utilized to optimize introspective and extrospective processes.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: March 5, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Jason Mars, Michael Laurenzano, Lingjia Tang
  • Patent number: 10223148
    Abstract: Full virtual machine (VM) functionality in one example implementation can include sending a complete initialization package to a location in memory of a machine accessible by a hypervisor and generating a VM capable of providing a respective full functionality of a hardware component in the machine.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: March 5, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Richard A. Bramley, Jr.
  • Patent number: 10216514
    Abstract: Examples herein disclose receiving a first topology map that is to describe a desired software configuration for at least one of multiple components in a system. The examples disclose accessing a second topology map that is to describe a current software configuration for at least one of the multiple components in the system. The examples determine based on the first topology map and the second topology map whether the desired software configuration differs from the current software configuration. Responsive to the determination that the desired software configuration differs from the current software configuration, the examples identify which at least one of the multiple components to upgrade.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: February 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Lyle Eric Wilkinson