Abstract: A compute instruction to be executed is to use a memory operand in a computation. An address associated with the memory operand is to be used to locate a portion of memory from which data is to be obtained and placed in the memory operand. A determination is made as to whether the portion of memory extends across a specified memory boundary. Based on the portion of memory extending across the specified memory boundary, the portion of memory includes a plurality of memory units and a check is made as to whether at least one specified memory unit is accessible and whether at least one specified memory unit is inaccessible.

Abstract: An emulation device 3 includes a storage unit 70 which stores information in which instruction information 710 including a type of an instruction 711 and an operand 712 included in emulation-execution-target-software 71, compiled instruction information 72 obtained by compiling the instruction information 710 capable of being emulated, and information 73 indicating a storage address of the compiled instruction information 72 are associated with, and a generation unit 80 which generates compiled software 81 that is compiled for the emulation-execution-target-software 71 capable of being emulated by converting the instruction information 710 into the subroutine-read-instruction-information which calls the compiled instruction information 72 associated with the instruction information 710 from the storage address.

Abstract: A microprocessor implemented method for maintaining a guest return address stack in an out-of-order microprocessor pipeline is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each function call instruction in the native address space fetched during execution, the method also comprises performing the following: (a) pushing a current entry into a guest return address stack (GRAS) responsive to a function call, wherein the GRAS is maintained at the fetch stage of the pipeline, and wherein the current entry comprises information regarding both a guest target return address and a corresponding native target return address associated with the function call; (b) popping the current entry from the GRAS in response to processing a return instruction; and (c) fetching instructions from the native target return address in the current entry after the popping from the GRAS.

Abstract: A system is provided for monitoring, regenerating and replacing the code of running applications with semantically equivalent, specialized code versions that reflect the demands of the execution environment. The system includes a co-designed compiler and runtime system that virtualizes a selected set of edges in a host program, where these edges provide hooks through which the runtime system may redirect execution into an intermediate representation utilized to optimize introspective and extrospective processes.

Abstract: Full virtual machine (VM) functionality in one example implementation can include sending a complete initialization package to a location in memory of a machine accessible by a hypervisor and generating a VM capable of providing a respective full functionality of a hardware component in the machine.

Abstract: Examples herein disclose receiving a first topology map that is to describe a desired software configuration for at least one of multiple components in a system. The examples disclose accessing a second topology map that is to describe a current software configuration for at least one of the multiple components in the system. The examples determine based on the first topology map and the second topology map whether the desired software configuration differs from the current software configuration. Responsive to the determination that the desired software configuration differs from the current software configuration, the examples identify which at least one of the multiple components to upgrade.

Abstract: A system, method and computer program product for implementing a thin hypervisor. The thin hypervisor does not have any direct association with a VM. The thin hypervisor serves as a wrapper over hardware capabilities of a processor. The processor has privileged low-level capabilities EPT VTX, AMD V and the ARM has virtualization technology. In order to use processor hardware capabilities and receiving root privileges, the system operates in a “super user” mode. The VM operates in a VM environment with kernel privileges in a user mode. A super user space is created in a safe mode. A user space application (or a process) is created. A user space virtualization framework library is used. These entities may be separated by a user space and a kernel (OS) space. A thin hypervisor is implemented in the user space.

Abstract: A crop modeling system includes an irrigation system and a user input device coupled to the irrigation system. The irrigation system and the user input device are configured to communicate with a processor and non-transitory memory storing executable instructions. The executable instructions are configured to cause the processor to open a crop modeling graphical user interface for a geospatial location of a field associated with the irrigation system, move a crop graphical user interface element to a mapped location on the crop modeling graphical user interface responsive to one or more user inputs received via the user input device, generate an in-season crop model by applying the one or more user inputs to the crop model via the moving of the crop graphical user interface element, and generate one or more control signals based on the in-season crop model.

Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.

Abstract: A simulation device being a “host” simulates execution of a program in a “guest” using a cache for reading instructions in the program. In the simulation device, an execution unit executes instructions described in host code stored in a buffer. When host code wherein a next instruction being an instruction to be executed by the execution unit next is described is not stored in the buffer, a processing unit reads from a storage medium a guest code group with a size of a cache line, including guest code wherein the next instruction is described, converts the guest code group read, generates a host code group including the host code wherein the next instruction is described, and collectively writes the host code group generated, as a host code block, in the buffer.

Abstract: A method for selecting at least one communication channel based on a plurality of communication channel characteristics is provided. The method may include receiving a plurality of communications. The method may further include separating the received plurality of communications into a plurality of units. Additionally, the method may include categorizing the plurality of units based on a number of commands associated with the plurality of units. The method may also include measuring a plurality of communication channels based on the categorized plurality of units, the number of commands, and the plurality of communication channel characteristics. The method may further include selecting the at least one communication channel associated with the measured plurality of communication channels to process at least one unit associated with the categorized plurality of units.

Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

Abstract: Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.

Abstract: An apparatus may include a printed circuit board, an integrated circuit mounted on a first surface of the printed circuit board, and one or more vias that extend through the printed circuit board from the first surface to a second surface of the printed circuit board to provide electrical connectivity for the integrated circuit. The second surface of the printed circuit board may be opposite the first surface of the printed circuit board. The apparatus may include a pin header that mechanically supports one or more pins that provide electrical connectivity for the integrated circuit. The pin header may be mounted to the second surface of the printed circuit board to mate the one or more pins with the one or more vias to provide electrical connectivity for the integrated circuit.

Abstract: Data collection management is disclosed. A data collection configuration is obtained. The data collection configuration is translated into executable code in a language usable to collect data. Data is collected using the executable code. The collected data values are provided as output. Metrics management is also disclosed. A configuration of a metric is obtained. The metric configuration includes a definition of how computation of the metric is to be performed and a mapping between a computation input and collected data. Collected data values are obtained based at least in part on the mapping. Metric values are computed according to the definition. One or more results associated with the computed metric values are stored.

Abstract: A computer system firmware is provided that includes functionality for using a system management mode (SMM) to efficiently boot to a secondary operating system prior to booting to a primary operating system. The SMM is utilized to store data describing the state of the computer system at a point just prior to booting the secondary operating system. This data is used following execution of the secondary operating system to restore the system to the same state that it was in prior to executing the secondary operating system. Execution can then be continued at a location just following the location at which the secondary operating system was booted in order to execute a primary operating system.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more translation caches, where operation includes: determining, at the load/store slice, a real address from a cache hit in the translation cache for an effective address for an instruction received at a load/store slice; determining, at the load/store slice, an error condition corresponding to an access of the real address; determining, at the load/store slice, a process type indicating a source of the instruction to be a guest process; and responsive to determining the error condition, initiating, in dependence upon the process type indicating a source of the instruction to be a guest process, an effective address translation corresponding to a cache miss in the translation cache for the effective address for the instruction.

Abstract: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.

Abstract: Systems and techniques for network on a chip based computer architectures and communications therein are described. A described technique includes generating, at a first computing resource of a computer system, a chained packet sequence. A packet therein can specify a chain indicator to indicate inclusion in the chained packet sequence, a destination address, and an opcode. The technique includes routing the sequence to a second computing resource based on the destination address of a first chained packet in the sequence. The technique includes receiving the sequence at the second computing resource; performing the operation specified by the opcode of the first chained packet; and determining whether to process or forward one or more chained packets in a remainder portion of the sequence based on the destination address of a second chained packet of the sequence, the second chained packet being located at a beginning of the remainder portion.

Abstract: An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request.

Abstract: The disclosed embodiments include a method for retroactively analyzing original input content to detect malicious content in a computer system, in which the original input content has been previously processed to generate modified input content and prevented from being received by an intended recipient. The method includes accessing the original input content or a characteristic associated with the original input content, and analyzing it based on a malware detection algorithm to determine whether the original input content includes suspected malicious content, wherein the malware detection algorithm includes at least one update of a signature or behavioral characteristic that was not included in the malware detection algorithm when the modified input content was generated. When it is determined that the original input content includes suspected malicious content, the method includes analyzing the modified input content to determine whether the modified input content includes the suspected malicious content.

Abstract: An information providing apparatus caches, based on a number of reservation remains which is periodically acquired from a management apparatus managing numbers of reservation remains of services, a number of remains of a reservation target in a cache means for each reservation target identified by a combination of a service and a time of providing the service; estimates, for each of a plurality of reservation targets corresponding to a request of a user, a probability that information related to a reservation target is browsed by the user; acquires the number of remains of a reservation target where the probability is greater than or equal to a threshold value from the management apparatus and acquires the number of remains of a reservation target where the probability is smaller than the threshold value from the cache means; and provides a state of remains of each of the plurality of reservation targets, the state of remains corresponding to the number of remains.

Abstract: A hypervisor of a host receives an indication of an exit from a guest to the hypervisor and a memory-mapped input output (MMIO) address that caused the exit to hypervisor. The hypervisor walks a page table of the guest to identify a guest address associated with the MMIO address that caused the exit to the hypervisor. The hypervisor decodes an instruction of the guest referenced by the guest address to determine a type of operation that the guest intended to execute and a location of MMIO information. The hypervisor records, in a page table entry for the MMIO address of a host page table, an association with the type of operation and the location of the MMIO information. The hypervisor executes the operation on behalf of the guest based on the type of the operation and the MMIO information.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: A system for collaborating on a component according to an exemplary aspect of the present disclosure includes, among other things, a computing device configured to execute an editing module. The editing module is configured to generate at least one developed feature of the component design in response to executing at least one global command relating to a multi-user CAx command set, and to generate at least one undeveloped feature of the component design in response to executing at least one local command relating to a local CAx command set.

Abstract: A method for proactively detecting shared libraries suspected of association with malware includes the steps of determining one or more shared libraries loaded on an electronic device, determining that one or more of the shared libraries include suspicious shared libraries by determining that the shared library is associated with indications that the shared library may have been maliciously injected, loaded, and/or operating on the electronic device, and identifying the suspicious shared libraries to a reputation server.

Abstract: A method for executing Android apps nativelyon any environment comprises converting one or more Android applications to a binary format of other applications in the Host Operating System. The Android applications are in one of a source format and a binary format. Further, all equivalent components are replaced from a standard Android environment with ones provided by the Host OS using the Host Operating System's capabilities. Furthermore, Android applications are executed natively by a Host Operating System. Moreover, the method includes mixing Android generated with content created by the Host Operating System to generate a final screen and the user views and interacts with the final screen.

Abstract: A simulating method for a flash memory and a simulator using the simulating method are provided. The simulator is configured to couple to a memory controller. The simulating method includes: setting a predetermined response condition; providing multiple command sets, wherein each of the command sets corresponds to a memory type; receiving a first command from the memory controller; identifying a second command in the command sets according to the first command; determining if the second command matches the predetermined response condition; obtaining a first signal corresponding to the second command according to the predetermined response condition; and, transmitting the first signal to the memory controller. Accordingly, the usage of the simulator is flexible.

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: A method for managing a variable caching structure for managing storage for a processor. The method includes using a multi-way tag array to store a plurality of pointers for a corresponding plurality of different size groups of physical storage of a storage stack, wherein the pointers indicate guest addresses that have corresponding converted native addresses stored within the storage stack, and allocating a group of storage blocks of the storage stack, wherein the size of the allocation is in accordance with a corresponding size of one of the plurality of different size groups. Upon a hit on the tag, a corresponding entry is accessed to retrieve a pointer that indicates where in the storage stack a corresponding group of storage blocks of converted native instructions reside. The converted native instructions are then fetched from the storage stack for execution.

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract: A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.

Abstract: An optimizer identifies application code to be modified and modifies that code, such that the application includes unmodified code and modified code. Based on generating the modified code, the optimizer sets one or more controls to selectively enable use of extended mode features by the application. The extended mode features include one or more features at an instruction set level different from an instruction set level available to the application. The controls may be set in a control register or entries of address translation structures, as examples.

Abstract: An optimizer identifies application code to be modified and modifies that code, such that the application includes unmodified code and modified code. Based on generating the modified code, the optimizer sets one or more controls to selectively enable use of extended mode features by the application. The extended mode features include one or more features at an instruction set level different from an instruction set level available to the application. The controls may be set in a control register or entries of address translation structures, as examples.

Abstract: An application server for generating project specific configuration data, the application server having a processor, a memory device coupled to the processor for storing digital data and an interface coupled to the processor for sending and receiving data across a data network. The processor is adapted to receive and store project template data, receive and store question configuration data representing at least one question and at least one associated candidate answer and receive and store rule data representing a rule relating the project template data and the question configuration data. The processor being further adapted to send question data from the question configuration data and receive, answer data in response to the question data and generate project specific configuration data from the project template data based on the answer data and rule data.

Abstract: Embodiments of techniques and systems for execution of code with multiple page tables are described. In embodiments, a heterogenous system utilizing multiple processors may use multiple page tables to selectively execute appropriate ones of different versions of executable code. The system may be configured to support use of function pointers to virtual memory addresses. In embodiments, a virtual memory address may be mapped, such as during a code fetch. In embodiments, when a processor seeks to perform a code fetch using the function pointer, a page table associated with the processor may be used to translate the virtual memory address to a physical memory address where code executable by the processor may be found. Usage of multiple page tables may allow the system to support function pointers while utilizing only one virtual memory address for each function that is pointed to. Other embodiments may be described and claimed.

Abstract: A method for managing a variable caching structure for managing storage for a processor. The method includes using a multi-way tag array to store a plurality of pointers for a corresponding plurality of different size groups of physical storage of a storage stack, wherein the pointers indicate guest addresses that have corresponding converted native addresses stored within the storage stack, and allocating a group of storage blocks of the storage stack, wherein the size of the allocation is in accordance with a corresponding size of one of the plurality of different size groups. Upon a hit on the tag, a corresponding entry is accessed to retrieve a pointer that indicates where in the storage stack a corresponding group of storage blocks of converted native instructions reside. The converted native instructions are then fetched from the storage stack for execution.

Abstract: According to one embodiment of the invention, a computerized method is described for improved efficiency in malware detection. The method comprises detecting a system call initiated by a virtual machine and determining a class assigned to the detected system call. In response to determining that the system call is associated with a first class of system calls, providing information associated with the system call to virtualized device hardware. In contrast, in response to determining that the system call is associated with a second class of system calls, which is different from the first class of system calls, the virtual machine resumes virtual processing of an object without providing information to the virtualized device hardware.

Abstract: A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.

Abstract: A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias. The compiler uses a code generation endian preference that is specified by the user, and that determines a natural element order. When the compiler processes a computer program, it generates instructions for vector operations by determining whether the vector instruction has an endian bias that matches the specified endian preference (i.e., the inherent element order of the vector instruction matches the natural element order). When the vector instruction has no endian bias, or when the endian bias of the vector instruction matches the specified endian preference, the compiler generates one or more instructions for the vector instruction as it normally does.

Abstract: A management system manages a storage system and a server computer. The management system (A) acquires the storage level pool information that includes the information of a capacity of a storage level pool from the storage system, (B) acquires the server level pool information that includes the information of a capacity of a server level pool from the server computer, (C) determines a first risk degree that indicate a risk of a depletion of a free capacity of the storage level pool based on the storage level pool information, (D) determines a second risk degree that indicate a risk of a depletion of a free capacity of a server level pool based on the server level pool information, and (E) displays the information that is associated with the first risk degree that indicate a risk of a depletion of a free capacity of the storage level pool and the second risk degree that indicate a risk of a depletion of a free capacity of the server level pool.

Abstract: Methods and apparatus for the flexible provision of control data within large data structures. In one exemplary embodiment, DisplayPort is modified from its existing 8B/10B line coding to 128B/130B (or 128B/132B). In one embodiment, the 128B/130B (or 128B/132B) block includes: sixteen (16) eight (8) bit command or data symbols and a two (2) bit (or four (4) bit) synchronization header. The synchronization header may provide a fixed reference to the next command symbol (for example, the symbol immediately following the synchronization header). In one variant, each command symbol is split into a first and a second portion, where the first portion identifies a control function (control symbol), and the second portion provides a reference to the next command symbol.

Abstract: A distributed report processing system. The system includes a management server and a queue server in communication with the management server. The system also includes a plurality of report generators in communication with the management server and the queue server.

Abstract: In accordance with an embodiment, a method of operating a processor includes operating in a first operating mode that prohibits access to a protected memory area, receiving a priority interrupt (PI) signal, operating in a second operating mode in response to receiving the PI signal, and executing a first routine by asserting a semi-privileged interrupt (SPI). Access to the protected memory area is permitted in the second operating mode, and the first routine operates in the second operating mode and is interruptible by the PI signal.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes intercepting a processor request to apply the lock on the object, identifying a performance history of the object based on a number of instances of contention, reducing computing resources of the processor by, when the number of instances is below a threshold value, generating a lock bypass for the object to cause speculative execution of target code within the object, and preventing speculative execution by applying the lock on the object when the number of instances is above the threshold value.

Abstract: A method and apparatus for signature-based detection of kernel data structure modification are disclosed. In the method and apparatus a signature is generated for a kernel data structure, whereby the kernel data structure is capable of being modified based at least in part on access to the kernel data structure. The signature is also updated as a result of access to the kernel data structure due at least in part to one or more identified instructions being executed. The signature is used to determine whether the kernel data structure is accessed by one or more other instructions.