Abstract: Software managing long names in an application programming interface receives a request to perform a requested operation on one or more fields, the application comprising a first operation operable to perform the requested operation on at least one field type. The software determines whether the field type of any of the fields is incompatible with the first operation. If the field types of the one or more fields are compatible with the first operation, then the software performs the requested operation on the one or more fields using the first operation. If the software determines that the field type of at least one of the fields is incompatible with the first operation, then it converts the request into a call for a second operation operable to perform the requested operation on the one or more fields and performs the requested operation using the second operation.

Abstract: Systems and methods are provided for concurrently emulating multiple channel impairments. The systems and methods may include storing a plurality of channel impairment profiles, where each channel impairment profile corresponds to a respective channel impairment type; receiving a selection of two or more of the plurality of channel profiles; generating a composite impairment profile by combining the selected two or more channel profiles, the composite profile specifying time-variant impairments, the composite profile reflecting a combination of the respective impairment types of the selected channel profiles; and applying the time-variant impairments specified by the composite profile to an input real-time data stream to generate an impaired real-time data stream, where a timing of the application of the time-variant impairments is based at least in part upon timing data from a real-time clock.

Abstract: A system and method for translating, synthesizing and acting upon disparate event sets is provided. The disclosed cross-platform event engine comprises an event module with information pertaining to various event inputs as they relate to different operating platforms and devices. Logic utilized by the cross-platform event engine determines how to handle a particular event within an operating environment. Methods of updating and training the engine are also provided.

Abstract: Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is emulated to generate a first set of emulated instructions that emulate a first component on the host system. A second set of code instructions is emulated to generate a second set of emulated instructions that emulate a second component of the target system on the host system. The first set is executed based on a first clock (which may be a fixed clock) and the second set is executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the first or second sets of instructions or a memory access to maintain a desired synchronization between the first and second sets of instructions.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

Abstract: A non-native, multi-modal compiler and an emulated computing environment for use in a native computing environment. The multi-modal compiler includes a parser configured to parse or divide received source code into a plurality of token elements, whereby at least one statement is recognized from a collection of token elements. The multi-modal compiler also includes a code emitter configured to emit machine code to implement the at least one statement, whereby the emitted machine code is compiled multi-modal object code that includes non-native operators (e.g., E-Mode operators) and NATV operators. The compiled multi-modal object code is configured in such a way that when translated by a code translation unit, the compiled multi-modal object code generates a merged codefile having translated native code segments corresponding to the non-native operators and native code segments corresponding to the NATV operators. The merged codefile is executable by a native processor in the native computing environment.

Abstract: An emulation system that provides the functionality of an emulated computer on a host computer pre-processes the object code file to be emulated to reduce the run-time overhead due to parsing the object code. The emulator uses pre-programmed functions that model each instruction of the emulated computer. An object code file is pre-parsed to generate a translated file which includes a sequence of function calls corresponding to the sequence of instructions in the code file. The translated file is compiled to generate a corresponding translated object-code file. The translated object-code file is executed in the emulation environment on the host computer. The emulation system also includes a standard mode in which the object code file is emulated by sequentially parsing each instruction in the object code file and invoking an appropriate one of the preprogrammed functions in the emulated environment.

Abstract: A management apparatus includes a management unit configured to manage information associating each of a plurality of image processing apparatuses constituting a virtual device with a function executed by the each of the plurality of image processing apparatuses, a control unit configured to provide a display for setting a virtual device as a transmission destination of transmission data, an identification unit configured, if a virtual device is set as the transmission destination of the transmission data, to identify an image processing apparatus that executes a function corresponding to a type of the transmission data from among the plurality of image processing apparatuses constituting the set virtual device based on the information managed by the management unit, and a transmission unit configured to transmit the transmission data to the image processing apparatus identified by the identification unit.

Abstract: An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that do not require a call to operating system services. The facility includes an instruction that determines elapsed time and reports it to the user as a single unit of operation.

Abstract: The composition of a data-driven analytics model that includes at least an analytical modeling component that defines analytical relationships between the model parameters using multiple analytical relations. The analytical modeling component uses the analytical relations to identify which of the model parameters are known and which are unknown, and solves for the identified unknown model parameter(s). The analytics modeling component also includes an analytics taxonomy in which the analytical relations are categorized into related analytics categories. Navigation through the analytics taxonomy assists in the composition of an analytics model. The analytics taxonomy may, but need not, be domain specific.

Abstract: Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.

Abstract: A hypervisor environment configured for accelerated access to device emulators comprises a hypervisor that intercepts a device access instruction to a child partition processor and routes said device access instruction to a root partition. A processor instruction emulator emulates said device access instruction along with any number of next instructions of the processor in said child partition, thereby dispatching accesses to a device emulator on behalf of the processor in said child partition. By emulating these instructions in the root partition, accesses to the device emulator are greatly accelerated.

Abstract: A method for simulating a hardware failure in a virtualization environment includes determining a location of an instruction pointer for a particular operating system operating in the virtualization environment; determining an address of a memory location containing an invalid instruction; and writing the address of the memory location containing the invalid instruction in the location of the instruction pointer.

Abstract: Emulation of a target system with a host system is disclosed. Two or more target system code instructions may be grouped into one or more fragments. A main translation function may be implemented by translating each fragment into a corresponding set of position-independent instructions executable by the host system. A target processor may be emulated by executing the corresponding set of position-independent executable instructions with the host system.

Abstract: In emulation of a target system on a host system one or more blocks of target system code may be translated with the host system to produce one or more corresponding blocks of translated code. Translating the target system code may include linking two or more blocks of translated code together to form a chain such that a look-up in a first translated block in the chain will directly branch to a second translated block. The target system code may be analyzed for the presence of one or more native target system instructions indicating modification of the target system code during execution. If such native target system instructions are present some or all of the blocks of translated code may be marked potentially invalid. The one or more blocks marked as potentially invalid may be re-translated and one or more instructions in the blocks of translated code may be overridden without undoing the chain.

Abstract: Systems and methods provide for emulating a host architecture in guest firmware. One aspect of the systems and methods comprises determining whether an emulated instruction would cause a transition into a legacy mode. A current execution context is converted into a legacy mode context, and the firmware emulator proceeds to a group of legacy mode instructions in a native mode for the processor. The firmware emulator detects an end instruction and converts the legacy context back to the guest firmware context.

Abstract: A system and method is disclosed for formal verification of software programs that advantageously bounds the ranges of values that a variable in the software can take during runtime.

Abstract: A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

Abstract: A native device includes a memory storing a personal computing environment; an interface configured for coupling with a host information processing system; a native function system for performing a native function; and a native function emulator for emulating the native function in the host information processing system. According to another embodiment, a host information processing system includes: an interface for coupling with a native device comprising its user's personal computing environment; a processor configured for operating with the native device when the native device is coupled; and logic for emulating functions of the native device when the native device is coupled.

Abstract: A system and method for creating a rights expression for association with an item for use in a system for controlling use of the item in accordance with the rights expression, including specifying rights expression information indicating a manner of use of an item, the rights expression information including at least one element, the element having a variable and corresponding value for the variable; and performing an encoding process, including determining an identifier associated with a template corresponding to the rights expression information, extracting from the rights expression information the value for the variable corresponding to the element, and encoding a license adapted to be enforced on a device based on the variable and the identifier, the license including an identification of the template and the value for the variable.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

Abstract: A method, computer readable medium and apparatus that utilize a JavaScript emulator in a proxy server to create and store an object model of a web page which has one or more JavaScript instruction sets. At least one of the one or more JavaScript instruction sets are extracted from the web page and a JavaScript field identifier is inserted into the web page to optimize the web page which is then provided.

Abstract: A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.

Abstract: A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.

Abstract: Processor emulation using fragment level translation is disclosed. A target system having a main target processor, a secondary target processor element and an instruction memory associated with the secondary target processor element may be emulated with a host system having one or more host processors and a host memory. Two or more target system code instructions for the secondary target processor may be grouped into one or more fragments with known starts and ends. A data structure that maps the host memory locations of the starts and ends may be maintained. Each fragment may be translated into a corresponding set of position-independent translated fragments executable by the host system. The translated fragments may be loaded into one or more of the host processors. If a memory layout for target system code corresponding to the one or more fragments has changed, the fragments may be dynamically re-linked, without re-translation, and executed.

Abstract: An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.

Abstract: In emulation of a target system on a host system one or more blocks of target system code may be translated with the host system to produce one or more corresponding blocks of translated code. Translating the target system code may include linking two or more blocks of translated code together to form a chain such that a look-up in a first translated block in the chain will directly branch to a second translated block. The target system code may be analyzed for the presence of one or more native target system instructions indicating modification of the target system code during execution. If such native target system instructions are present some or all of the blocks of translated code may be marked potentially invalid. The one or more blocks marked as potentially invalid may be re-translated and one or more instructions in the blocks of translated code may be overridden without undoing the chain.

Abstract: An original processor uses addresses with a first length of n bits for addressing in a cyclical address space and a target processor uses addresses with a second length of m bits, where the second length m is greater than the first length n. In the original processor, distance values that lie between a lower value min and an upper value max are permissible for the base register-relative addressing. The supported address space on the original processor for the code to be emulated is limited in such a manner that the conversion of address operands as described in the following steps leads to semantically equivalent behavior on the target processor.

Abstract: A method and system for emulating tape library commands is disclosed. Tape library commands implemented in response to commands received from a data protection application are emulated in a disk based storage medium so that existing data protection applications may be used to copy data to and from the disk based storage medium.

Abstract: Configuring reconfigurable interconnect resources employing a switch matrix and configuration bit look-up table are disclosed. Reconfigurable interconnect resources include multiplexors to decrease the number of bits needed to load a configuration. Distributed processing resources configure a selected reconfigurable interconnect resource, interconnecting each input of the reconfigurable interconnect resource with a particular output of the reconfigurable interconnect resource using configuration bits scalably extracted from a row of configuration bits of a look-up table. Use of a configuration bit look-up table allows for compression of the bits needed to load the configuration for a reconfigurable interconnect resource.

Abstract: A processor may include a floating-point unit (FPU) and an arithmetic logic unit (ALU). Instructions to the processor may include greater or lesser amounts of floating-point operations and integer operations. In a circumstance where instructions include predominantly integer operations, power to the FPU may be reduced or turned completely off. In such a circumstance, occasional floating-point operations may be emulated and performed by the ALU. If the processor subsequently determines that incoming instructions include a greater proportion of floating-point operations, the FPU may be powered back on and used to perform the floating-point operations.

Abstract: Systems and methods for protecting client computers are described. One method includes receiving webpage data at a proxy from a webpage before the data reaches an intended recipient; gathering scripting-language-data from the webpage data; normalizing the scripting-language-data so as to generate normalized data; emulating execution of the normalized scripting-language-data with a inspection-point-script-execution engine that that is adapted to provide inspection points instead of effectuating particular functions, and determining whether to block the data from the intended recipient by analyzing inspection-data collected from the inspection points.

Abstract: The invention relates to a verification of applications in interpreted language of the byte-code type (pseudo-code) loaded on portable electronic devices, in particular a chipcard and a method for verification of an application (31) interpreted by a virtual machine (42), said application being loaded on a portable electronic device (1), comprising at least one processor (2) and one RAM (5). The method comprises carrying out the following after loading said application in the device and before validation thereof, checks in the code of said application by means of a process carried out by the processor (2), characterized in comprising, on starting a sub-program, a step of backing up the actual verification context (200 to 203) in the RAM (5), a step for creation and activation of a new verification context (206 to 209) for the sub-program and a step for restoration of the verification context (200 to 203) previously backed-up.

Abstract: A data processor is arranged to execute software to emulate an instruction-handling processor having an instruction preparation stage and an instruction execution stage. The software is operable first to emulate the instruction preparation stage in respect of a group of two or more instructions to generate a group of prepared instructions; and then to emulate the instruction execution stage in respect of the group of prepared instructions, so that the completion of the emulation of the instruction execution stage in respect of each of the prepared instructions occurs serially in an instruction order.

Abstract: The present invention concerns a mainframe data stream proxy (MDSP) (1) for caching communication of at least one emulator (2) directed to at least one mainframe (3), wherein the MDSP (1) comprises: a. a runtime application server (10), adapted for receiving (101, 201) at least one emulator action from the at least one emulator (2) and for sending (105, 209) at least one corresponding mainframe action to the at least one emulator (2); b. wherein the runtime application server (10) is further adapted for retrieving (102, 103) the at least one corresponding mainframe action to be sent to the at least one emulator (2) from a cache (20) of the MDSP (1).

Abstract: A system comprising a media processing apparatus and a computer where the media processing apparatus emulates a mass storage device and interfaces with the computer is disclosed. In one embodiment the media processing apparatus appears to the computer as a Universal serial bus (USB) mass storage device, and the operating system (OS) on the computer, using its pre-installed USB mass storage device driver, establishes bi-directional communication channel with the media processing apparatus. Thus, the need to develop an OS specific kernel-mode device driver for the media processing apparatus is eliminated. The system may employ a proprietary communication protocol on the USB bus to send and receive data between the computer and the media processing apparatus.

Abstract: Operational resource modeling is usable to analyze application and computer system performance over a wide range of hypothetical scenarios. Operational resource modeling involves creating and training one or more resource models, and/or simulating hypothetical scenarios using resource models.

Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

Abstract: A virtualization apparatus includes: an emulation manager for searching a basic block cache for an entry with an entry point, and, if there exists no entry with the entry point in the basic block cache, requesting the identification of a basic block corresponding to the entry point; a basic block identifier for identifying the basic block by sequentially analyzing instructions of a source binary in response to a request from the emulation manager; and an instruction replacer for writing an entry of the identified basic block in an replaced instruction table, writing a branch instruction for the entry of the basic block in the source binary, and then branching to the entry point. The apparatus further includes an instruction emulator for executing an instruction of the basic block when a branch to the entry point is made.

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.

Abstract: A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.

Abstract: Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed.

Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.

Abstract: A method of restructuring a source computer program to a target computer program. A defined source computer program has source code. A set of tasks is defined for the source computer program to be performed by the source computer program. For each task, a corresponding set of input data sets is defined. For each input data set, a corresponding set of programs is determined such that each program in the set of programs includes declarations and executable statements, from the source code of the source computer program, required to execute the task in each input data set. Each set of programs is processed to generate a component that executes the respective task, resulting in generation of a set of components. A target computer program is generated from the set of components.

Abstract: A method of accurately simulating a target machine on a simulator, wherein, a mapping table is set up in a main program to record correspondence relations between target machine instructions and host machine instructions, and a signal handler is registered in a host machine for calling said mapping table. When an interrupt occurs while said simulator is performing simulation for a target program on the host machine, signal handler searches the mapping table to obtain or dynamically calculates to obtain host machine instruction corresponding to the next target machine instruction to be executed in target program; and replacing said host machine instruction with a return instruction, thus when executing said return instruction, the simulator will return to main program in checking said interrupt and proceeding with necessary proceedings required. Through the present invention, when said interrupt occurs, said simulator may return to main program in time for handling the interrupt.

Abstract: A method and system for exposing a version-independent interface to a computer resource. The interface system exposes a version-independent interface to a computer resource, such as a database or computer program. The interface system also provides a version-dependent interface to the computer resource that is typically not exposed. When the computer resource is modified, the version-dependent interface may be modified, but the version-independent interface might not be modified. When the version-dependent interface is modified, a mapping is generated (in some cases automatically) between the version-independent interface and the version-dependent interface. When an accessing computer program uses the version-independent interface to request services of the computer resource, the system uses the mapping to map the request to a request that is appropriate for the version-dependent interface.

Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction.

Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.

Abstract: An emulator schedules emulation threads for DMA emulation and other emulation functions in a time-multiplexed manner. Emulation threads are selected for execution according to a load balancing scheme. Non-DMA emulation threads are executed until their execution time period expires or they stall. DMA emulation thread execution is allowed to execute indefinitely until the DMA emulation thread stalls. The DMA emulation thread prefetches additional adjacent data in response to target computer system DMA requests. Upon receiving a target computer system DMA request, the DMA emulation thread first checks to the prefetched data to see if this data matches the request. If so, the request is fulfilled using the prefetched data. If the prefetched data does not match the target computer system DMA request, the DMA emulation thread fetches and stores the requested data and additional adjacent data for potential future use.