Discrete Cosine Transform (i.e., Dct) Patents (Class 708/402)
  • Patent number: 11051044
    Abstract: An image decoding apparatus that includes circuitry that performs filter processing on an image using both filter coefficients and a number of filter taps being set based on an orthogonal transform size, and decodes the image obtained through the filter processing.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 29, 2021
    Assignee: SONY CORPORATION
    Inventor: Kazushi Sato
  • Patent number: 10908879
    Abstract: A fast vector multiplication and accumulation circuit is applied to an artificial neural network accelerator and configured to calculate an inner product of a multiplier vector and a multiplicand vector. A scheduler is configured to arrange a plurality of multiplicands of the multiplicand vector into a plurality of scheduled operands according to a plurality of multipliers of the multiplier vector, respectively. A self-accumulating adder is signally connected to the scheduler and includes a compressor, at least two delay elements and at least one shifter. The compressor is configured to add the scheduled operands to generate a plurality of compressed operands. The at least two delay elements are connected to the compressor. The shifter is configured to shift one of the compressed operands. An adder is signally connected to the output ports of the compressor so as to add the compressed operands to generate the inner product.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: February 2, 2021
    Assignee: NEUCHIPS CORPORATION
    Inventors: Youn-Long Lin, Tao-Yi Lee
  • Patent number: 10809977
    Abstract: A first computation unit acquires a first variation coefficient representing characteristics of linear variation of first time-series data, and calculates a value of a start time point and a value of an end time point of the first time-series data. A second computation unit acquires a second variation coefficient representing characteristics of linear variation of second time-series data, and calculates a commencing time point in the second time-series data, and a completing time point obtained by adding a time width between the start time point and the end time point to the commencing time point. A difference integrated value is calculated between paired time points which are in the same positional relationship in a range from the start time point to the end time point and in a range from the commencing time point to the completing time point, without calculating values of intervening time points.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: October 20, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takeshi Takeuchi
  • Patent number: 10644877
    Abstract: Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, a first multiplier, and first selection circuitry coupled to the first adder/subtractor and the first multiplier. Respective bypass paths selectively bypass the first adder/subtractor and the first multiplier. The low input word path includes a second adder/subtractor, a second multiplier, and second selection circuitry coupled to the second adder/subtractor and the second multiplier. Respective bypass paths selectively bypass the second adder/subtractor and the second multiplier. The first and second selection circuitry is responsive to different mode control signals to reconfigure the low and high input word paths into different logic processing units.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: May 5, 2020
    Assignee: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Alhassan Khedr, Glenn Gulak
  • Patent number: 10536720
    Abstract: A method of decoding or encoding that includes generating a new multi-transform data structure by embedding one or more non-recursive transforms into a larger recursive transform. The method may further include receiving information regarding a target data block and determining whether to use a recursive transform or a non-recursive transform. When the determination is to use the recursive transform, the method may include generating the recursive transform using a multi-transform data structure and causing the target data block to be encoded or decoded using the generated recursive transform. If not, the method may include causing the target data block to be encoded or decoded using one of the one or more the non-recursive transforms embedded in the multi-transform data structure.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 14, 2020
    Assignee: TENCENT AMERICA LLC
    Inventors: Xin Zhao, Xiang Li, Shan Liu
  • Patent number: 10521232
    Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: December 31, 2019
    Assignee: ARM Limited
    Inventors: David James Seal, Richard Roy Grisenthwaite, Nigel John Stephens
  • Patent number: 10452356
    Abstract: An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 22, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Junji Ichimiya, Masahiro Kuramoto
  • Patent number: 10424305
    Abstract: An error-concealing audio decoding method comprises: receiving a packet comprising a set of MDCT coefficients encoding a frame of time-domain samples of an audio signal; identifying the received packet as erroneous; generating estimated MDCT coefficients to replace the set of MDCT coefficients of the erroneous packet, based on corresponding MDCT coefficients associated with a received packet directly preceding the erroneous packet; assigning signs of a first subset of MDCT coefficients of the estimated MDCT coefficients, wherein the first subset comprises such MDCT coefficients that are associated with tonal-like spectral bins, to coincide with signs of corresponding MDCT coefficients of said preceding packet; randomly assigning signs of a second subset of MDCT coefficients of the estimated MDCT coefficients, wherein the second subset comprises MDCT coefficients associated with noise-like spectral bins; replacing the erroneous packet by a concealment packet containing the estimated MDCT coefficients and the s
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: September 24, 2019
    Assignee: Dolby International AB
    Inventors: Arijit Biswas, Tobias Friedrich, Klaus Peichl
  • Patent number: 10349052
    Abstract: There is disclosed a method comprising receiving a set of coefficients; and determining whether a sign of a coefficient in the set of coefficients can be embedded in a bitstream. If the determining indicates that the sign of the coefficient in the set of coefficients can be embedded in the bitstream, an indication of the embedded sign is inserted into the bitstream. There is also disclosed a method comprising receiving a set of decoded coefficients; and determining whether a bitstream contains an indication of an embedded sign of a coefficient. If the determining indicates that the bitstream contains the indication of an embedded sign of a coefficient, the sign is determined on the basis of the decoded coefficients; and the sign of the coefficient is modified on the basis of the determined sign.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: July 9, 2019
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Kemal Ugur, Jani Lainema
  • Patent number: 10031846
    Abstract: The present embodiments relate to an address generator circuit for addressing a storage circuit. The address generator circuit may generate address signals for read and write access operations at the storage circuit. The write access operation may store a two-dimensional array in the storage circuit and the read access operation may retrieve a transpose of the two-dimensional array from the storage circuit. The address generator circuit may include a status flag generation circuit that generates status flag signals, a modulo adder circuit that receives first and second signals and computes a modulo adder output signal, and an address processing circuit. The address processing circuit may receive the modulo adder output signal from the modulo adder circuit and the plurality of status flag signals from the status flag generation circuit and provide the first and second signals to the modulo adder circuit.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: July 24, 2018
    Assignee: Altera Corporation
    Inventors: Simon Peter Finn, Martin Langhammer
  • Patent number: 9851970
    Abstract: An apparatus and method are described for performing SIMD reduction operations. For example, one embodiment of a processor comprises: a value vector register containing a plurality of data element values to be reduced; an index vector register to store a plurality of index values indicating which values in the value vector register are associated with one another; single instruction multiple data (SIMD) reduction logic to perform reduction operations on the data element values within the value vector register by combining data element values from the value vector register which are associated with one another as indicated by the index values in the index vector register; and an accumulation vector register to store results of the reduction operations generated by the SIMD reduction logic.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 26, 2017
    Assignee: INTEL CORPORATION
    Inventors: David M. Kunzman, Christopher J. Hughes
  • Patent number: 9838704
    Abstract: Embodiments of the present application provide a method for decoding a video and an apparatus for decoding a video, which increases accuracy of data processing while simplifying a micro architecture design of inverse discrete cosine transform in video decoding process. The method comprises: storing received data to be decoded in a plurality of first data registers and a plurality of second data registers that are spaced with each other in sequence; performing shift and look-up table processing on the data to be decoded that is stored in the first data registers and the second data register, to obtain a look-up table result corresponding to a first coefficient matrix and a look-up table result corresponding to a second coefficient matrix respectively; performing a distributed computing on the look-up table result corresponding to the first coefficient matrix and the look-up table result corresponding to the second coefficient matrix, to obtain decoded data.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: December 5, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jianming Wang, Zhiming Meng, Zongze He
  • Patent number: 9825614
    Abstract: A common sub-expression elimination method for simplifying hardware logic of a hardware filter circuit by eliminating a common sub-expression included in a plurality of sub-expressions is provided. Each of the sub-expressions includes a corresponding two or more of inputs constituting a plurality of coefficients used by the hardware filter circuit. The method is implemented on a computing device and includes: identifying for each coefficient of the plurality of coefficients, a combination of the inputs constituting the coefficient; counting occurrences of the sub-expressions in each of the coefficients; identifying one or more of the sub-expressions having a maximum one of the counts and including the corresponding two or more of the inputs; selecting one of the one or more of the sub-expressions as the common sub-expression; eliminating the common sub-expression; and repeating these steps to eliminate more of the sub-expressions common to multiple ones of the coefficients.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hassan Kamal, Hee Chul Hwang
  • Patent number: 9779748
    Abstract: The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a 64 channel filter bank using a prototype filter length of 640 coefficients and a system delay of 319 samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: October 3, 2017
    Assignee: Dolby International AB
    Inventor: Per Ekstrand
  • Patent number: 9727531
    Abstract: Provided is a fast Fourier transform circuit including: a first butterfly circuit and a second butterfly circuit which perform butterfly calculations corresponding to calculation bit-widths being different from each other; and a control means which controls selection of the first and second butterfly circuits in accordance with any one of a plurality of operation modes including: a first operation mode in which a calculation is performed by both of the first and second butterfly circuits; and a second operation mode in which a calculation is performed by any one of the first and second butterfly circuits.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 8, 2017
    Assignee: NEC CORPORATION
    Inventor: Atsufum Shibayama
  • Patent number: 9727530
    Abstract: Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described and comprise (1) performing a first transform on a block of first input values to obtain a block of first output values by scaling the block to obtain scaled input values, performing a scaled one-dimensional (1D) transform on each row of the block, and performing a scaled 1D transform on each column of the block; and (2) performing a second transform on a block of second input values to obtain a block of second output values by performing a scaled 1D transform on each row of the block, performing a scaled 1D transform on each column of the block, and scaling the block.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: August 8, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Yuriy Reznik, Albert Scott Ludwin, Hyukjune Chung, Harinath Garudadri, Naveen B. Srinivasamurthy, Phoom Sagetong
  • Patent number: 9712829
    Abstract: A method and system may identify a video data block using a video codec and apply a transform kernel of a butterfly asymmetric discrete sine transform (ADST) to the video data block in a pipeline.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: July 18, 2017
    Assignee: Google Inc.
    Inventors: Jingning Han, Yaowu Xu, Debargha Mukherjee
  • Patent number: 9641721
    Abstract: An image processing system includes a first flip-flop bank and a second flip-flop bank, and a control system configured to control JPEG processing of image data. The control system is further configured to, during a first period, use one of the first or second flip-flop banks as a write bank and the other of the first or second flip-flop banks as a read bank and, during a second period, alternate the use of the first and second flip-flop banks as the write bank and the read bank. Further, the control system is configured to, after alternating the use, initialize the read bank to zero.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 2, 2017
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Thien-Phuc Nguyen Do
  • Patent number: 9634647
    Abstract: An apparatus for generating real-valued output audio samples is disclosed. The apparatus includes a memory that stores complex-valued input subband samples, real-valued demodulated samples, and the real-valued output audio samples. The apparatus also incudes a phase shifter that shifts a phase of the complex-valued input subband samples by an amount equal to a previously added phase shift and a complex-valued synthesis filter bank that generates the real-valued output audio samples in response to the complex-valued input subband samples, the real-valued demodulated samples, and prototype filter coefficients.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 25, 2017
    Assignee: Dolby International AB
    Inventor: Per Ekstrand
  • Patent number: 9459831
    Abstract: A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: October 4, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Yuriy Reznik
  • Patent number: 9378185
    Abstract: A method of encoding a video stream in a video encoder is provided that includes computing an offset into a transform matrix based on a transform block size, wherein a size of the transform matrix is larger than the transform block size, and wherein the transform matrix is one selected from a group consisting of a DCT transform matrix and an IDCT transform matrix, and transforming a residual block to generate a DCT coefficient block, wherein the offset is used to select elements of rows and columns of a DCT submatrix of the transform block size from the transform matrix.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: June 28, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mangesh Sadafale, Madhukar Budagavi
  • Patent number: 9378186
    Abstract: A data processing apparatus and method are provided for performing a transform between spatial and frequency domains when processing video data. The data processing apparatus comprises transform circuitry configured to receive N input values and to perform a sequence of operations to generate N output values representing the transform of the N input values between the spatial and frequency domains. In doing this, the transform circuitry employs a base circuitry that is configured to receive M internal input values generated by the transform circuitry, where M is greater than or equal to 4, and to perform a base operation equivalent to matrix multiplication of the M internal input values by a Hankel matrix, which is a square matrix with constant skew diagonals, where each element of the array identifies a coefficient, performance of the base operation generating M internal output values for returning to the transform circuitry.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 28, 2016
    Assignee: ARM Limited
    Inventors: Dominic Hugo Symes, Tomas Edso
  • Patent number: 9378560
    Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: June 28, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Konstantine Iourcha, John W. Brothers
  • Patent number: 9349196
    Abstract: A first set of discrete cosine transform (DCT) blocks is obtained. Each DCT block from the first set of DCT blocks has a first block size. When performing a split operation on the first set of DCT blocks, a filter is applied to the first set of DCT blocks. A second set of data blocks is generated based on the first set of DC blocks using a transform function. Each block in the second set of data blocks has a second block size. When performing a merge operation, the filter is applied to the second set of data blocks.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 24, 2016
    Assignee: Red Hat, Inc.
    Inventor: Christopher Montgomery
  • Patent number: 9311275
    Abstract: Discrete cosine transform/inverse discrete cosine transform method and device are provided. The discrete cosine transform/inverse discrete cosine transform method includes: generating a table index for only an input value other than 0 (zero) out of input values of coordinates in an input block; reading one or more partial values corresponding to the table index out of a plurality of table information pieces which are generated and stored in advance so as to include partial values corresponding to a multiplication of a weight value and an index; and adding the read partial value and calculating the resultant value of each coordinate in an output block. Accordingly, it is possible to perform a fast DCT/IDCT operation and to reduce the energy consumption for the transform.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: April 12, 2016
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION, HANYANG UNIVERSITY)
    Inventors: Euee S Jang, Kiho Choi, Sunyoung Lee, Sikyoung Kim
  • Patent number: 9172980
    Abstract: A method for adaptively performing video decoding includes: performing decoding complexity management based upon bit stream information of an input bit stream, in order to determine whether to reduce decoding complexity of at least one component of a plurality of components within an adaptive complexity video decoder; and selectively reducing decoding complexity of a portion of components within the adaptive complexity video decoder. An associated adaptive complexity video decoder and an associated adaptive audio/video playback system are also provided. In particular, the adaptive complexity video decoder includes a plurality of components and a decoding complexity manager. When needed, the decoding complexity manager delays audio playback of audio information.
    Type: Grant
    Filed: July 5, 2010
    Date of Patent: October 27, 2015
    Assignee: MEDIATEK INC.
    Inventors: Fang-Yi Hsieh, Jian-Liang Lin
  • Patent number: 9117060
    Abstract: A system and method for preventing an application program, which is licensed to a customer to be exclusively executed in a processor based on a certain processor design, from being executed properly in unauthorized processors is provided. The system includes a scrambling module and a recovery module. The scrambling module scrambles a selected portion of the application program using an identifier which identifies the authorized processor design. The recovery module adds an unscrambling program to the application program such that when the program is running in a processor, it retrieves a second identifier from the processor and unscrambles the scrambled portion of the application program using the retrieved second identifier. If the second identifier does not correspond to an authorized processor design, the unscrambling operation will incorrectly unscramble the scrambled portion and the application program will not run properly.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 25, 2015
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Darin S. Petkov, Dror E. Maydan, Pushkar G. Patwardhan, Sachin P. Ghanekar, Samir S. Pathak
  • Patent number: 9081733
    Abstract: In general, techniques are described for implementing a 16-point inverse discrete cosine transform (IDCT) that is capable of applying multiple IDCTs of different sizes. For example, an apparatus comprising a 16-point inverse discrete cosine transform of type II (IDCT-II) unit may implement the techniques of this disclosure. The 16-point IDCT-II unit performs these IDCTs-II of different sizes to transform data from a spatial to a frequency domain. The 16-point IDCT-II unit includes an 8-point IDCT-II unit that performs one of the IDCTs-II of size 8 and a first 4-point IDCT-II unit that performs one of the IDCTs-II of size 4. The 8-point IDCT-II unit includes the first 4-point DCT-II unit. The 16-point IDCT-II unit also comprises an inverse 8-point DCT-IV unit that includes a second 4-point IDCT-II unit and a third 4-point IDCT-II unit. Each of the second and third 4-point IDCT-II units performs one of the IDCTs-II of size 4.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: July 14, 2015
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yuriy Reznik, Rajan L. Joshi, Marta Karczewicz
  • Patent number: 9076254
    Abstract: A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Victor W. Lee, Mikhail Smelyanskiy, Ganesh S. Dasika, Jose Gonzalez, Jatin Chhugani, Yen-Kuang Chen, Changkyu Kim, Julio Gago, Santiago Galan, Victor Moya Del Barrio
  • Patent number: 9075757
    Abstract: In general, techniques are described for implementing a 16-point discrete cosine transform (DCT) that is capable of applying multiple IDCT of different sizes. For example, an apparatus comprising a 16-point discrete cosine transform of type II (DCT-II) unit may implement the techniques of this disclosure. The 16-point DCT-II unit performs these DCTs-II of different sizes to transform data from a spatial to a frequency domain. The 16-point DCT-II unit includes an 8-point DCT-II unit that performs one of the DCTs-II of size 8 and a first 4-point DCT-II unit that performs one of the DCTs-II of size 4. The 8-point DCT-II unit includes the first 4-point DCT-II unit. The 16-point DCT-II unit also comprises an 8-point DCT-IV unit that includes a second 4-point DCT-II unit and a third 4-point DCT-II unit. Each of the second and third 4-point DCT-II units performs one of the DCTs-II of size 4.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: July 7, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Yuriy Reznik, Rajan L. Joshi, Marta Karczewicz
  • Patent number: 9066097
    Abstract: A joint optimization iterative algorithm determines optimized mode pairs. Each mode pair includes an intra-predictor and a transform pair that are iteratively modified to determine an optimized intra-predictor and an optimized transform that forms the optimized mode pair. A set of training videos and a set of quantization parameters (QPs) are used as the base data for determining the optimized mode pairs. Each video includes a plurality of pixel blocks, herein referred to as blocks. Block statistics associated with each mode pair are accumulated by separately encoding each block using each mode pair, and selecting the best mode pair for each block according to a measured characteristic of each encoding. The accumulated block statistics are used to modify the intra-predictor and the transform within each mode pair.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: June 23, 2015
    Assignee: SONY CORPORATION
    Inventors: Cheung Auyeung, Ali Tabatabai
  • Patent number: 9026573
    Abstract: A recursive type-IV discrete cosine transform system includes a first permutation device, a recursive type-III discrete cosine/sine transform device, a cosine/sine factor generation device, a recursive type-II discrete cosine/sine transform device, a second permutation device. The first permutation device performs two-dimensional order permutation operation on N digital signals for generating N two-dimensional first temporal signals. The recursive type-III discrete cosine/sine transform device repeats a type-III discrete cosine/sine transform for generating second temporal signals. The cosine/sine factor generation device sequentially performs cosine/sine factor multiplication and corresponding addition operations for generating third temporal signals. The recursive type-II discrete cosine/sine transform device repeats a type-II discrete cosine/sine transform for generating fourth temporal signals.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: May 5, 2015
    Assignee: National Cheng Kung University
    Inventors: Sheau-Fang Lei, Shin-Chi Lai, Wen-Chieh Tseng
  • Patent number: 9002122
    Abstract: A codec includes an encoder having a quantization level generator that defines a quantization level specific to a block of values (e.g., transform coefficients), a quantizer that quantizes the block of transform coefficients according to the block-specific quantization level, a run-length encoder, and an entropy encoder. The quantization level is defined to result in at least a predetermined number (k) of quantized coefficients having a predetermined value. The amount of data compression by the encoder is proportional to (k). The codec also includes a decoder having entropy and run-length decoding sections whose throughputs are proportional to (k). The decoder takes advantage of this increased throughput by further decoding coefficients in parallel using a plurality of decoding channels. Methods for encoding and decoding data are also disclosed. The invention is well-suited to quantization, entropy, and/or run-length-based codecs, such as JPEG.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: April 7, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventor: Xuanming Du
  • Patent number: 8990280
    Abstract: In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: March 24, 2015
    Assignee: Nvidia Corporation
    Inventors: Partha Sriram, Robert Quan, Bhagawan Reddy Gnanapa, Ahmet Karakas
  • Publication number: 20140337396
    Abstract: A data processing apparatus and method are provided for performing a transform between spatial and frequency domains when processing video data. The data processing apparatus comprises transform circuitry configured to receive N input values and to perform a sequence of operations to generate N output values representing the transform of the N input values between the spatial and frequency domains. In doing this, the transform circuitry employs a base circuitry that is configured to receive M internal input values generated by the transform circuitry, where M is greater than or equal to 4, and to perform a base operation equivalent to matrix multiplication of the M internal input values by a Hankel matrix, which is a square matrix with constant skew diagonals, where each element of the array identifies a coefficient, performance of the base operation generating M internal output values for returning to the transform circuitry.
    Type: Application
    Filed: March 26, 2014
    Publication date: November 13, 2014
    Applicant: ARM LIMITED
    Inventors: Dominic Hugo SYMES, Tomas EDSO
  • Patent number: 8849884
    Abstract: Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described. A full transform is a transform that implements the complete mathematical description of the transform. A full transform operates on or provides full transform coefficients. A scaled transform is a transform that operates on or provides scaled transform coefficients, which are scaled versions of the full transform coefficients. The scaled transform may have lower computational complexity whereas the full transform may be simpler to use by applications. The full and scaled transforms may be for a 2D IDCT, which may be implemented in a separable manner with 1D IDCTs. The full and scaled transforms may also be for a 2D DCT, which may be implemented in a separable manner with 1D DCTs. The 1D IDCTs and 1D DCTs may be implemented in a computationally efficient manner.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: September 30, 2014
    Assignee: Qualcom Incorporate
    Inventors: Yuriy Reznik, Albert Scott Ludwin, Hyukjune Chung, Harinath Garudadri, Naveen Srinivasamurthy, Phoom Sagetong
  • Patent number: 8819095
    Abstract: A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: August 26, 2014
    Assignee: Qualcomm Incorporated
    Inventor: Yuriy Reznik
  • Patent number: 8762441
    Abstract: In general, techniques are described that provide for 4×4 transforms for media coding. A number of different 4×4 transforms are described that adhere to these techniques. As one example, an apparatus includes a 4×4 discrete cosine transform (DCT) hardware unit. The DCT hardware unit implements an orthogonal 4×4 DCT having an odd portion that applies first and second internal factors (C, S) that are related to a scaled factor (?) such that the scaled factor equals a square root of a sum of a square of the first internal factor (C) plus a square of the second internal factor (S). The 4×4 DCT hardware unit applies the 4×4 DCT implementation to media data to transform the media data from a spatial domain to a frequency domain. As another example, an apparatus implements a non-orthogonal 4×4 DCT to improve coding gain.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: June 24, 2014
    Assignee: Qualcomm Incorporated
    Inventor: Yuriy Reznik
  • Patent number: 8724913
    Abstract: A method for decoding run-length encoded (RLE) data includes the steps of receiving the RLE data and storing a predetermined value (e.g., zero) in each of a plurality of consecutively-accessible storage locations of a buffer. The method further includes writing a first value different than the predetermined value to a first storage location based on the RLE data, jumping over (i.e., skipping) a number of the consecutively-accessible storage locations from the first storage location to a next storage location based on the RLE data, and writing a next value different than the predetermined value to the next storage location based on the RLE data. In the case of JPEG, the values stored in the storage locations of the buffer are quantized coefficients associated with a block of image data. A run-length decoder is also described.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: May 13, 2014
    Assignee: Omnivision Technologies, Inc.
    Inventor: Xuanming Du
  • Patent number: 8718144
    Abstract: In general, techniques are described for implementing an 8-point discrete cosine transform (DCT). An apparatus comprising an 8-point discrete cosine transform (DCT) hardware unit may implement these techniques to transform media data from a spatial domain to a frequency domain. The 8-point DCT hardware unit includes an even portion comprising factors A, B that are related to a first scaled factor (?) in accordance with a first relationship. The 8-point DCT hardware unit also includes an odd portion comprising third, fourth, fifth and sixth internal factors (G, D, E, Z) that are related to a second scaled factor (?) in accordance with a second relationship. The first relationship relates the first scaled factor to the first and second internal factors. The second relationship relates the second scaled factor to the third internal factor and a fourth internal factor, as well as, the fifth internal factor and a sixth internal factor.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: May 6, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Yuriy Reznik, Rajan Laxman Joshi, Marta Karczewicz
  • Patent number: 8706786
    Abstract: A signal processing device and an image processing device are provided. The signal processing device includes a matrix calculator for performing a matrix operation selected by a switch part among a DCT matrix operation, a Haar matrix operation, and a Slant matrix operation, with respect to an input signal. Thus, the signal processing device can be implemented in a hybrid architecture capable of selectively processing the DCT-II transform, the Haar transform, and the Slant transform with a single chip.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: April 22, 2014
    Assignee: Industrial Cooperative Foundation Chonbuk National University
    Inventors: Moon Ho Lee, Dae Chul Park
  • Patent number: 8700687
    Abstract: A video codec method is provided, for processing video data processed by a Discrete Cosine Transformation (DCT) operation, comprising: (a) if a transformation matrix having a plurality of coefficients comprises at least one non-integer coefficient among the coefficients, multiplying the transformation matrix by a multiplication factor ? to make all coefficients of the transformation matrix integers, (b) estimating a compensation set, (c) performing a Column in Row out IDCT two-dimensional operation on the video data according to the transformation matrix and the compensation set, to obtain a compensated two-dimension operation result, (d) selectively dividing the compensated two-dimension operation result by ?2 to obtain an IDCT operation result.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 15, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Ying-Chieh Tu, Jin-Mu Wu, Yao-Hsin Wang
  • Patent number: 8631060
    Abstract: A more efficient encoder/decoder is provided in which an N-point MDCT transform is mapped into smaller sized N/2-point DCT-IV, DST-IV and/or DCT-II transforms. The MDCT may be systematically decimated by factor of 2 by utilizing a uniformly scaled 5-point DCT-II core function as opposed to the DCT-IV or FFT cores used in many existing MDCT designs in audio codecs. Various transform factorizations of the 5-point transforms may be implemented to more efficiently implement a transform.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 14, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Yuriy Reznik, Ravi Kiran Chivukula
  • Patent number: 8606839
    Abstract: A method for computing a fast Fourier transform (FFT) in a parallel processing structure uses an interleaved computation process. In particular, the interleaved FFT computation process intertwines the output of two different shifted Fourier matrices to obtain a Fourier transform of an input vector. Next, an even-odd extension process is applied to the transformed input vector, whereupon various terms are grouped in a computational tree. As such, the resulting segmentation of the computation allows the fast Fourier transform to be computed in a parallel manner.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: December 10, 2013
    Assignee: The University of Akron
    Inventors: Dale H. Mugler, Nilimb Misal
  • Publication number: 20130318141
    Abstract: Systems and methods for generating updates of large scale 3D geological models with multi-model facies, permeability or porosity distribution.
    Type: Application
    Filed: November 2, 2010
    Publication date: November 28, 2013
    Inventor: Marko Maucec
  • Patent number: 8595281
    Abstract: Techniques for efficiently performing transforms on data are described. In one design, an apparatus performs multiplication of a first group of at least one data value with a first group of at least one rational dyadic constant that approximates a first group of at least one irrational constant scaled by a first common factor. The apparatus further performs multiplication of a second group of at least one data value with a second group of at least one rational dyadic constant that approximates a second group of at least one irrational constant scaled by a second common factor. Each rational dyadic constant is a rational number with a dyadic denominator. The first and second groups of at least one data value have different sizes. The first and common factors may be selected based on the number of logical and arithmetic operations for the multiplications, the precision of the results, etc.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: November 26, 2013
    Assignee: QUALCOMM Incorporated
    Inventor: Yuriy Reznik
  • Patent number: 8514947
    Abstract: A semiconductor device including a first processing unit processing an input signal based on a plurality of image compression standards, a signal generation unit outputting a switching signal to the first processing unit, a first calculation unit performing an operation on the input signal in accordance with a first coefficient that is based on the switching signal, a second calculation unit performing an operation on an output of the first calculation unit in accordance with a second coefficient that is based on the switching signal, a selection unit selecting one of the output of the first calculation unit and an output of the second calculation unit based on the switching signal, and a third calculation unit selecting one or both of the input signal and the output of the first calculation unit based on the switching signal and performing a predetermined calculation on the selected signal.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: August 20, 2013
    Assignee: Fujitsu Limited
    Inventors: Noboru Yoneoka, Hirofumi Nagaoka
  • Publication number: 20130173679
    Abstract: A recursive type-IV discrete cosine transform system includes a first permutation device, a recursive type-III discrete cosine/sine transform device, a cosine/sine factor generation device, a recursive type-II discrete cosine/sine transform device, a second permutation device. The first permutation device performs two-dimensional order permutation operation on N digital signals for generating N two-dimensional first temporal signals. The recursive type-III discrete cosine/sine transform device repeats a type-III discrete cosine/sine transform for generating second temporal signals. The cosine/sine factor generation device sequentially performs cosine/sine factor multiplication and corresponding addition operations for generating third temporal signals. The recursive type-II discrete cosine/sine transform device repeats a type-II discrete cosine/sine transform for generating fourth temporal signals.
    Type: Application
    Filed: July 25, 2012
    Publication date: July 4, 2013
    Inventors: Sheau-Fang LEI, Shin-Chi LAI, Wen-Chieh TSENG
  • Patent number: 8451904
    Abstract: In general, techniques are described for implementing an 8-point discrete cosine transform (DCT). An apparatus comprising an 8-point discrete cosine transform (DCT) hardware unit may implement these techniques to transform media data from a spatial domain to a frequency domain. The 8-point DCT hardware unit includes an even portion comprising factors A, B that are related to a first scaled factor (?) in accordance with a first relationship. The 8-point DCT hardware unit also includes an odd portion comprising third, fourth, fifth and sixth internal factors (G, D, E, Z) that are related to a second scaled factor (?) in accordance with a second relationship. The first relationship relates the first scaled factor to the first and second internal factors. The second relationship relates the second scaled factor to the third internal factor and a fourth internal factor, as well as, the fifth internal factor and a sixth internal factor.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: May 28, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Yuriy Reznik, Rajan L. Joshi, Marta Karczewicz
  • Patent number: 8423597
    Abstract: A method and system for adaptive matrix trimming in an inverse discrete cosine transform (IDCT) operation. At least one row of an input matrix is accessed. At least one matrix element of the row having a value of zero is detected. During execution of an IDCT multiplication operation on the row for generating an output row, IDCT multiplication operation for a matrix element having a value of zero is skipped.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: April 16, 2013
    Assignee: NVIDIA Corporation
    Inventors: Yiu Cheong Ho, Eric Kwong-Hang Tsang