Abstract: A method is disclosed for performing an inverse discrete cosine transform (IDCT) using a microprocessor having an instruction set that includes SIMD floating-point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating-point form so that the registers each hold two floating-point row data values; and (c) using SIMD floating-point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating-point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-IDCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-IDCT, two columns are preferably processed concurrently using SIMD instructions to improve computational efficiency.

Abstract: The present invention relates to the methods of estimation and recovering of general affine geometrical transformations which were applied to data, extensible to any other defined class of geometrical transformations, according to the preamble of the dependent claims. The parameters of the undergone deformation are robustly estimated based on maxima given by a parametric transform such as Hough transform or Radon transform of some embedded information with periodical or any other known regular structure. The main applications of this invention are robust digital still image/video watermarking, document authentication, and detection of periodical or hidden patterns. In the case of periodical watermarks, the watermark can also be predistorted before embedding based on a key to defeat block-by-block removal attack.

Abstract: A device and method are described that apply 1-D and 2-D discrete cosine transforms (DCT) and inverse discrete cosine transforms (IDCT) to sets of input data, typically 8×8 or 16×16 matricies of coefficients. One device includes input lines, logic to pre-add input values and generate opcrands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the device may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic or pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.

Abstract: A system and method for parallel computation of Discrete Sine and Cosine Transforms. The computing system includes a plurality of interconnected processors and corresponding local memories. An input signal x is received, partitioned into P local vectors xi, and distributed to the local memories. The preprocessors may calculate a set of coefficients for use in computing the transform. The processors perform a preprocess in parallel on the input signal x to generate an intermediate vector y. The processors then perform a Fast Fourier Transform in parallel on the intermediate vector y, generating a second intermediate vector a. Finally, the processors perform a post-process on the second intermediate vector a, generating a result vector v, the Discrete Transform of signal x. In one embodiment, the method generates the Discrete Sine Transform of the input signal x. In another embodiment, the method generates the Discrete Cosine Transform of the input signal x.

Abstract: A system and method for carrying out a two-dimensional forward and/or inverse discrete cosine transform is disclosed herein. In one embodiment, the method includes, but is not necessarily limited to: (1) receiving multiple data blocks; (2) grouping together one respective element from each of the multiple data blocks to provide full data vectors for single-instruction-multiple-data (SIMD) floating point instructions; and (3) operating on the full data vectors with SIMD instructions to carry out the two dimensional transform on the multiple data blocks. Preferably the two dimensional transform is carried out by performing a linear transform on each row of the grouped elements, and then performing a linear transform on each column of the grouped elements. The method may further include isolating and arranging the two dimensional transform coefficients to form transform coefficient blocks that correspond to the originally received multiple data blocks.

Abstract: A compressed data buffer 21 maintains an image data loaded from a storage device 1, and a decoding section 22 conducts variable length decoding, inverse quantization and inverse discrete cosine transform, and a pixel data shifting section 23 shifts each value of pixel data to right by 1 bit, and a motion compensating section 24 applies motion compensation processing to the data shifted to right by 1 bit, and the frame data buffer 25 stores an image data to be displayed, and a reference data calculating section 24a of the motion compensating section 24 obtains a reference data from a reference buffer based on a motion vector, and a reference data adding section 24b adds the reference data to a data to which decoding processing has been applied, and a reference data storing section 24c leaves in the reference buffer the data to which the motion compensation processing has been applied.

Abstract: A method including decimating a signal x using a filter f to obtain a decimated signal y, interpolating the decimated signal y to obtain a reconstructed signal z, determining a refinement factor s by decimating z and comparing decimated z to the decimated signal y, and determining an improved reconstructed signal r by using the refinement factor s, the filter f, and the reconstructed signal z is disclosed.

Abstract: Apparatus, methods, and computer program products are provided for generating a second set of equations requiring reduced numbers of computations from a first set of general equations, wherein each general equation defines coefficients in terms of a set of samples and a plurality of functions having respective values. A first set of tokens is initially assigned to the plurality of functions such that every value of the functions that has a different magnitude is assigned a different token, thereby permitting each general equation to be defined by the set of samples and their associated tokens. Each general equation is then evaluated and the samples having the same associated token are grouped together. A second set of tokens is then assigned to represent a plurality of unique combinations of the samples. The second set of equations is then generated based at least on the first and second sets of tokens.

Abstract: In one example, a transform component of a system receives a first plurality of image parts in a first domain that comprise an initial size. A transform component of the system transforms the first plurality of image parts to obtain a second plurality of image parts in a second domain different from the first domain. A transform component of the system transforms a plurality of image parts based on the second plurality of image parts to obtain a resultant plurality of image parts in the first domain that comprise a resultant size different from the initial size. In a further example, a transform component of a system applies sparse matrix multiplication to each of first and second image parts.

Abstract: A method of implementing a two-dimensional Inverse Discrete Cosine Transform on a block of input data. The method includes 1) generating a performance array for the columns of the input data; 2) performing a column-wise IDCT upon the input data, the IDCT performed in accordance with cases given for each of the columns by the performance array; (3) generating a row performance offset for rows of the input data; and 4) performing a row-wise IDCT upon the result data from the performing of the column-wise IDCT.

Abstract: Fast transforms that use multiple scaled terms is disclosed. The discrete transforms are split into sub-transforms that are independently calculated using multiple scaling terms on the transform constants. The effect of the scaling for the transform coefficients may optionally be handled by appropriately scaling the quantization values or any comparison values. Further, optimal representations of the scaled terms for binary arithmetic are found. The resulting calculations result in fast transform calculations, decreased software execution times and reduced hardware requirements for many linear transforms used in signal and image processing application, e.g., the DCT, DFT and DWT.

Abstract: A high-speed inverse discrete cosine transformation method and apparatus are provided. All elements of a discrete cosine transformation (DCT) matrix for elements having a value other than 0 are searched for in a predetermined order when a total number of elements having a value other than 0 is not greater than a predetermined critical value. Two-dimensional (2D) IDCT is performed on the elements having a value other than 0. 2D IDCT is performed on the DCT matrix when the total number of elements having a value other than 0 is greater than the predetermined critical value.

Abstract: Many video processing applications, such as the decoding and encoding standards promulgated by the moving picture experts group (MPEG), are time constrained applications with multiple complex compute intensive algorithms such as the two-dimensional 8×8 IDCT. In addition, for encoding applications, cost, performance, and programming flexibility for algorithm optimizations are important design requirements. Consequently, it is of great advantage to meeting performance requirements to have a programmable processor that can achieve extremely high performance on the 2D 8×8 IDCT function. The ManArray 2×2 processor is able to process the 2D 8×8 IDCT in 34-cycles and meet the IEEE standard 1180-1990 for precision of the IDCT. A unique distributed 2D 8×8 IDCT process is presented along with the unique data placement supporting the high performance algorithm.

Abstract: Systems and methods are disclosed to perform fast discrete cosine transform (DCT) by computing the DCT in five stages using three coefficients, and scaling the outputs using a plurality of scaling coefficients.

Abstract: A system and method for carrying out a two-dimensional forward and/or inverse discrete cosine transform is disclosed herein. In one embodiment, the method comprises: (1) receiving multiple data blocks; (2) grouping together one respective element from each of the multiple data blocks to provide full data vectors for single-instruction-multiple-data (SIMD) floating point instructions; and (3) operating on the full data vectors with SIMD instructions to carry out the two dimensional transform on the multiple data blocks. Preferably the two dimensional transform is carried out by performing a linear transform on each row of the grouped elements, and then performing a linear transform on each column of the grouped elements. The method may further include isolating and arranging the two dimensional transform coefficients to form transform coefficient blocks that correspond to the originally received multiple data blocks. The multiple data blocks may consist of exactly two data blocks.

Abstract: An inverse discrete-cosine transform apparatus that is simple in structure and can yet output pixel data items different in resolution. The apparatus comprises eight inverse discrete-cosine transform multipliers 23, ten field, compression, inverse discrete-cosine transform multipliers 22, eight selectors 24, eight selectors 25, eight buffers 26, eight sign multipliers 27, a control section, eight adders 28, and eight buffers 29. The control section controls the selectors 24, selectors 25, buffers 26 and sign multipliers 27 in accordance with whether the input discrete-cosine block has been subjected to field division and where the discrete-cosine coefficients are located in the block. One of the values input to the selectors 24, selectors 25, buffers 26 and sign multipliers 27 is thereby selected. The value selected is output after added with the plus sign or the minus sign. The adders 28 add the values output from the selectors 24, selectors 25, buffers 26 and sign multipliers 27.

Abstract: A discrete cosine transformation apparatus comprises a transposition section that transposes input picture signal of N×N pixels in every N pixels between the one-dimensional processing and the two-dimensional processing and a transformation section that subjects an output of the transposition section to a discrete cosine transformation.

Abstract: A method and apparatus are disclosed for reducing aliasing between neighboring subbands in cascaded filter banks. An alias reduction filter bank is included to reduce the aliasing components between different subbands. Generally, the magnitude response and phase of the alias reduction filter bank is similar to the magnitude response of the synthesis filter bank of the first stage filter bank. The alias reduction filter bank filters and adds the signals from a set of M2 subbands from the M1 subbands of the first stage analysis filter bank. A higher frequency resolution is obtained after the alias reduction stage by a following analysis filter bank. The signals of these subbands are first fed into an alias reduction filter bank to reduce the aliasing.

Abstract: A method and apparatus for compression/decompression and filtering of a signal in which the apparatus has an input register (704) which receives the received signal, an output register (712) which transmits a processed signal and a distributed arithmetic processor (708) having a plurality of operational modes. The distributed arithmetic processor is coupled to the input register by an input path and is coupled to the output register by an output path. The apparatus also has a DCT butterfly processor (706) selectively switched into the input path in response to selection of a predetermined operational mode from the plurality of operational modes. An IDCT butterfly processor (710) is also selectively switched into the output path in response to the selection of one of the predetermined operational modes. Additionally, the apparatus selectively functions as a FIR filter with both the DCT butterfly processor (706) and IDCT butterfly processor (710) removed from the input and output paths.

Abstract: A system and method of a forward and/or inverse discrete cosine transform in a video system. In one embodiment, an array of DCT transform coefficients are converted to a two dimensional array of spatial data. The array of DCT transform coefficients are first operated upon by a pre-scale computation unit (implemented in either hardware or software) which multiplies a set of predetermined pre-scale constants with the input coefficients. The pre-scale constants multiplied by the input DCT coefficient matrix form a symmetric pre-scale array. Upon pre-scaling using the symmetric pre-scale factor array, an intermediary array is composed by performing intermediary calculations upon each column vector of the pre-scaled array. The output of this intermediary calculation is composed to form an intermediary array. Subsequently, a set of calculations are performed row-wise upon each row vector of the intermediary array to thereby form the output array of spatial data.

Abstract: A computational unit, or node, in an adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric FIR Filter, Symmetric FIR Filter, Complex Multiply/FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad IIR Filter, Radix-2 FFT/IFFT, Radix-2 DCT/IDCT, Golay Correlator, Local Oscillator/Mixer.

Abstract: Some embodiments of the invention provide a method of performing a Discrete Cosine Transform (“DCT”) encoding or decoding coefficients of a data array by (1) multiplying the coefficients by a scalar value before the encoding or decoding, and then (2) dividing the encoded or decoded coefficients by the scalar value. When used in conjunction with fixed-point arithmetic, this method increases the precision of the encoded and decoded results. In addition, some embodiments provide a method of performing a two-dimensional (2D) Inverse Discrete Cosine Transform (“iDCT”). This method splits a pre-multiplication operation of the iDCT into two or more separate stages. When used in conjunction with fixed-point arithmetic, this splitting increases the precision of the decoded results of the iDCT.

Abstract: Discrete Cosine Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the transform domain for enabling recursive merges and splits in transform domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. In the split transform process, whole transformed data is split using combinational processing into first and second transformed data halves in the transform domain as a true split. In the merge transform process, first and second transform halves are merged using combinational processing into a merged transformed data whole in the transform domain. In either case, time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole.

Abstract: The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.

Abstract: A fast and precise method to perform inverse and forward Discrete Cosine Transform (DCT) is disclosed. The method may be used for implementing a two-dimensional (2D) inverse or forward DCT that operates on an N×M coefficient block and has a higher accuracy than is specified by the IEEE 1180-1990 standard (for the inverse operation). The disclosed method comprises the following stages: based on integer operations, a fixed point one dimensional (1D) DCT may be performed on each row of an input coefficient block, an integer-to-single-precision floating point result conversion may be performed, and a single precision floating point 1D DCT may be performed on each column of the coefficient block resulting from the previous stages.

Abstract: Provided are a method, system and program for fractionally shifting input data subject to a first transform process without first applying an inverse transformation by using a second transform process. The second transform process applies a transformed matrix to the transformed data. At least one transformed matrix is provided in non-volatile storage, wherein each transformed matrix is generated by applying the first transform process to a fractional shift matrix operator. The input data that was transformed using the first transform process is received and the at least one transformed matrix is applied to the transformed input data to generate transformed data that represents fractionally shifted transformed output data.

Abstract: A method and system for processing data arriving from a bit-stream to perform numerical computations in a temporal order independent fashion. According to one embodiment, the method is applied to IDCT computations to allow processing of IDCT coefficients in the same order they are received from an MPEG bit stream. The coefficients are not required to be converted from scan order to array order before processing. This provides significant advantages in that it imposes minimal storage requirements for the coefficients and the coefficients are processed in scan order.

Abstract: A method and system for computing 2-D DCT/IDCT which is easy to implement with VLSI technology to achieve high throughput to meet the requirements of high definition video processing in real time is described. A direct 2-D matrix factorization approach is utilized to compute the 2-D DCT/IDCT. The 8×8 DCT/IDCT is computed through four 4×4 matrix multiplication sub-blocks. Each sub-block is half the size of the original 8×8 size and therefore requires a much lower number of multiplications. Additionally, each sub-block can be implemented independently with localized interconnection so that parallelism can be exploited and a much higher DCT/IDCT throughput can be achieved.

Abstract: The present invention provides an algorithm and hardware structure for numerical operations on signals that is reconfigurable to operate in a downsampling or non-downsampling mode. According to one embodiment, a plurality of adders and multipliers are reconfigurable via a switching fabric to operate as a plurality of MAAC kernels (described in detail below), when operating in a non-downsampling mode and a plurality of MAAC kernels and AMAAC kernels (described in detail below), when operating in a downsampling mode.

Abstract: The present invention relates to a DCT operator for compressing image data through dividing the image data into various frequency components by using a spatial correlation on a screen, particularly to be fit with a low-power required mobile video terminal. Therefore, the present invention provides a DCT operator, in which a range of DCT coefficients for a calculation is controllable among an entire DCT region, and also provides, in another embodiment, a 2D DCT device including a first 1D DCT operator for executing a 1D DCT operation in rows about input image data; a transposition memory for temporarily storing a result of the 1D DCT operator; a second 1D DCT operator for executing a 1D DCT operation in columns about the resultant data processed by the 1D DCT operation in rows and stored in the transposition memory; and a timing control logic unit for controlling operation of the first and second 1D DCT operators and the transposition memory according to a DCT block size control signal given from outside.

Abstract: A method in a signal processor for quantizing a digital signal is provided. A fixed-point approximation of a value X÷Q is generated, wherein X is a fixed-point value based on one or more samples in the digital signal, and wherein Q is a fixed-point quantization parameter. A correction is generated, and the approximation is modified with the correction.

Abstract: There is provided a DCT processor for performing at least one of DCT operation and inverse DCT operation for image data in unit blocks having different sizes. This DCT processor is provided with a bit slice circuit (102) for outputting, bit by bit, the pixel data inputted for each column or row; a first butterfly operation circuit (103) for subjecting the output data of the bit slice circuit (102) to butterfly operation; a ROM address generation circuit (104) for generating continuous ROM addresses; an RAC (105) for reading the data corresponding to the ROM addresses from ROMs (ROM0˜ROM7) and accumulating the data by accumulation circuits (51a˜51h); and a second butterfly operation circuit 106 for subjecting the output data of the RAC 105 to butterfly operation.

Abstract: In particular, the present invention relates to a method and system for improving the efficiency of computational processes and specifically multiply and accumulate (“MAC”) processes such as the DCT (“Discrete Cosine Transform”) and/or IDCT (“Inverse Discrete Cosine Transform”) using a performance optimized method and associated hardware apparatus.

Abstract: The present invention relates to a distributed arithmetic module employing a zero input detection circuit that reduces electric power consumption by avoiding unnecessary calculation. An apparatus for performing a discrete cosine transform (DCT) on a video signal, including; input unit for receiving the video signal in a block by block basis; discrete cosine transform (DCT) unit for receiving each image data block from the input unit and conducting a discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) operation on the received image data block to generate a transformed image data block containing N×M pixel value; zero input detect unit for determining whether pixel values of a current image data block are all “0” and generating a detection signal in order to bypass the DCT/IDCT performing on the current image block; and output unit for outputting the transformed image data block as a transformed video signal.

Abstract: The invention relates to an approximation of a DCT and a quantization which are to be applied subsequently to digital data for compression of this digital data. In order to improve the transform, it is proposed to simplify a predetermined transform matrix to require less operations when applied to digital data. In addition, elements of the simplified transform matrix constituting irrational numbers are approximated by rational numbers. These measures are compensated by extending a predetermined quantization to include the operations which were removed in the simplification of the predetermined transform matrix. The included operations are further adjusted to compensate for the approximation of elements of the simplified transform matrix by rational numbers. If the simplified transform matrix and the extended quantization are used as basis for implementation, a fast transform with a good resulting quality can be achieved.

Abstract: An efficient digital video (DV) decoder process that utilizes a specially constructed quantization matrix allowing an inverse quantization subprocess to perform parallel computations, e.g., using SIMD processing, to efficiently produce a matrix of DCT coefficients. The present invention utilizes a first look-up table (for 8×8 DCT) which produces a 15-valued quantization scale based on class number information and a QNO number for an 8×8 data block (“data matrix”) from an input encoded digital bit stream to be decoded. The 8×8 data block is produced from a deframing and variable length decoding subprocess. An individual 8-valued segment of the 15-value output array is multiplied by an individual 8-valued segment, e.g., “a row,” of the 8×8 data matrix to produce an individual row of the 8×8 matrix of DCT coefficients (“DCT matrix”).

Abstract: A method and circuit computes a Discrete Cosine Transform in a more efficient manner for improving the computation speed, thereby reducing the computation time and allowing a higher number of digital samples to be processed. The circuit provides a microcontroller that includes a parallel accumulation multiplier for performing a first transform of the input data. A further quantization step is then performed on the transformed data. Likewise, the method includes the first transform being computed by the parallel accumulation multiplier. A further quantization step is performed on the transformed data. In this respect, the method and circuit provides good performance in terms of compression rate.

Abstract: The present invention is embodied in a system and method for performing spectral analysis of a digital signal having a discrete duration by spectrally decomposing the digital signal at predefined frequencies uniformly distributed over a sampling frequency interval into complex frequency coefficients so that magnitude and phase information at each frequency is immediately available to produce a modulated complex lapped transform (MCLT). The system includes real and imaginary window processors and real and imaginary transform processors. The real and imaginary window processors receive the input signal and apply and compute butterfly coefficients for the real and imaginary parts of the signal to produce resulting real and imaginary vectors, respectively. The real and imaginary transform processors compute spatial transforms on the real and imaginary vectors to produce real and imaginary transform coefficient of the MCLT, respectively.

Abstract: An apparatus computes an inner product vector of a matrix and a vector. The matrix has a first set of coefficients and the vector has a second set of coefficients. At least one input register is used to store the second set of coefficients. A plurality of storage elements are used to store partial sums that are pre-calculated from the first set of coefficients of the matrix. The outputs of the at least one input register are used as the address inputs to the plurality of storage elements to select a subset of the partial sums. In addition, a select circuit is coupled to the storage elements' address lines to determine which row in the matrix the vector forms one element of the resultant inner product for that row. The subset of partial sums from the outputs of the storage elements are added in an adder circuit to create a summation output that presents the element of the inner product vector of the matrix multiplied by the vector.

Abstract: Data compressed according to a lossy DCT-based algorithm, such as the MPEG or MPEG2 algorithms, is decompressed according to a dynamically-selected set of DCT coefficients, with unused coefficients masked out. A macroblock of the data exhibiting little motion is decompressed with a small subset of DCT coefficients, while a macroblock exhibiting more motion is decompressed using a larger subset of DCT coefficients up the full set of DCT coefficients. Average computational complexity is thus kept low, enabling the use of inexpensive equipment, while degradation is minimized.

Abstract: To decrease the number of arithmetical operations in a filtering process for decoding a digital signal and reduce a cost required for decoding. A filtering method for use in decoding a digital signal from a frequency domain to a time domain includes: a first step of multiplying an input data stream and a transformation matrix that is decomposed into a sparse matrix from an inverse MDCT transformation matrix for making the inverse MDCT transformation of the input data stream composed of a plurality of data blocks, and has a smaller size than the inverse MDCT transformation matrix, to acquire an output data stream composed of a plurality of data blocks; a second step of storing predetermined data contained in each data block of the output data stream; and a third step of generating the digital signal in the time domain on the basis of each data block acquired at the first step and the predetermined data stored at the second step in processing the former stage data block.

Abstract: A circuit arrangement and method for performing the 2-D DCT. An input permutation processor reorders input samples, constructing a logical matrix of input samples. A plurality of 1-D DCT processors are arranged to receive the reordered data and apply the 1-D DCT along extended diagonals of the matrix. The output polynomials from the 1-D DCT processors are provided to a polynomial transform processor, and the output data from the polynomial transform processor are reordered, by an output permutation processor. The 1-D DCT processors and polynomial transform are multiplier free, thereby minimizing usage of FPGA resources in an FPGA implementation.

Abstract: To simplify the structure of a discrete cosine transformation circuit for use in an audio recording/reproducing device. A selector can desirably supply a value “0” to an input terminal B of the adder/subtracter (80), so that an input to the adder/subtracter (80) via an input terminal A can be passed intact therethrough to be fed back thereto via the input terminal B. With this arrangement, direct connection between a multiplier to the input terminal B is unnecessary, and a selector which conventionally selects the direct connection and a loop back is also unnecessary. Further, since a selector (72) relating to proportional coefficients can desirably supply a value “1” to the multiplier (66), operand data inputted to the multiplier (66) can be supplied intact to the subsequent adder/subtracter (80) through the multiplier (66).

Abstract: A linear transform apparatus for implementing a linear transform on input data values to produce linear transformed output data, the apparatus comprising: input means for inputting input data values one after another to each of a series of multiplication means; a series of multiplication means interconnected with the input means for multiplying a current input data value by a constant to produce a current multiplier output; an interconnection network interconnecting the series of multiplication means to predetermined ones of a series of signed accumulator means; a series of signed accumulator means each interconnected to the interconnection network, each of the signed accumulator means producing an intermediate accumulator output by accumulating a corresponding one of the current multiplier outputs with a corresponding previous intermediate accumulator output, each of the signed accumulator means outputting the intermediate accumulator output as a corresponding linear transformed output data value.

Abstract: The invention comprises an efficient system and method for performing the modified discrete cosine transform (MDCT) in support of time-domain aliasing cancellation (TDAC) perceptive encoding compression of digital audio. In one embodiment, an AC-3 encoder performs a required time-domain to frequency-domain transformation via a MDCT. The AC-3 specification presents a non-optimized equation for calculating the MDCT. In one embodiment of the present invention, an MDCT transformer is utilized which produces the same results as carrying out the calculations directly as in the AC-3 equation, but requires substantially lower computational resources. Because the TDAC scheme requires MDCT calculations on differing block sizes, called the long and short blocks, one embodiment of the present invention utilizes complex-valued premultiplication and postmultiplication steps which prepare and arrange the data samples so that both the long and short block transforms may be computed with a computationally efficient FFT.

Abstract: A method and apparatus for compression/decompression and filtering of a signal in which the apparatus has an input register (704) which receives the received signal, an output register (712) which transmits a processed signal and a distributed arithmetic processor (708) having a plurality of operational modes. The distributed arithmetic processor is coupled to the input register by an input path and is coupled to the output register by an output path. The apparatus also has a DCT butterfly processor (706) selectively switched into the input path in response to selection of a predetermined operational mode from the plurality of operational modes. An IDCT butterfly processor (710) is also selectively switched into the output path in response to the selection of one of the predetermined operational modes. Additionally, the apparatus selectively functions as a FIR filter with both the DCT butterfly processor (706) and IDCT butterfly processor (710) removed from the input and output paths.

Abstract: An apparatus for a fast inverse discrete cosine transform (IDCT) by processing only non-zero IDCT input data including non-zero feeding unit connected to each row-column decomposed one dimensional IDCT input for feeding only non-zero input data during each cycle. The first 1-D IDCT and the second 1-D IDCT have the same structure, and 1-D IDCT core with a non-zero feeding unit at its front end. The 1-D IDCT core of the present invention is for performing IDCT operation based on the input scaling method, and the operation of the IDCT core consists of a cosine kernel selection operation using a received non-zero input, multiplication-and-addition, and a storing operation. The non-zero feeding unit for the first 1-D IDCT and the second one are different in their configuration. There are two different methods for implementing the first 1-D IDCT, a stored input feeding method and a zigzag scanned input feeding method.

Abstract: A data processing device provides for registers which can be formatted as segments containing numbers to which operations can be applied in SIMD fashion. In addition it is possible to perform operations which combine different segments of one register or segments at different positions in the different registers. By providing specially selected it is thus made possible to perform multidimensional separable transformations (like the 2-dimensional IDCT) without transposing the numbers in the registers.

Abstract: A method and apparatus for efficiently computing an Inverse Discrete Cosine Transform (IDCT).

Abstract: A signal processing device and a signal processing method can reduce the work area and realize a higher speed for arithmetic operations by reducing the number of multiplications and additions when performing MDCT operations, IMDCT operation and/or transforming code strings between different coding system.