Abstract: A linear transform system (18) for decoding video data is provided. The system (18) includes inputs (50, 52, 54, 56, 58, 60, 62, 64) connected in series to a circuit (40) for implementing a decoding algorithm that includes a multiplication circuit stage (42, 44, 46) having a multiple output scaler structure (82, 84, 86). A bit-serial operator stage (48) is connected in series with the multiplication circuit stage (42, 44, 46). The bit-serial operator stage (48) is coupled to a plurality of outputs (66, 68, 70, 72, 74, 76, 78, 80) that generate decoded video data.

Abstract: An invention about inverse discrete cosine transformer of MPEG decoder is disclosed. By using the symmetry of N×N IDCT kernel matrix, the invention reduces the number of multipliers to N/4, the number of accumulators to N/2 in IDCT block without loss of decoding speed. This invention include memory parts, N/4 multipliers, M/2 accumulators and transposing means. Memory parts store absolute values of kernel matrix of inverse discrete cosine transform. N/4 multipliers receive elements of discrete cosine transform coefficient matrix or of transpose matrix of one-dimensional inverse discrete cosine transform coefficient matrix, as their multiplicand input, and elements of kernel matrix of inverse discrete cosine transform as their multiplier input. N/2 accumulators accumulate data outputted from multiplier.

Abstract: Methods and apparatus for performing a fast two-dimensional inverse discrete cosine transform (IDCT) in a media processor are disclosed. A processor receives discrete cosine transform data and combines, in a first stage, the discrete cosine transform data with a first set of constants. In a media processor with a partitioned SIMD architecture, the discrete cosine transform data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction. The output is transposed in a second stage and combined with constants in a third stage to obtain the pixel information of an image.

Abstract: There is disclosed a discrete cosine transform circuit for use in a voice recording/reproducing device to solve problems that RAM in which data is stored is frequently accessed and that the power consumption is large. In discrete cosine transform, an algorithm can be constituted to include four or less items of operand data in one operation equation. Correspondingly, four registers 62-1 to 62-4 are arranged on the output side of RAM 60. The discrete cosine transform includes a predetermined regularity. For example, a plurality of operation equations using the same operand data are included in the processing. By continuously processing all of the operation equations, the data read into the registers 62-1 to 62-4 can be reused without being overwritten in another processing, so that accesses to RAM 60 can be suppressed.

Abstract: In order to execute a rapid and effective DCT and IDCT and embody DCT and IDCT in one processor, in an inventive DCT/IDCT processor, an input multiplexer selects DCT or IDCT coefficients and transfers the coefficients to a matrix multiplier, and DCT/IDCT deciding unit within the matrix multiplier controls a flow of the DCT and IDCT coefficients. An output multiplexer decides an output of the DCT and the IDCT, to thereby embody the DCT and the IDCT in one processor, and perform the DCT and the IDCT at a high speed by reducing the number of multiplication calculation, namely through a decrease of the calculation number.

Abstract: A reversible Discrete Cosine Transform (DCT) is described. The reversible DCT may be part of a compressor in a system. The system may include a decompressor with a reversible inverse DCT for lossless decompression or a legacy decompressor with an inverse DCT for lossy decompression.

Abstract: A method and apparatus is presented for video image compression using a unique operand decomposition technique combined with an innovative data scatter and retrieve process. This combination of features allows the use of single ported RAM structures where multiported RAMS would normally be used, such as when retrieving two operands in the same time cycle. As applied to the Discrete Cosine Transformation this method and appatatus additionally allows elimination of the usual prior art use of a separate transpose matrix buffer. The elimination of the separate transpose matrix buffer is accomplished by combining the transpose matrix intermediate results memory storage with the memory buffer used for the other intermediate results in a double buffer system.

Abstract: An inverse discrete cosine transforming (IDCT) system for a digital television receiver performing a variable length decoding and an inverse quantization of an applied bit stream and an IDCT with respect to inversely quantized DCT coefficients, including an integrated IDCT part which performs an inverse discrete cosine transformation of standards DCT coefficients inversely quantized or high definition DCT coefficients inversely quantized.

Abstract: To achieve bi-directional transformation by using a single simply-structured discrete cosine transformation circuit for use in an audio recording/reproducing device. There is provided a circuit which comprises a RAM 60, a ROM 68, a multiplier 66, and an adder/subtracter 80 and is capable of performing inverted transformation of a discrete cosine transformation. The multiplier 66 multiplies operand data stored in the RAM 60 by a proportional coefficient stored in the ROM 68. The adder/subtracter 80 add/subtracts outputs of the multiplier 66. This circuit is also able to perform a characteristic operation in a forward direction, such as addition or subtraction using intact base data. Specifically, data before conversion is stored in the RAM 61, and one of them is supplied to the adder/subtracter 80 via an input terminal A.

Abstract: A two-dimensional discrete cosine transform processor (two-dimensional DCT processor) includes two one-dimensional DCT circuits and a transposition memory interposed therebetween. Each of the two one-dimensional DCT circuits includes a butterfly operation circuit and a distributed arithmetic circuit at the subsequent level. Partial sums of vector inner products based on a constant matrix obtained by multiplying respective elements of a discrete cosine matrix by frequency-depending weighting according to human visual sense are stored in ROMs included in the distributed arithmetic circuit, and the contents of the ROMs are used to obtain a one-dimensional DCT result with weighting given. In this manner, arbitrary weighting can be given to the transform result without using a multiplier. Thus, for example, in a compressing and coding system for image data, the compression efficiency can be improved as compared with the case where weighting is not given to the transform result.

Abstract: Methods and apparatus for performing a fast two-dimensional inverse discrete cosine transform (IDCT) in a media processor are disclosed. A processor receives at least one input component representing discrete cosine transform data and combines, in a first stage, the at least one input component with a first set of constants. In a media processor with a partitioned SIMD architecture, the input data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction. The output is transposed in a second stage and combined with constants in a third stage.

Abstract: Methods and apparatus for performing a fast two-dimensional inverse discrete cosine transform (IDCT) in a media processor are disclosed. A processor receives discrete cosine transform data and combines, in a first stage, the discrete cosine transform data with a first set of constants. In a media processor with a partitioned SIMD architecture, the discrete cosine transform data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction. The output is transposed in a second stage and combined with constants in a third stage to obtain the pixel information of an image.

Abstract: An orthogonal transform apparatus has: orthogonal transform circuit for performing n-dimensional s-order (n and s are natural numbers) orthogonal transform, modified-information control circuit for performing control in accordance with modified information for outputting n-dimensional m-order data as n-dimensional p-order data (m and p are natural numbers), and rearrangement circuit for performing the following in accordance with the control by said modified-information control circuit: (1) m-p data values from the high-order side out of m-order input data values are set to 0 when m is equal to s and m is larger than p, p-m data values are added to the high-order side among m-order input data values to rearrange the data values when m is smaller than p, or data values are left as they are when m is equal to p; (2) the data values in said Item (1) are rearranged after discarding m-s data values from the high-order side of said m-order input data values before rearranging the data values in said Item (1) whe

Abstract: This arithmetic unit for carrying out partial sum of products for transform operations such as discrete cosine transform is provided which includes a plurality of first units for calculating in parallel sums of and/or differences between a plurality of input variables or sums of and/or differences between a plurality of values obtained by multiplying said plurality of input variables by a constant. The arithmetic unit also includes a processing unit having a plurality of shift units for shifting outputs from said plurality of first units by respectively predetermined numbers of digit-shifts and a plurality of second units for calculating concurrently sums of outputs from said plurality of shift units. The arithmetic can be used, for example, as a high speed discrete cosine unit, a high speed Hartley transform unit or a high speed Hough transform unit.

Abstract: A method of implementing a dual-mode audio decoder and filter is provided. The inverse modified discrete cosine transform (IMDCT) method and circuit for a dual-mode audio decoder perform the IMDCT with respect to a signal encoded using either the MPEG or Dolby AC-3 standard by utilizing a shared fast Fourier transform (FFT) circuit thereby simplifying the necessary hardware construction. Also, the number of IMDCT outputs used for windowing is reduced by utilizing the properties of the IMDCT outputs of the MPEG bit stream and thus the size of memory necessary for storing the IMDCT outputs is reduced.

Abstract: An apparatus and a method for performing discrete cosine transformation (DCT) are presented. The apparatus includes an arithmetic circuit interconnected with a transpose memory. The arithmetic circuit includes a combinatorial circuit for calculating a DCT without using an intermediate clocked storage unit. The combinatorial circuit includes a predetermined number of sequentially arranged stages for implementing the DCT. The apparatus may optionally include a controller for controlling operation of the apparatus and a multiplexer for multiplexing data input to the apparatus and data from the transpose memory. An apparatus and a method for performing inverse discrete cosine transformation (IDCT) are also presented.

Abstract: A set of scaled weighing coefficients is employed in the intrinsic multiplication stage of a six-stage DCT/IDCT fast algorithm for one of two one-dimensional DCT/IDCT operations so that a corresponding stage of the DCT/IDCT fast algorithm for the other one of the one-dimensional DCT/IDCT operations can be omitted. Accordingly, the number of multiplication operations for two-dimensional DCT/IDCT processing is reduced in order to achieve a higher processing speed.

Abstract: One multiplier 13 operated at a normalized frequency 4 is provided to multiply the elements of DCT transformation coefficients and the elements of input data, and the multiplication results are added by a cumulative adder 15 to determine cumulative addition results corresponding to the sum (x0+x7) and the difference (x0−x7) of a pair of elements (x0, x7) of data to be outputted from a one-dimensional DCT operation circuit 1. The paired cumulative addition results are added and subtracted by an adder 17 and a subtracter 18, respectively, to determine the elements (x0, x7). The operations are performed specific times the number of which is one half of the number of elements of a column of the matrix of the input data to determine the elements of a column of the matrix of the output data and are performed specific times the number of which is equal to the number of elements of a row of the matrix or the input data to determine all the elements of the matrix of the output data.

Abstract: A reversible eight-element discrete cosine transform coding system which provides transform values near to transform values of the original eight-element discrete cosine transform. In a 4.times.4 matrix transform which appears when an eight-element discrete cosine transform is decomposed in accordance with a fast calculation method, transform coefficients (X1, X7, X3, X5) are separated into (X1, X7) and (X3, X5), which are quantized individually making use of the fact that, if (X1, X7) are determined, then values which can be taken by (X3, X5) are limited. (X1, X7) are quantized with step sizes k1, k7 by linear quantizers to obtain quantization values (Xq1, Xq7). Meanwhile, (X3, X5) are divided into global signals and local signals, and the global signals are quantized with step sizes L3, L5 by linear quantizers while quantization values of the local signals are determined using a table. The quantization values are added by adders to obtain quantization values (Xq3, Xq5) of (X3, X5).

Abstract: A method and device compute the inverse discrete cosine transform (IDCT) in a block based motion compensated digital video decoder, such that the computational complexity is dependent on syntax cues from an input block, and the resulting overall complexity is greatly reduced on average. The method and device provide a means for selecting a set of pruned IDCT algorithms based on the statistics of generic coded video data. The classification of input IDCT blocks uses the last non-zero coefficient obtained as a by-product of decompression and dequantization. The mapping from the last non-zero coefficient to a corresponding set of separable one-dimensional IDCT algorithms is performed efficiently with the careful consideration of memory requirements, mapping complexity, and pruned IDCT-complexity tradeoffs.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU.

Abstract: An 8.times.8 two-dimensional discrete inverse cosine transform circuit includes two row arithmetic sections each of which implement an 8-point one-dimensional inverse discrete cosine transform in a row direction, a replacement section which replaces the arithmetic results of the row arithmetic sections with replacement data, and two column arithmetic sections each of which receive parts of the replacement data from the replacement section and implement an 8-point one-dimensional inverse discrete cosine transform in a column direction. Each of the arithmetic sections include a 16-bit four parallel adder and subtracter and a 16-bit four parallel multiply-accumulate unit with polarity symmetric rounding function.

Abstract: A method is provided for performing a fast Discrete Cosine Transform (DCT) and a fast Inverse Discrete Cosine Transform (IDCT) in a software implementation. The method provided exploits symmetries found in both the DCT and IDCT. As a result of the symmetries found in the DCT and IDCT, both transforms may be performed using a combination of look-up tables and butterfly operations, thus employing only a small number of additions and subtractions and no multiplications. Furthermore, there is provided an aspect of the present invention which exploits the excess precision available in current central processing units (CPUs) relative to the precision required by the DCT and IDCT calculations.

Abstract: A two-dimensional array transposition circuit having a small circuit scale and accordingly having a small power consumption includes a memory cell array capable of storing a two-dimensional array and an address translation circuit receiving an address signal and generating a row address signal and a column address signal for specifying a memory cell of the memory cell array via a row decoder and a column decoder. The address translation circuit generates, when one two-dimensional array is written into the memory cell array, a row address signal and a column address signal successively such that an order of writing is according to one of an order giving priority to a row direction and selecting a memory cell and an order giving priority to a column direction and selecting a memory cell and generates, when the two-dimensional array is read from the memory cell array, a row address signal and a column address signal successively such that an order of reading is according to the other order.

Abstract: The present invention is embodied in a system and method for fast computation of a spatial transform of an input signal. The computation system includes a window processor having a window function and an operator having a first set of weights. The window processor receives the input signal as sample blocks and the operator is adapted to apply butterfly coefficients determined by the window function to produce resulting vectors. Also, the window processor maps the input signal to a cascade of butterflies using the first set of weights and reorders the cascade of butterflies. A transform processor having a transform module computes a spatial transform from the reordered cascade of butterflies to produce transform coefficient. A coefficient combination operator combines the transform coefficients to produce an encoded output corresponding to the input signal.

Abstract: A method and apparatus for performing matrix multiplication used in image processing is described. A modified Booth encoding method is used to reduce the logic circuitry in processor modules used for calculating forward and inverse discrete cosine transforms. A set of products of image values and matrix coefficients are generated and provided to a set of multiplexers. The multiplexers provide preselected products to a set of accumulators. The accumulators combine the products to generate the set of transform coefficients at the accumulator outputs.

Abstract: A memory, which consumes less electric power and has a longer life, stores a redundant binary code produced by replacing each digit of data in binary representation, with a separate 2-bit string allocated to a value which the digit can take. If a value to be output before or after a value is output from the memory is known, a redundant binary representation and a redundant binary code associated therewith are determined such that the number of transitions can be reduced. Thus, a memory which consumes less electric power and has a longer life can be provided.

Abstract: A Discreet Cosine Transform (DCT) circuit consisting of a pipe-lined Single Instruction stream, Multiple Data stream (SIMD) processor array, a transpose memory and a control circuit is provided by exploiting the row-column decomposition method, wherein the processor array is capable of computing one dimensional DCT. In an N-point DCT application, the processor array consists of N PEs (processor elements), each of which can compute a N/2-point inner product. Instead of a conventional Multiplexed Analogue Components (MAC) design, the present DCT circuit computes the N/2-point inner product by a word-parallel bit-serial method, which uses N/2 Read Only Memory (ROM) tables, a Wallace tree and one carry propagate adder. This implementation achieves cost-saving and better timing in comparison to a MAC design. Meanwhile, the circuit also has the advantages of simple data routing, regular structure and modular design, and is suitable for Very Large Scale Integration (VLSI) implementation.

Abstract: An arithmetic unit for carrying out partial sum of products for transform operations such as discrete cosine transform is provided which includes a plurality of first units for calculating in parallel sums of and/or differences between a plurality of input variables or sums of and/or differences between a plurality of values obtained by multiplying said plurality of input variables by a constant. The arithmetic unit also includes a processing unit having a plurality of shift units for shifting outputs from said plurality of first units by respectively predetermined numbers of digit-shifts and a plurality of second units for calculating concurrently sums of outputs from said plurality of shift units. The arithmetic can be used, for example as a high speed discrete cosine unit, a high speed Hartley transform unit or a high speed Hough transform unit.

Abstract: Devices for computing discrete cosine transform, inverse discrete cosine transform or reduced ones, which require fewer transistors and less chip area, and which operate at a higher speed than those of the prior art. For example, the DCT/IDCT processor in the present invention essentially includes a matrix summation device and a plurality of shift adders. The matrix summation device computes a plurality of binary vectors from bits of an input vector, respectively for each term of an output vector. The shift-adding means respectively compute the terms of the output vector by sequentially left-shifting and adding the corresponding binary vectors.

Abstract: An integrated circuit data processing structure and method for performing a discrete cosine transform (DCT) makes the correspondence between a table f(x,y) of N.times.N data and a table F(u,v) of N.times.N coefficients according to the following relation: ##EQU1## The innovative structure uses: a memory containing a data table;a memory of the productsP=.vertline.cos[n(x,u).pi./2N].multidot.cos[n(y,v).pi./2N].vertline., with:p(x,u)=Sgn[p(x,u)].multidot..vertline.cos[n(x,u).pi./2N].vertline.p(y,v)=Sgn[p(y,v)].multidot..vertline.cos[n(y,v).pi./2N].vertline.where n(x,u) and n(y,v) are integers ranging from 1 to N-1;a table of the signs of p(x,u) and p(y,v) and values of n(x,u) and n(y,v) addressing the product memory (3);a coordinate generator sequentially providing value pair (u,v) and, for each pair (u,v), all the values of pair (x,y);a multiplier calculating the product of P by a data combination of the data memory; andan accumulator of the results of the multiplication.

Abstract: A data processing system (100) of the present invention analyses input data (10) for statistical similarities in time and determines processing steps depending on the analysis. The system (100) transfers a first data set (12) which changes at every time transition (i-1) to i into a second data set (13) to output sets (22 and 23) by a transfer function H. According to a method of the present invention, the number of calculation instructions h(n) which are performed is established by comparing consecutive old input data (12) and new input data (13). The transfer function H is thereby simplified and the number of executed instructions optimized.

Abstract: The invention provides a high speed two-dimensional discrete cosine transform circuit which can reduce the number of addition operations for rounding to one time. The two-dimensional IDCT circuit calculates M.times.N-point two-dimensional inverse discrete cosine transforms wherein M.times.N is equal to 2.sup.2n, and includes an M.times.N two-dimensional IDCT operator for calculating two-dimensional inverse discrete cosine transforms as matrix vector products of a transform matrix of MN rows and MN columns and MNth-order input vectors, a shift operator for shifting results of the calculation of the M.times.N two-dimensional IDCT operator rightwardly, and an adder for adding 2.sup.n-2 to a discrete cosine coefficient from among discrete cosine transform coefficients to be inputted to the M.times.N two-dimensional IDCT operator. An output signal of the shift operator is outputted as a circuit output signal of the two-dimensional IDCT circuit.

Abstract: When a weighted calculation in which a cosine-transformed coefficient is multiplied with diagonal matrixes from the right and left direction is carried out, a new transform matrix is obtained by previously multiplying a weighting diagonal matrix and the cosine transform matrix and input data is transformed by using the new transform matrix. Thus, a circuit scale can be reduced, the processing steps can be simplified, and the cost can be reduced. When a weighted calculation in which a cosine transformed coefficient C is multiplied with a diagonal matrix W from the right and left directions is carried out, the weighted cosine transform is carried out by using a new transform matrix Fw which results from previously multiplying the weighting diagonal matrix W and the cosine transform matrix F.