Abstract: The present invention relates to a bank of digital filters that can be cascade connected. It also relates to a reception circuit comprising such a bank of cascaded filters. With the digital filter being sampled at a given sampling frequency Fs, the bank of cascadable digital filters has: at the input, a frequency transposition circuit (31) for the digital signal. A polyphase filter (30) receives as input the frequency-transposed digital signal clocked at the sampling frequency Fs. The polyphase filters has an FFT filter (32) having a number N of points. The output of the filtering device retains a given number of outputs (36) of the FFT filter (32) so that the information bit rate at the output of the device is equal to the information bit rate at the input. The invention is particularly applicable to heterodyne-type radar signal receivers.

Abstract: A fast Fourier transform circuit includes a computation component, an extraction component and a setting component. The extraction component, at each step of the computation, extracts, from computation result data points calculated by the computation component, data in a pre-specified range with a number of bits the same as a predetermined number of bits, which is an effective range for a butterfly computations. The setting component sets the data points of the predetermined number of bits which have been extracted by the extraction component to serve as input data when butterfly computations of a next step are to be performed by the computation component.

Abstract: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).

Abstract: An efficient method of generating a bit-reverse index array in real time without performing any bit manipulation for a wireless communication system.

Abstract: We disclose an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. An input module combines a plurality of inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator generates multiplicands. At least two complex multiplier modules perform complex multiplications with at least one of the complex multiplier modules receiving an output from the input module. A map module receives outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs received to generate multiple outputs. Finally, an accumulation module receives and performs an accumulation task on each of the multiple outputs of the map module thereby generating a corresponding number of multiple outputs.

Abstract: Various approaches for performing a fast-Fourier transform (FFT) of N input data elements using a radix K decomposition of the FFT are disclosed (K>=2, and N>=8). In one approach, N/K input data elements are written to respective ones of K addressable memories, and N/K*logK N passes are performed on the input data. Each pass includes reading K data elements in parallel from the K addressable memories using the respectively generated addresses, the K data elements being in a first order corresponding to the respective memories; permuting the first order of K data elements into a second order of K data elements; performing a radix K calculation on the second order of K data elements, resulting in corresponding result data elements in the second order; permuting the second order of K result data elements into the first order; and writing the K result data elements in parallel to the corresponding K addressable memories using the respective addresses.

Abstract: The invention comprises an encoder for encoding a stegotext and a decoder for decoding the encoded stegotext, the stegotext being generated by modulating the log power spectrogram of a covertext signal with at least one key, the or each key having been added or subtracted in the log domain to the covertext power spectrogram in accordance with the data of the watermark code with which the stegotext was generated, and the modulated power spectrogram having been returned into the original domain of the covertext. The decoder carries out Fast Fourier Transformation and rectangular polar conversion of the stegotext signal so as to transform the stegotext signal into the log power spectrogram domain; subtracts in the log power domain positive and negative multiples of the key or keys from blocks of the log power spectrogram and evaluates the probability of the results of such subtractions representing an unmodified block of covertext in accordance with a predetermined statistical model.

Abstract: Embodiments of a hardware accelerator having a circuit configurable to perform a plurality of matrix operations and Fast Fourier Transforms (FFT) are presented herein.

Abstract: The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.

Abstract: A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the CCK modulation using FFT structure in the OFDM module, and embodying the suboptimal and the optimized CCK modulations using FFT structure in OFDM module. CDMA, OFDM, CCK modules may be integrated as single module.

Abstract: A motion estimator 50 for image processing finds a motion vector from a search area in a reference picture to a source macroblock in a source picture by finding a maximum of a 2-dimensional normalised cross-correlation surface between the source macroblock and a portion of the reference search area using a transform domain.

Abstract: The present invention relates to a complex multiplier and a twiddle factor generator.

Abstract: The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising: distributing the plurality of elements of the array in a first dimension across the plurality of nodes of the computer system over the network to facilitate a first one-dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing the one-dimensional FFT-transformed elements at each node in a second dimension via “all-to-all” distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FFT on elements of the array re-distributed at each node in the second dimension, wherein the random order facilitates eff

Abstract: Provided is an apparatus and method for comparing structures of proteins by extracting main axes of the proteins using principal components analysis (PCA), dividing regions using grids into voxels for precise structure alignment, and placing the proteins respectively in the regions to calculate a similarity between the proteins by autocorrelation. The apparatus for comparing protein structures using principal components analysis (PCA) and autocorrelation includes: a PCA calculator for receiving a query protein for extracting a main axis of the query protein; a voxel generator for receiving information about the main axis from the PCA calculator and dividing a predetermined region using a grid to determine whether the divided region is occupied by the query protein for generating voxels of the query protein; and a comparison processor for performing an autocorrelation calculation between voxels of one protein and voxels of the other protein that are generated by the voxel generator.

Abstract: Disclosed is a transmitting and receiving method for reducing a time-varying channel distortion in an orthogonal frequency division multiplex (OFDM) system. In the present invention, the transmitter defines M sub-channels in one data group, mathematically analyzes a change of channel for each path causing a time-varying channel distortion in a high-speed mobile environment by approximation, calculates a weight value based on the mathematical analysis and assigns the calculated weight value to transmit data of each sub-channel. Subsequently, the receiver combines the signals of these M sub-channels and demodulates the combined signals. Accordingly, the present invention greatly reduces a distortion caused by the time-varying channel to improve a bit error rate and a channel estimation performance.

Abstract: A FFT/IFFT processor and an intellectual property (IP) builder are disclosed. Which include a circuit applying the mixed-radix algorithm and a parametric graphic user interface (GUI). The circuit is for a parametric IP builder. The parametric GUI is for user to complete hardware design and functional test of FFT/IFFT processor by software. The IP builder could accelerate the progress of processor design and SOC integration.

Abstract: A method encodes a sequence of blocks of input bits to be transmitted over a wireless channel. Each block of input bits is converted to a codeword, and each codeword is mapped to multiple sub-blocks of complex numbers. Each sub-block is multiplied by a disambiguating spreading transform to obtain a sub-block of transformed symbols, which can be modulated and transmitted to a receiver, where each received block is demodulated to a block of complex numbers, which are partitioned into sub-blocks. The sub-block of complex numbers are converted to a set of likelihood ratios that correspond to decoded codewords. The input bits can be decoded unambiguously even if only one of the blocks of symbols corresponding to the block of input bits is received correctly.

Abstract: A butterfly processor architecture including a single high speed multiplier unit and two adder/subtracter units structured to efficiently perform radix-2 decimation-in-time (DIT) butterfly operations is disclosed. The computations for windowing operations, FFT operations, and IFFT operations may be realized in terms of butterfly operations. Therefore, the butterfly processor architecture may be used to perform the computations of a plurality of signal processing operations. The butterfly operations may be performed in-place whereby the results of each operation may be stored in the same location in memory where the inputs for each operation were retrieved. Performing the butterfly operations in-place ensures that the memory may be big enough to hold one frame of data.

Abstract: An approach is provided for reducing latency in fast Fourier transformation (FFT) related systems, such as orthogonal frequency division multiplexing (OFDM) systems. In a first processing direction, an interleaving processing is performed to obtain an interleaved data sequence which is then subjected to an inverse fast Fourier transformation processing, wherein the interleaving processing comprises a bit re-ordering processing of the inverse fast Fourier transformation processing. In an opposite second processing direction, a fast Fourier transformation processing is performed with a bit-reversed output data sequence which is then subjected to a de-interleaving processing, wherein the de-interleaving processing comprises a bit re-ordering processing required for re-ordering said bit-reversed output data sequence. The combined interleaving/de-interleaving and reordering processing leads to a reduced latency and saves memory space.

Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

Abstract: Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.

Abstract: The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising: distributing the plurality of elements of the array in a first dimension across the plurality of nodes of the computer system over the network to facilitate a first one-dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing the one-dimensional FFT-transformed elements at each node in a second dimension via “all-to-all” distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FFT on elements of the array re-distributed at each node in the second dimension, wherein the random order facilitates eff

Abstract: Dislosed is a fast Fourier transform device of a wireless LAN orthogonal frequency division multiplexing (OFDM) system. The device comprises: an FFT/IFFT unit constituted with one hardware, for performing a fast Fourier transform (FFT) and an inverse fast Fourier transform (IFFT); and a control signal input unit for outputting a control signal for controlling an operation of the FFT/IFFT unit.

Abstract: A fast Fourier transform (FFT) circuit from which unneeded butterfly computation modules can be effectively pruned for specific applications. Each module that is not needed is pruned by injecting zero signals into it, thereby minimizing the power dissipated in the pruned circuit. A multiplexer integrated into each butterfly module output (or input) line allows the line signal to be either forced to zero or allowed to carry a nonzero signal.

Abstract: The invention includes apparatus and methods for high-speed calculation of non-linear functions based upon a shifted adder and a offset generator. Various implementations may preferably include a input preprocessor and/or an output post processor. The invention includes a family of core cells built from instances of these calculators providing an upward, functionally compatible, extension to a family of Application Specific Integrated Circuit (ASIC) core cells. All of these core cells consistently provide the ability to perform high speed DSP tasks including Fast Fourier Transforms (FFTs), Finite Impulse Response (FIR) filters and Infinite Impulse Response (IIR) filters. The core cells built from the calculators can concurrently perform many non-linear function calculations. The core cells can switch between tasks every clock cycle.

Abstract: When a three-dimensional Fourier transform is performed on the data x (i, j, k), the Fourier transform is performed on each two-dimensional plane formed by a first dimension and a second dimension (two-dimensional array defined by i and j). Since data is stored in a continuous area in the direction in which index i expressing the first dimension continues, the transform of the first dimension is performed such that i can be continuous. When the Fourier transform of the second dimension expressed by j is performed, data is accessed such that i can continuously changes not by continuously changing j. The Fourier transform of the third dimension is performed with i continuously changed on each plane defined by i and k. Reversed bits are obtained by simultaneously exchanging the first dimensions and the second dimensions.

Abstract: Output terminal 340 extracts specific subcarrier data assigned by a base station from at least one of a plurality of butterfly operation sections provided in output terminal 340. The butterfly operation sections in first node 320, second node 330, and output terminal 340 make only butterfly operation sections relating to extraction of the specific subcarrier data perform the butterfly operation. Thereby, unnecessary butterfly operation performed in butterfly operation unit 300 is omitted.

Abstract: A Fast Fourier Transform (FFT) arrangement for use in those situations in which not all of the outputs are desired is controlled in such a fashion that at least those multiplications (and possibly those additions) are not performed which do not contribute toward the desired outputs. The technique is usable in those situations in which the desired output signals are noncontiguous, or are in noncontiguous bins. The technique includes signal preprocessing in which the indices are adjusted so that the index for a particular stage points to those butterflies of the previous stage which contribute toward its output. The FFT is performed on the indexed data. In one embodiment, a pipelined FFT processor is controlled in a corresponding manner.

Abstract: A data transform system performs FFT and IFFT computations with respect to N data points. The data transform system performs radix-R (R is an integer) butterfly computation in parallel by use of M arithmetic elements. Serial and parallel computation structures a recombined to provide a system that provides for optimal trade-off between system speed and the size of the resulting hardware.

Abstract: The present invention relates generally to the problem of filtering, decimation or interpolation and frequency conversion in the digital domain, and more particularly to its use in wideband multichannel receiver, channelization, and transmitter, de-channelization, structures. The invention combines a stand-alone fast convolution algorithm which is further modified and then combined with additional signal processing. By intelligently splitting the filtering effort between the modified fast convolution algorithm block and an additional signal processing block a synergy is created between the two blocks which provides for decreased costs, reduced delay and a reduction in the size of the Fast Fourier Transforms (FFTs). The resulting advantages are especially useful in any system handling multiple channels simultaneously, but especially where there exist strict requirements on both delay and on input Fast Fourier Transform (FFT) size.

Abstract: A system for efficiently filtering interfering signals in a front end of a GPS receiver is disclosed. Such interfering signals can emanate from friendly, as well as unfriendly, sources. One embodiment includes a GPS receiver with a space-time adaptive processing (STAP) filter. At least a portion of the interfering signals are removed by applying weights to the inputs. One embodiment adaptively calculates and applies the weights by Fourier Transform convolution and Fourier Transform correlation. The Fourier Transform can be computed via a Fast Fourier Transform (FFT). This approach advantageously reduces computational complexity to practical levels. Another embodiment utilizes redundancy in the covariance matrix to further reduce computational complexity. In another embodiment, an improved FFT and an improved Inverse FFT further reduce computational complexity and improve speed.

Abstract: A method and device are described for generating two output signals (I; Q) each substantially identical to a square-wave input signal (A) from a local oscillator (2), wherein the first output signal (I) may have a certain time shift with respect to the input signal (A), and wherein the second output signal (Q) is shifted over T1/4 [mod T1] with respect to the first output signal (I), T1 being the period of the input signal (A). To generate the first output signal (I), Fourier components (S1(?1), S3(?3), S5(?5), S7(?7), S9(?9), S11(?11) etc) of the input signal are combined. To generate the second output signal (Q), Fourier components (S1(?1), S5(?5), S9(?9) etc) of the input signal are phase shifted over +90° while Fourier components (S3(?3), S7(?7), S11(?11) etc) of the input signal are phase shifted over ?90°, and the thus shifted Fourier components of the input signal are combined.

Abstract: Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.

Abstract: The present invention provides apparatus, methods, and computer program products that can decrease the latency with which the coefficients of a function representative of signal are determined. Specifically, the apparatus, methods, and computer program products of the present invention, taking advantage of the independence of samples, updates each of the coefficients of the function as each sample is received. As such, when the final sample is received, the apparatus, methods, and computer program products of the present invention need only update each coefficient with the contribution of the last sample prior to outputting the coefficients. As such, the latency from the time the last sample is received and the availability of the coefficients is decreased. To further decrease the latency, in one embodiment, the apparatus, methods, and computer program products of the present invention prestore either all or a portion of the possible values of the contribution of a sample to each coefficient, such that.

Abstract: A multi-pass frequency hop timing acquisition correlator that produces a more accurate time estimate from the fast acquisition frequency hop signal is disclosed. The time estimate produced by the multi-pass acquisition correlator is more accurate than the ¼ hop estimate produced by single-pass fast acquisition correlators. The multi-pass frequency hop timing acquisition correlator uses a time estimate generated by a previous pass through the multi-pass frequency hop timing acquisition correlator as a starting point for computing a new, more accurate, time estimate. Thus, the second pass through the multi-pass frequency hop timing acquisition correlator produces a time estimate that is relatively more accurate than the time estimate produced by the first pass. The more accurate time estimate produced by the multi-pass acquisition correlator reduces the hardware and time needed by the direct acquisition process to acquire the M-code.

Abstract: Systems and methods are provided for performing signal processing on communication data utilizing scale reduced Fast Fourier Transform computations. The present invention provides scaling in a Fast Fourier Transform computation at stages where it is determined that bit growth is present and omits scaling at stages where it is determined that bit growth is absent. The determination is based on the characteristics of the input signal. The determination can be made off-line by modeling and/or simulation or in real-time by analyzing the input signal to determine stages at which bit growth is present and/or absent and setting the stage scaling accordingly.

Abstract: Systems and methods are described for providing a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes The circuit may be controllably configures to perform a fast Fourier transform function, a multiplier function, and a divider function. In one exemplary practical application of the invention, the fast Fourier transform function, multiplier function, and divider function may be used for signal demodulation, channel equalization and channel estimation for a WLAN IEEE 802.11 system.

Abstract: A method for computing an out of place FFT in which each stage of the FFT has an identical signal flow geometry. In each stage of the presently disclosed FFT method the group loop has been eliminated, the twiddle factor data is stored in bit-reversed manner, and the output data values are stored with a unity stride.

Abstract: A method and apparatus to reduce the amount of required memory and instruction cycles when implementing Fast Fourier Transforms (FFTs) on a computer system is described. The invention optimizes FFT software using in-place bit reversal (IPBR) implemented on a processor capable of bit reversed incrementation. Alternative embodiments implement the invention for out of place bit reversal (OOPBR) and on processors that do not support special instructions for bit reversed incrementation. The invention only generates unique bit-reversed address pairs and avoids generation of self-reversed addresses. To optimize the invention for in place bit reversal, every non-self bit reversed address in the input array is generated only once, while making simple, computationally efficient increments away from the previous pair of bit reversed addresses. The address pair generator can independently advance only one address in each address pair, and bit reversal of one address uniquely defines the other address.

Abstract: A system for identifying files can use fingerprints to compare various files and determine redundant files. Frequency representations of portions of files can be used, such as Fast Fourier Transforms, as the fingerprints.

Abstract: A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

Abstract: In a method for performing a fast-Fourier transform (FFT), input data samples are written to a storage instance in a data input step, then subjected to a processing step in which the stored input samples are read out of the storage instance and processed in accordance with a transformation algorithm. The resulting output data samples are written back to the storage instance and, in a transformed data output step, read out of the storage instance, successively received batches of the input data samples being fed cyclically to a plurality of such multiple-function storage instances. Each batch is fed to a respective storage instance such that, at any given time during performance of the method, the input, processing and output steps are being performed simultaneously in respect of different batches using different respective storage instances.

Abstract: A processing apparatus includes a memory capable of storing data, a butterfly arithmetic unit for performing butterfly computation processes, and a bit-reversed order shuffle processing unit for writing results obtained by butterfly computation processes performed by the butterfly arithmetic unit at addresses in the memory after bit-reversed order shuffle instead of writing the results at addresses in the memory in processing order. The data written by the bit-reversed order shuffle processing unit are discrete fast Fourier transform results.

Abstract: A memory address generating method in which a memory bank index and an address control signal, that are required for a series of FFT processes in which a plurality of butterfly input samples are concurrently read from the same number of memory banks, a butterfly calculation is performed thereon by using the plurality of butterfly input samples, and the results are concurrently stored at the same position with the input samples, are calculated within a fixed small delay time by using a differential parity counter.

Abstract: An address generator for use in conjunction with a fast Fourier transform processor includes an efficient architecture for computing the memory addresses of input data points, output data points and twiddle coefficients. In particular, multiplication operation in the calculation of memory addresses is minimized. Instead, a cascaded series of adders is used, in which the output of one adder is input to the next adder. At each stage of the cascaded adders, the same input variable is successively added. The cascaded adder structure is used in the writing address generator, the reading address generator and the twiddle coefficient address generator. In addition, a plurality of modulo N circuits is used in series with the cascaded series of adders to generate the twiddle coefficient addresses.

Abstract: A DMT/OFDM transceiver wherein communication occurs between stations in the form of symbols distributed and transmitted in channels which are allocated when making a link between the stations, each channel supporting a number of bits depending on the spectral response of the link when established. Instead of providing separate modules for performing iFFT's and FFT's, the transceiver has only a single FFT, or iFFT which operates on real and imaginary parts of the data stream; the outputs of the FFT or iFFT being supplied to a post processing stage where simultaneous equations having real and imaginary terms for the transmit and receive data, are solved in order to separate the transmit and receive data.

Abstract: A method for indexing a plurality of ordered elements stored in bit-reversed order in a first and a second memory space, the first memory space indexed by a first memory index denoting memory positions in the first memory space, the second memory space indexed by a second memory index denoting memory positions in the second memory space, the logical position of the elements within the ordered elements indexed by an element index, the method including bit-reversing the element index of a selected element, locating the selected element as being in the first memory space where the MSB of the bit-reversed index equals 0 and the second memory space where the MSB of the bit-reversed index equals 1, and locating the position of the selected element within the MSB-located memory space at the memory index of the MSB-located memory space that corresponds to the non-MSB bits of the bit-reversed index.

Abstract: The present invention may significantly reduce the number of iteration of the time recursive IFFT structure. First, the real and imaginary part of the input signal are modified based on the symmetric and anti-symmetric. Then, they are mixed together by an adder and fed into the lattice module. Next, an IFFT is performed on the modified input data sequence to generate a transformed sequence. Through the symmetric and anti-symmetric properties, the redundant terms may be eliminated.

Abstract: A method and apparatus are used to generate FFT data addresses for a butterfly stage based upon a computation stage value. The method includes setting a selected bit of a binary word at a logical value, performing an addition operation by adding a logical “1” to the binary word, and skipping a carry bit as selected by a one-hot decoded stage value during the addition operation. The apparatus includes consecutive adders configured to store a binary value and perform an addition operation on the binary value, multiplexers configured to select either the carry out output of the current consecutive half adder or the carry out output of the previous consecutive half adder as the carry in input of a next consecutive adder, and sets of logic gates that provide one bit of the data address.

Abstract: A fast Fourier transform with sequential memory accessing within each stage.