Abstract: A processor for processing digital data includes at least one butterfly operator for execution of a fast Fourier transform computation, the butterfly operator having a pipeline architecture for synchronized receiving and processing of input data according to a clock signal. This pipeline architecture includes a plurality of elements including addition, subtraction, and multiplication hardware modules and links for synchronized transmission of data between the modules. At least one element of this pipeline architecture is configurable by at least one programmable parameter, between a first configuration wherein the butterfly operator performs the fast Fourier transform computation and a second configuration wherein the butterfly operator performs a metric computation of an implementation of a channel decoding algorithm.

Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

Abstract: A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.

Abstract: In a data processing system, having a twiddle factor unit, a method for performing a mixed-radix discrete Fourier transform (DFT) having a block size, N, and a maximum block size, Nmax, wherein the maximum block size includes a radix that is not a power of 2 is provided. The method includes receiving a delta value at an input of the twiddle factor unit, the delta value representing a ratio of a modified maximum bock size to the block size, wherein the modified maximum block size is a power of 2. The method further includes using the delta value to obtain a step size for generating indices of a look-up table stored within the twiddle factor unit, wherein the look-up table stores real and imaginary components of twiddle factors corresponding to a set of block sizes of the DFT.

Abstract: Disclosed is a fast Fourier transform circuit capable of high-speed reading and writing of data processed in the individual stages of a fast Fourier transform calculation without segmenting memory. The circuit is provided with: a calculation unit which performs the fast Fourier calculations with digital Fourier transforms as structural elements; memory for storing the input/output data of the calculation unit; and a means for controlling the writing of calculation results from the calculation unit to the memory such that the order of reading data from the memory is the same at each stage in the multi-stage calculation performed on the data being processed by the calculation unit.

Abstract: The invention consists of new ways of constructing a Measuring Matrices (MMs) including time deconvolution of Digital Fourier Transforms DFTs. Also, windowing functions specifically designed to facilitate time deconvolution may be used, and/or the DFTs may be performed in specific non-periodic ways to reduce artifacts and further facilitate deconvolution. These deconvolved DFTs may be used alone or correlated with other DFTs to produce a MM.

Abstract: Methods and apparatus for relative pitch tracking of multiple arbitrary sounds. A probabilistic method for pitch tracking may be implemented as or in a pitch tracking module. A constant-Q transform of an input signal may be decomposed to estimate one or more kernel distributions and one or more impulse distributions. Each kernel distribution represents a spectrum of a particular source, and each impulse distribution represents a relative pitch track for a particular source. The decomposition of the constant-Q transform may be performed according to shift-invariant probabilistic latent component analysis, and may include applying an expectation maximization algorithm to estimate the kernel distributions and the impulse distributions. When decomposing, a prior, e.g. a sliding-Gaussian Dirichlet prior or an entropic prior, and/or a temporal continuity constraint may be imposed on each impulse distribution.

Abstract: Provided are a high-speed Discrete Fourier Transform (DFT) apparatus and a method thereof. The high-speed DFT apparatus includes a zero padding unit, a Fast Fourier Transform (FFT) unit, and a preamble index decision unit. The zero padding unit receives a first input signal having a length of a prime number and changes the first input signal into a second input signal having a length of an exponentiation of 2. The FFT unit performs a FFT on the second input signal outputted from the zero padding unit. The preamble index decision unit detects a preamble index from an output signal from the FFT unit.

Abstract: A method may include storing N number of Fast Fourier Transform (FFT) data points into x-memories, N and x being integers greater than one, and the x-memories having a total memory capacity equivalent to store the N number of FFT data points, and reading K FFT data points of the N number of FFT data points from each of the x-memories so that the N number of FFT data points are read, K being an integer greater than one. The method may further include performing parallel radix-m FFTs on the x*K number of FFT data points, multiplying the x*K number of FFT data points by twiddle factors to obtain resultants, shifting the resultants, and writing back the shifted resultants of the x*K number of FFT data points to the x-memories.

Abstract: A method for generating a transmit sequence in a single carrier frequency division multiple access (SC-FDMA) transmitter is disclosed. In one embodiment, the method includes generating a first time domain sequence, transforming the first time domain sequence to a first frequency domain sequence according to a first transform, distributing the first frequency domain sequence among a subset of subcarriers among a plurality of subcarriers in a second frequency domain sequence, transforming the second frequency domain sequence to a second time domain sequence, and adding a cyclic prefix to the second time domain sequence to form a transmit sequence. In one exemplary embodiment, the first time domain sequence is a plurality of pilot symbols that have known properties e.g., a constant amplitude, and zero autocorrelation (CAZAC).

Abstract: For a large size FFT computation, this invention decomposes it into several smaller sizes FFT by decomposition equation and then transform the original index from one dimension into multi-dimension vector. By controlling the index vector, this invention could distribute the input data into different memory banks such that both the in-place policy for computation and the multi-bank memory for high-radix structure could be supported simultaneously without memory conflict. Besides, in order to keep memory conflict-free when the in-place policy is also adopted for I/O data, this invention reverses the decompose order of FFT to satisfy the vector reverse behavior. This invention can minimize the area and reduce the necessary clock rate effectively for general sized memory-based FFT processor design.

Abstract: A discrete Fourier transform calculation apparatus includes a plurality of multiplier units, and a plurality of butterfly calculation units. Each butterfly calculation unit is configured to perform simultaneous calculations for at least two stages of a fast Fourier transform (FFT) algorithm by using shared resources of the butterfly calculation unit. Each butterfly calculation unit includes a respective memory device to store input data for the corresponding at least two stages of the FFT algorithm, and a respective butterfly calculator coupled to the respective memory device. Each butterfly calculation unit also includes a respective controller coupled to the respective memory device and the respective butterfly calculator. The respective controller is configured to control the corresponding butterfly calculation unit to calculate the corresponding at least two stages of the FFT algorithm. The plurality of butterfly calculation units and the plurality of multiplier units are coupled in series.

Abstract: An orthogonal frequency division multiplexing (OFDM) receiving apparatus, including a receiving unit, a subcarrier demodulation unit and a signal output processing unit, is provided. The receiving unit is for receiving an RF signal to generate a set of discrete signals. The subcarrier demodulation unit is coupled to the receiving unit, and used for demodulating a set of discrete signals to obtain a complex signal. The signal output processing unit is coupled to the subcarrier demodulation unit, and used for capturing and outputting real parts of the complex signal.

Abstract: An apparatus and method for area and speed efficient fast Fourier transform (FFT) processing comprising mapping a one-dimensional DFT to a multi-dimensional representation; re-indexing the multi-dimensional representation as a radix 23 decimation architecture; simplifying the radix 23 decimation architecture to obtain a nested butterfly architecture; acquiring N samples of a finite duration time-sampled signal; and inputting the acquired N samples into the nested butterfly architecture to obtain a N-point fast Fourier transform (FFT) output.

Abstract: A Non-Continuous Orthogonal Frequency Division Multiplexing (NC-OFDM) system may be provided. The NC-OFDM system, including: a sensing unit to determine whether to use at least one frequency band; a band control unit to disable a subcarrier with respect to a frequency band in use as a result of the determination; a pruning determination unit to determine whether a number of points where the subcarrier is disabled is greater than a threshold value; a pruning retrieval unit to retrieve a pruning path generated by the disabling of the subcarrier, when the number of points is greater than the threshold value; and a Fourier transform unit to perform a Fast Fourier transform (FFT) or Inverse FFT (IFFT) by applying the pruning path to the subcarrier.

Abstract: A method for establishing a simulating signal suitable for estimating a complex exponential signal includes the following computer-implemented steps: sampling a time domain signal of a physical system to obtain a sampling signal; transforming the sampling signal to a frequency domain signal using Fast Fourier Transform; determining parameters of the frequency domain signal; establishing a simulating signal; establishing a target function which is a deviation of the simulating signal from the sampling signal; obtaining correcting factors; iterating the target function using a gradient method and the correcting factors to obtain three sets of iterated signal parameters; obtaining corrected parameters using quadratic interpolation; and using the corrected parameters to correct the simulating signal, and establishing an updated target function. The simulating signal can be used to estimate dynamic behavior of the physical system if the updated target function converges to a tolerable range.

Abstract: An optical processor that incorporates optical computing in a monolithic, i.e. single unit, structure that can take the place of, or operate as a coprocessor with, traditional processor devices such as vector processors, digital signal processors, RISCs, CISCs, ASICs, FPGAs among others. The optical processor incorporates photonic devices that perform algorithmic functions on optical signals. The optical processor takes one or more incoming digital signals, converts the digital signal into an optical signal, performs the algorithmic function(s) in the optical domain, and then converts the result back into a digital signal, all in a monolithic or single unit structure.

Abstract: A processor for processing digital data includes at least one butterfly operator for executing an FFT/IFFT computation. This butterfly operator contains a first stage of complex multiplication and a second stage of complex addition and subtraction. Each of these two stages contains a plurality of addition/subtraction hardware modules and data transmission links between these modules. At least a part of the addition/subtraction modules of each stage of the butterfly operator and at least a part of the links between these modules are configurable with the aid of at least one programmable parameter, between a first configuration in which the butterfly operator carries out said fast Fourier transform computation and a second configuration in which the butterfly operator carries out a computation of branch metrics values and of path metrics and survivors values of a Viterbi algorithm.

Abstract: A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.

Abstract: An addition/subtraction hardware operator includes a plurality of addition/subtraction hardware modules and a plurality of transmission links between these modules, on one hand, and between inputs and outputs of the operator and these modules, on the other hand, according to a pre-determined structure for performing arithmetical calculations. At least a part of the addition/subtraction hardware modules and at least a part of the links between these modules can be configured by at least one programmable parameter, at least between a first configuration in which the operator finalizes a computation of real parts of fast Fourier transform coefficients, a second configuration in which the operator finalizes a computation of imaginary parts of fast Fourier transform coefficients, and a third configuration in which the operator carries out a computation of path metrics and survivors values of a Viterbi algorithm implementation.

Abstract: A method of analyzing a spectrum of one-dimensional or multi-dimensional signal X(t) requires a number of steps including deriving coefficients [AN(?), BN(?)] of an Lp-norm harmonic regression of tie signal with 0<p?? and p?2, squaring the coefficients, summing the squared coefficients, and scaling the summed, squared coefficients with a constant c to realize a periodogram of X(t) as LN(?)=c{[AN(?)]+[BN(?)]2}. The method may include receiving the signal X(t), storing the received signal X(t), and outputting the periodogram LN(?). The method may still further include scanning to maximize the periodogram LN(?) by identifying its largest peak(s) and comparing the amplitude of the identified largest peak(s) with a threshold to determine if the largest peak(s) is(are) attributable to a presence of a periodic signal. The coefficients are preferable derived from a time series signal X(t), t=1, 2, . . . , N, but may include receiving a continuous-time signal and converting it to the time series signal.

Abstract: The present invention provides technologies for implementing a high-speed Fast Fourier Transform (FFT) algorithm with a small memory. An information processing apparatus for performing a radix-2 FFT on a data sequence comprises storage means, reading means, a plurality of butterfly operation means, writing means, and control means, wherein each stage of the FFT operation includes a plurality of operation steps, and at every operation step the control means controls each of the means so that: the reading means reads from the storage means sets of data elements referred by storage addresses A, A+1, A+2m, and A+2m+1, the plurality of butterfly operation means perform radix-2 butterfly operation on the data elements in the sets, and the writing means writes the sets of the result data into the storage area referred by the storage addresses A, A+1, A+2m, and A+2m+1.

Abstract: A method for receiving a pilot symbol in a receiver is disclosed. In one embodiment, the method includes removing a cyclic prefix from a received sequence to produce a modified sequence, transforming the modified sequence to a first frequency domain sequence according to a first transform, demapping a plurality of distributed subcarriers in the transformed modified sequence to extract a plurality of received symbols, deriving an intermediate channel estimate for each of the plurality of received symbols, and interpolating a final channel estimate based on the plurality of derived intermediate channel estimates. In one exemplary embodiment, the received symbols have one or more predefined characteristics such as a constant amplitude, and zero autocorrelation (CAZAC sequence).

Abstract: A variable length fast Fourier transform (FFT) system and a method for performing the FFT system in a global navigation satellite system (GNSS) signal acquisition and tracking, which includes a memory and a number of processing elements are disclosed. Based on the GNSS signal tracking, the variable length FFT system performs a first FFT operation together with a first data length. Based on the GNSS signal acquisition, the variable length FFT system is divided into several FFT subsystems to simultaneously perform different operations with various data lengths different from the first data length. Thus, the variable length FFT system can enhance the hardware utility and increase throughputs.

Abstract: Methods for modeling the secondary path of an ANC system to improve convergence and tracking during noise control operation, and their associated uses are provided. In one aspect, for example, a method for modeling a secondary path for an active noise control system is provided. Such a method may include receiving a reference signal, filtering the reference signal with an initial secondary path model to obtain a filtered reference signal, calculating an autocorrelation matrix from the filtered reference signal, and calculating a plurality of eigenvalues from the autocorrelation matrix. The method may further include calculating a maximum difference between the plurality of eigenvalues and iterating a test model to determine an optimized secondary path model having a plurality of optimized eigenvalues that have a minimized difference that is less than the maximum difference of the plurality of eigenvalues, such that the optimized secondary path model may be utilized in the active noise control system.

Abstract: An FFT engine implementing a cycle count method of applying twiddle multiplications in multi-stages. When implementing a multistage FFT, the intermediate values need to be multiplied by various twiddle factors. The FFT engine utilizes a minimal number of multipliers to perform the twiddle multiplications in an efficient pipeline. Optimizing a number of complex multipliers based on an FFT radix and a number of values in each row of memory allows the FFT function to be performed using a reasonable amount of area and in a minimal number of cycles. Strategic ordering and grouping of the values allows the FFT operation to be performed in a fewer number of cycles.

Abstract: A method of fast matrix multiplication and a method and apparatus for fast solving of a matrix equation are disclosed. They are useful in many applications including image blurring, deblurring, and 3D image reconstruction, in 3D microscopy and computer vision. The methods and apparatus are based on a new theoretical result—the Generalized Convolution Theorem (GCT). Based on GCT, matrix equations that represent certain linear integral equations are first transformed to equivalent convolution integral equations through change of variables. Then the resulting convolution integral equations are evaluated or solved using the Fast Fourier Transform (FFT). Evaluating a convolution integral corresponds to matrix multiplication and solving a convolution integral equation corresponds to solving the related matrix equation through deconvolution. Carrying-out these convolution and deconvolution operations in the Fourier domain using FFT speeds up computations significantly.

Abstract: A communication system includes: a sampling section that samples a reception signal; a preprocessing execution section that acquires a sampling value, which is obtained by the sampling section, while executing preprocessing for performing a Fast Fourier Transform in a divided manner; and a Fast Fourier Transform section that performs the Fast Fourier Transform in the divided manner on the basis of an output acquired from the processing execution section.

Abstract: A system and method for estimating a signal based on a stream of randomly generated samples. The method includes: (a) receiving a sample; (b) generating a sampling vector; (c) multiplying the sample and the sampling vector to obtain a current back projection; (d) computing a first intermediate vector that represents an average of the current back projection and previous back projections; (e) transforming the first intermediate vector to determine a second intermediate vector; (f) identifying locations where the second intermediate vector attains its k largest values; (g) computing an estimate for the transformation of the signal by solving a system of equations based on the identified locations, the received sample value, previously received sample values, the sampling vector and previously generated sampling vectors; (h) inverse transforming the transformation estimate to determine an estimate of the signal; and (i) storing the signal estimate.

Abstract: A fast Fourier transformer (FFT) includes a radix-2 butterfly unit configured to perform a butterfly operation on input data; a buffer unit configured to buffer data outputted from the radix-2 butterfly unit and output the buffered data to the radix-2 butterfly unit; a multiplexing unit configured to selectively output a twiddle factor; and a constant multiplier configured to multiply the data outputted from the radix-2 butterfly unit by the twiddle factor outputted from the multiplexing unit.

Abstract: Disclosed are a method and apparatus of performing a fast Fourier transform (FFT). The apparatus include a plurality of single-path delay feedback (SDF) butterfly blocks which performs butterfly operations, respectively; a plurality of memories which are connected to the SDF butterfly blocks, respectively; and a controller which controls the plurality of SDF butterfly blocks, wherein the plurality of SDF butterfly blocks are connected in a pipeline structure and thus output from one SDF butterfly block is input to a following SDF butterfly block.

Abstract: A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.

Abstract: A hybrid fast Fourier transform (FFT) combines a prime-factor algorithm (PFA) with a Cooley-Tukey algorithm (CTA). The combining includes performing combined permutations and combined weight multiplications during CTA processing using permutations and weights derived from the PFA processing and the CTA processing to improve efficiency. The combined permutations can include the last permutation of the PFA processing combined with the first permutation of the CTA processing. The combined weights can include multiplying weights resulting from a permutation that was omitted during PFA processing by “twiddle” factors generated during CTA processing. The combined weights can be pre-computed and stored in table where they can be applied during CTA processing.

Abstract: A method of computing matrices of discrete-frequency Discrete Fourier Transform (DFT) coefficients, the method including the steps of (a) for a first frame (10) of samples, multiplying a frame of samples of a discrete-time signal by a twiddle factor matrix (F1, F2) to compute a matrix of DFT coefficients for that first frame, and storing a computation resulting from multiplication of the second half of the frame (b) of samples by the right half (F2) of the twiddle factor matrix; and (b) for each subsequent frame (12, 14) of samples, wherein each subsequent frame overlaps a preceding frame by half, (i) retrieving the stored computation from the preceding frame, inverting the sign of the stored computation every second frame; (ii) multiplying the second half of the current frame of samples by the right half of the twiddle factor matrix, and storing the resultant computation; and (iii) adding the results of steps (i) and (ii).

Abstract: An implement method of a FFT processor comprises the following steps. First, a 21 point FFT processor, which has an output and an input receiving a 2n+1 point data, is provided. A 2n-point FFT processor having an input and an output is provided. Sequentially, a multiplexer, which has a first input coupled to the output of the 21 point FFT processor, a second input receiving a 2n point data and an output coupled to the input of the 2n point FFT processor, is provided. When an input data is a 2n point data, the second input of multiplexer is coupled to the output thereof, and when an input data is a 2n+1 point data, the first input of multiplexer is coupled to the output thereof.

Abstract: The present invention relates to a complex multiplier and a twiddle factor generator.

Abstract: An algorithm to detect a broad class of signals in Gaussian noise using higher-order statistics. The algorithm detects a number of different signal types. The signals may be in the base-band or the pass-band, single-carrier or multi-carrier, frequency hopping or non-hopping, broad-pulse or narrow-pulse etc. In a typical setting this algorithm provides an error rate of 3/100 at a signal to noise ratio of 0 dB. This algorithm gives the time frequency detection ratio that may be used to determine if the detected signal falls in Class Single-Carrier of Class Multi-Carrier. Additionally this algorithm may be used for a number of different applications such as multiple signal identification, finding the basis functions of the received signal and the like.

Abstract: Provided is a fast Fourier transformation circuit capable of optimizing an operation resource while matching a plurality of communication systems. In this circuit, an FFT circuit (100) comprises a first FFT operation unit (110) for subjecting two-parallel 2<M?1> digital signals to FFT operations of (M?1) steps, a second FFT operation unit (120) for subjecting 2<N> digital signals to FFT operations of (N?M+1) steps, and a third FFT operation unit (130) for subjecting 2<M> digital signals to an FFT operation of one step. The output signal of the first FFT operation unit (110) is subjected to the FFT operation by the second FFT operation unit (120) and the third FFT operation unit (130) thereby to perform the FFT operations of 2<N> points and 2<M> points simultaneously.

Abstract: A processor for performing a fast Fourier transform or inverse fast Fourier transform comprises a radix-2 butterfly structure; and a radix-4 butterfly structure. A method of performing a fast Fourier transform or inverse fast Fourier transform comprises selectively performing a radix-2 butterfly operation on an input data stream; and selectively performing a radix-4 butterfly operation on one of a result produced by the radix-2 butterfly operation and the input data stream. Apparatus for performing a fast Fourier transform or inverse fast Fourier transform comprises means for selectively performing a radix-2 butterfly operation on an input data stream; and means for selectively performing a radix-4 butterfly operation on one of a result produced by the radix-2 butterfly operation and the input data stream.

Abstract: The present invention relates to the design and implementation of parallel pipelined circuits for the fast Fourier transform (FFT). In this invention, an efficient way of designing FFT circuits using folding transformation and register minimization techniques is proposed. Based on the proposed scheme, novel parallel-pipelined architectures for the computation of complex fast Fourier transform are derived. The proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The proposed circuits process L consecutive samples from a single-channel signal in parallel. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. The proposed scheme is general and suitable for applications such as communications, biomedical monitoring systems, and high speed OFDM systems.

Abstract: The invention suggests a novel pipeline FFT/IFFT architecture that not only produces time-domain samples (after IFFT) but also pushes time-domain samples into FFT in a time-based sequential order. This reduces external memory requirement for buffering the time-domain samples. Also the design is based on a mixed radix-2 and radix-22 algorithm aiming at reducing number of multipliers and adders. Compared with other FFT/IFFT design methodologies such as radix-4, it achieves the minimum multiplier use, the minimum adder use and the minimum operating memory use. On the other hand, the design architecture not only can support different FFT/IFFT size required by different VDSL2 profiles but also utilizing a novel pipeline control mechanism to reduce logic switching at low-speed profiles. This effectively further reduces the power consumption at lower profiles and enables our VDSL2 digital chipsets to compete with ADSL2+ systems in terms of power consumption.

Abstract: We disclose an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. An input module combines a plurality of inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator generates multiplicands. At least two complex multiplier modules perform complex multiplications with at least one of the complex multiplier modules receiving an output from the input module. A map module receives outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs received to generate multiple outputs. Finally, an accumulation module receives and performs an accumulation task on each of the multiple outputs of the map module thereby generating a corresponding number of multiple outputs.

Abstract: A circuit and a method for implementing Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are provided.

Abstract: An SR-2/8 FFT apparatus includes a memory, an SRFFT processor and a control unit. The control unit includes an input control block, an SRFFT control block and an output control block. The input control block loads memory banks with the input data in a first order, such that the SRFFT processor is able to retrieve data from the memory banks simultaneously in a single clock cycle. The SRFFT control block determines a decomposition structure of a 2M-point FFT and controls the SRFFT processor to repeatedly perform a butterfly computation along the decomposition structure. The order of the input data of each butterfly computation fits in with the first order. The SRFFT control block controls output results of each butterfly computation to be written back into the memory banks corresponding to the input data. The output control block controls the output results to be outputted in a second order.

Abstract: The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising: distributing the plurality of elements of the array in a first dimension across the plurality of nodes of the computer system over the network to facilitate a first one-dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing the one-dimensional FFT-transformed elements at each node in a second dimension via “all-to-all” distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FFT on elements of the array re-distributed at each node in the second dimension, wherein the random order facilitates eff

Abstract: A method for realizing IFFT by FFT is provided, which comprises: performing a left mirror permutation on an input data sequence, then performing FFT, and dividing the result with N, so as to obtain IFFT processing data; or performing FFT on an input data sequence, then performing a left mirror permutation on the result of FFT and being divided by N, so as to obtain IFFT processing data; the left mirror permutation is: inverting the sequence of the other data except the first data; the N is the length of the input data sequence. Also, an IFFT processing apparatus comprising an FFT computing unit and a left mirror permutation unit is provided.

Abstract: When a receiving apparatus which employs a OFDM-based cellular wireless communication scheme detects as an excessive signal for each frame, the signal having signal intensity exceeding a reference value after a Fourier transform, a gain variable according to an excessive quantity relative to the reference value is used for each frame to control signal intensity such that the amplitude thereof is at most the reference value.

Abstract: In an FFT computing apparatus, a computation-unit switching detection unit detects timing at which a complex multiplication is not being carried out in said butterfly computation of FFT computation, and a complex-multiplication power-computation unit switches computation between complex multiplication and power computation, based on a detection result by said computation-unit switching detection unit. The complex-multiplication power-computation unit performs power computation at timing at which complex multiplication is not carried out in said butterfly computation of FFT computation.

Abstract: An FFT algorithm that splits a large bit width waveform into two parts, making it possible to conduct the FFT with much lower logic resource consumption is disclosed. The waveform is split into its most significant bits and its least significant bits through division in the form of a bit shift. Each partial signal is then put through an FFT algorithm. The MSB FFT output is then right bit shifted. The two partial FFT's are summed to create a single output that is largely equivalent to an FFT of the original waveform. Rounding distortion is reduced by overlapping the MSB and LSB partial signals.

Abstract: A method for creating a customized music visualization display for a music input involves presenting a user with a plurality of effects icons and a visualizer canvas as a portion of the user interface display. A user places one or more of the visual effects icons on the visualizer canvas. A sweep arm travels in a continuous sweeping motion through an arc and at a speed determined by a musical input and where each effect icon is detected and the effect is displayed when the sweep arm impacts the location of the video effect icon within the visualizer canvas.