Abstract: A memory-based Fast Fourier Transform device is provided, which adopts single-port random access memory (RAM), rather than dual-port RAM, as a storage, and the circuit area of the FFT device is therefore reduced. In order to enhance the access efficiency of the memory and the use efficiency of a processor, the transformer adopts a modified in-place conflict-free addressing to achieve similar performance of a traditional Fast Fourier Transform device.

Abstract: Certain embodiments of the present disclosure relate to methods for peak-to-average power ratio (PAPR) reduction of a transmission signal in a single carrier frequency division multiple access (SC-FDMA) system. The proposed methods and systems are based on manipulations of an SC-FDMA transmission signal in a time- and/or a frequency-domain.

Abstract: An FFT processor is disclosed, which includes a first multi-pipelined MDC unit, a second multi-pipelined MDC unit and a switching network. The first multi-pipelined MDC unit and the second multi-pipelined MDC unit respectively employ a plurality of MDC circuits to change the positions of the delayers thereof in parallel way. By changing the operation time sequence of the signals in the first multi-pipelined MDC unit and the second multi-pipelined MDC unit, the first multi-pipelined MDC unit is able to directly send the operation results to the second multi-pipelined MDC unit through the switching network.

Abstract: Provided are a high-speed Discrete Fourier Transform (DFT) apparatus and a method thereof. The high-speed DFT apparatus includes a zero padding unit, a Fast Fourier Transform (FFT) unit, and a preamble index decision unit. The zero padding unit receives a first input signal having a length of a prime number and changes the first input signal into a second input signal having a length of an exponentiation of 2. The FFT unit performs a FFT on the second input signal outputted from the zero padding unit. The preamble index decision unit detects a preamble index from an output signal from the FFT unit.

Abstract: Disclosed are a fast Fourier transform (FFT) start point setting apparatus, and a method thereof. An FFT start point according to a synchronization acquisition result is moved to a CP direction by a predetermined sample offset and perform FFT.

Abstract: The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements, comprising computing each butterfly of the first “log2P” stages on either a single processor or each of the “P” processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the “P” processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.

Abstract: The present invention provides for a method of receiving a signal spread over a frequency range, and in particular a direct sequence spread spectrum signals including the step of employing a Fast Fourier Transform (FFT) in the Doppler search. In particular, the invention relates to the receipt of spread spectrum signals such as those transmitted as part of a GPS system.

Abstract: An N-point FFT processor 100 suitable for large data inputs (e.g. 2 k or 8 k-point input data) is formed from a m-point FFT processor unit 10 and a n-point FFT processor unit 20 in combination, where N=m×n and m and n are any positive integers. First, second and third permutation units 31, 32 & 33 perform global permutations on the data passing through the FFT processor. A twiddle factor unit 40 applies twiddle factors. A digital signal processing apparatus 1100 (FIG. 11) comprising the FFT processor 100 is also described. Further, a testing apparatus 1200 (FIG. 12) is described for testing an N-point FFT processor 100 by selecting amongst a plurality of m-point FFT processor units 10-10c and a plurality of n-point FFT processor units 20a-2c.

Abstract: Techniques for efficiently performing partial FFT for subcarriers of interest are described. The N total subcarriers may be arranged into M sets. Each set may contain K subcarriers uniformly distributed across the N total subcarriers, where M·K=N. For the partial FFT, pre-processing is initially performed on time-domain samples to obtain intermediate samples. The pre-processing may include performing M-point FFTs on the time-domain samples and multiplying the FFT outputs with unit complex values. For each set of subcarriers of interest, a K-point FFT is performed on a set of intermediate samples to obtain a set of frequency-domain symbols for that set of subcarriers. Since K is typically much smaller than N, substantial savings in computation and power may be realized when only one or few sets of subcarriers are of interest.

Abstract: An apparatus for simulating a signal composed of a plurality of individual signals from respective signal locations at a simulation location, having a provider for providing the plurality of individual signals in the time domain, a transformer for transforming the individual signals to the frequency domain, a processor for processing the individual signals transformed to the frequency domain each depending on a signal channel existing between the simulation location and the respective signal location, a combiner for combining the processed individual signals transformed to the frequency domain to a combined signal, and a transformer for transforming the combined signal to the time domain for generating the simulated combined signal at the simulation location.

Abstract: In one embodiment, a method is disclosed that includes obtaining at least one measurement in a spectral domain of a sample and computing one or more measurements of the salient features in the spectral domain. The salient features correspond to at least one peak within the spectral domain. This method also includes classifying the computed salient features against a feature signature of nitric acid. In addition, this method includes determining if the chemical is present in the sample.

Abstract: A non-invasive motion and respiration monitor receives impulses from a subject's movement, heartbeat, and respiration. The raw signal is biased and digitized, and a signal processor applies a Fast Fourier Transform to the signal. The transformed signal is filtered to isolate the component representing heart rate from the component representing respiration. An Inverse Fast Fourier Transform is then applied to the component signals, which are sent to a processor. The processor is programmed to detect irregularities in the respiration and heart rate. If severe irregularities or complete cessation is detected in either signal, a mechanical stimulator is actuated to try to stimulate the subject, and an alarm is sounded to alert a caregiver such as a parent or nurse.

Abstract: A data reordering system for determining addresses associated with a vector of transformed data and corresponding method of reordering transformed data, where the data reordering system includes: a first transform function coupled to a data vector and operable to provide the vector of transformed data; a reordering function, including a plurality of counters, that is operable to determine a plurality of offset addresses, with a, respective, offset address for each element in the vector of transformed data; and an adder operable to add a base address that corresponds to the first address to the each, respective, offset address to provide a sequence of addresses suitable for accessing the vector of transformed data to provide a re-sequenced vector of transformed data.

Abstract: A system described herein includes a selector component that receives input data that is desirably transformed by way of a Discrete Fourier Transform, wherein the selector component selects one of a plurality of algorithms for computing the Discrete Fourier Transform from a library based at least in part upon a size of the input function. An evaluator component executes the selected one of the plurality of algorithms to compute the Discrete Fourier Transform, wherein the evaluator component causes leverages shared memory of a processor to compute the Discrete Fourier Transform.

Abstract: A method is provided to compare recordings that includes providing a list of a plurality of recordings and selecting at least a first recording and a second recording from the plurality of recordings. The first recording and the second recording have predetermined lengths The method also includes selecting a first portion of the first recording, identifying a second portion of the second recording based on the first portion, and comparing the first portion to the second portion When the entire length of the recording is selected as the first portion, the entire length of the second recording can be identified as the second portion. Identifying a second portion may also include normalizing it to the first portion. Also, identifying the second portion can include translating the first portion into a wave-form searching the second recording for another wave-form similar to the translated wave-form and matching the translated wave form with the similar wave-form.

Abstract: A Fast Fourier Transform (FFT) hardware implementation and method provides efficient FFT processing while minimizing the die area needed in an Integrated Circuit (IC). The FFT hardware can implement an N point FFT, where N=rn is a function of a radix (r). The hardware implementation includes a sample memory having N/r rows, each storing r samples. A twiddle factor memory can store k twiddle factors per row, where 0<k<r represents the number of complex twiddle multipliers available. An FFT module reads r rows from memory, performs an r-point complex FFT on the samples, followed by twiddle multiplication, and writes the results into an r×r register bank. The contents of the register bank are written in transposed order back to the sample memory. This operation is repeated N/r2 times for each stage and then repeated for n-stages to produce the N point FFT.

Abstract: A novel technique for providing high speed FFT architecture for OFDM processors that reduces silicon area while maintaining the high speed requirement. In one example embodiment, this is accomplished by pipelined and/or sequential implementation of two or more FFT stages so that each stage performs a small portion of the FFT.

Abstract: A Fourier transform device generates a first sequence according to an input sequence based on a stored lookup table, and generates an output sequence by performing a butterfly operation on the first sequence a plurality of times.

Abstract: Described is a technology for use with general discrete Fourier transforms (DFTs) performed on a graphics processing unit (GPU). The technology is implemented in a general library accessed through GPU-independent APIs. The library handles complex and real data of any size, including for non-power-of-two data sizes. In one implementation, the radix-2 Stockham formulation of the fast Fourier transform (FFT) is used to avoid computationally expensive bit reversals. For non-power of two data sizes, a Bluestein z-chirp algorithm may be used.

Abstract: This invention relates to a hybrid passive agent system impedance monitoring station and method. The method of monitoring impedance of an electrical system includes the steps of providing an impedance monitoring station adapted to test and monitor system impedance, solving for system impedance in a time domain, solving for system impedance in a frequency domain, and determining a time domain driving point impedance and a frequency domain driving point impedance to identify the impedance of the system.

Abstract: A system and method for Fourier encoding a nuclear magnetic resonance (NMR) signal is disclosed. A static magnetic field B0 is provided along a first direction. An NMR signal from the sample is Fourier encoded by applying a rotating-frame gradient field BG superimposed on the B0, where the BG comprises a vector component rotating in a plane perpendicular to the first direction at an angular frequency ? in a laboratory frame. The Fourier-encoded NMR signal is detected.

Abstract: A circuit for converting frequency domain information to time domain information includes an Inverse Fast Fourier Transform circuit having a length of N coefficients. The Inverse Fast Fourier Transform circuit is adapted to receive input data of length N coefficients and generate output data of length N coefficients that are circularly shifted by m coefficients. The circuit also includes Cyclical Prefix Insertion circuit adapted to insert a cyclical prefix of length m. The Cyclical Prefix Insertion circuit includes a first switch, connected to the Inverse Fast Fourier Transform circuit, a buffer, having an input connected to the first switch and an output, the buffer having a length m, and a second switch, coupled to the first switch and to the buffer. The first and second switches selectively couple the output of the buffer and the Inverse Fast Fourier Transform circuit to an output of the second switch. The buffer is reduced to length m.

Abstract: A 2N-point and N-point FFT/IFFT dual mode processor is provided. The processor includes a butterfly operator, the first and second MUXs, and the first and second N-point FFT processors. The butterfly operator receives 2N data and butterfly-operates on the received 2N data when receiving a control signal ‘0’ from the controller. The first and second MUXs respectively receive results from the butterfly operator to output the results in an increment of N when receiving a control signal ‘0’ from the controller, and respectively outputs different N data when receiving a control signal ‘1’ from the controller. The first and second N-point FFT processors N-point FFT operate on the results from the first and second MUXs and respectively output the same under control of the controller. Since the N-point FFT operation can be simultaneously performed two times at a receiver, the performance of the receiver can be enhanced.

Abstract: Methods and apparatuses are provided for a fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT) architecture that not only allows for efficient computation of N-point FFT/IFFT transform (N=2n), but also allows for efficient reuse of the multipliers and delay blocks for efficient implementation of signal energy detection and autocorrelation of length or period 2p, where p?{0, 1, . . . , log2(N)?1}. Signal energy detection and autocorrelation may then used for received energy measurement, frame synchronization, including packet detection or symbol timing, and carrier frequency offset estimation.

Abstract: A method and corresponding apparatus for fast FFT processing of paging information includes receiving an analog signal that is converted to a first digital signal and digitally filtered through a first filter having a first bandwidth (BWA) to obtain a second digital signal. The second digital signal is stored in a buffer. The first digital signal is further digitally filtered through a second filter having a second bandwidth (BWB) to obtain a third digital signal. An FFTM processing of the third digital signal is initiated and simultaneously, an FFTN processing of the second digital signal is initiated. The FFTM processed third digital signal is then decoded and, based on the decoding of the FFTM processed third digital signal, a determination is made of whether to complete the FFTN processing of the second digital signal from the buffer.

Abstract: A Decimation In Frequency (DIF) Fast Fourier Transform (FFT) stage is used in an N bin FFT, wherein N is an even integer. The DIF FFT stage includes swap logic that receives a first input sample, x(v), and a second input sample, x(v+N/2), and selectively supplies either the first and second input samples at respective first and second swap logic output ports or alternatively the second and first input samples at the respective first and second swap logic output ports, wherein 0?v<N/2. The DIF FFT stage further includes a summing unit for adding values supplied by the first and second swap logic output ports; a differencing unit for subtracting values supplied by the first and second swap logic output ports; and twiddle factor logic that multiplies a value supplied by the differencing unit by a twiddle factor, WN(v+s)mod(N/2), where s is an integer representing an amount of circular shift of N input samples.

Abstract: In a data processing system, having a twiddle factor unit, a method for performing a mixed-radix discrete Fourier transform (DFT) having a block size, N, and a maximum block size, Nmax, wherein the maximum block size includes a radix that is not a power of 2 is provided. The method includes receiving a delta value at an input of the twiddle factor unit, the delta value representing a ratio of a modified maximum bock size to the block size, wherein the modified maximum block size is a power of 2. The method further includes using the delta value to obtain a step size for generating indices of a look-up table stored within the twiddle factor unit, wherein the look-up table stores real and imaginary components of twiddle factors corresponding to a set of block sizes of the DFT.

Abstract: An FFT apparatus for quickly processing input signals and method thereof is disclosed. In performing the FFT for processing N input signals, four N/4-point FFT units implemented by radix-2 single-path delay feedback (R2SDF) units performs the FFT with respect to the input signals, and a radix-4 computation unit performs a radix-4 computation with respect to the signals transferred from the N/4-point FFT units. Accordingly, the input signals are processed in parallel through the N/4-point FFT units, and thus a quick process of the input signals can be performed.

Abstract: A method of designing a IEEE 802.11n modem starting from a IEEE 802.11a/g modem using a programmable FFT (Fast Fourier Transform) based on a half length FFT core, modifies data in a reception chain implemented in a IEEE 802.11n standard application. The method uses a N/2 FFT which is validated, along with a wrapper; and, extends and applies the validated N/2 FFT, (e.g., 64 FFT) to a N FFT (e.g., 128 FFT) by splitting the N FFT into two smaller first and second FFTs. The first FFT is applied to selected data samples (e.g., even samples) from the N FFT and the second FFT is applied to remaining data samples (e.g., odd samples) from the N FFT to complete data-handling, wherein the extending step is based on Danielson-Lanczos formula using a reduced number of Cordics. The method is also suitable for IFFT computations in IEEE 802.11n MIMO OFDM modem designs.

Abstract: An FFT conversion instruction based on a single instruction multiple data (“SIMD”) technique is executed to reduce the number of cycles for software to perform conversion processing used in an FFT computation. In an embodiment, the FFT conversion instruction implements two instances of a conversion operation, i.e., 2-way SIMD, over two sets of complex points at once. A control register or variant opcode controls an inverse flag to control the behavior of the conversion process. In an embodiment, the control register contains a control bit to select between forward and inverse FFT context.

Abstract: According to an inventive scheme for introducing a watermark into an information signal, the information signal is at first transferred from a time representation to a spectral/modulation spectral representation). The information signal is then manipulated in the spectral/modulation spectral representation in dependence on the watermark to be introduced to obtain a modified spectral/modulation spectral representation, and subsequently an information signal provided with a watermark is formed based on the modified spectral/modulation spectral representation. An advantage is that, due to the fact that the watermark is embedded and/or derived in the spectral/modulation spectral representation or range, traditional correlation attacks as are used in watermark methods based on a spread-band modulation cannot succeed easily.

Abstract: A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.

Abstract: An input random access memory (RAM) module of a fast Fourier transform (FFT) engine of a DVB receiver is used to store, during a first time period, delayed versions of an input signal that includes a first orthogonal frequency division multiplexed (OFDM) symbol and a cyclic prefix therefor received at the receiver, and samples for a second OFDM symbol to be demodulated using the FFT engine during a second time period. Delayed versions of the input signal are stored in the input RAM module of the FFT engine in a first-in-first-out (FIFO) fashion for signal acquisition and for FFT processing. Similarly, an output RAM module of the FFT engine is used to store moving averages of an autocorrelation of the input signal with its cyclic prefix computed over presumed guard intervals and over multiple symbols.

Abstract: A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems.

Abstract: An FFT butterfly instruction based on single instruction multiple data (“SIMD”) technique is executed to reduce the number of cycles for software to perform FFT butterfly operations. The FFT butterfly instruction can implement one or more instances of the FFT butterfly operation (e.g., non-SIMD, 2-way SIMD, 4-way SIMD, etc.), at once, each instance operating over a set of complex values. A control register or variant opcode controls the behavior of the FFT butterfly operation. The contents of the control register or the variant opcode can be altered to configure the butterfly behavior to suit specific circumstances. The FFT butterfly instruction can be used in the software on a processor in a chip-set implementing the central-office modem end of a DSL link. The FFT butterfly instruction can also be used in other contexts where an FFT function is performed (and/or where an FFT butterfly operation is used) including systems that do not implement DSL or DMT.

Abstract: A fast Fourier transform (FFT) computation system comprises a plurality of field programmable gate arrays (FPGAs), a plurality of initial calculations modules, a plurality of butterfly modules, a plurality of external interfaces, and a plurality of FPGA interfaces. The FPGAs may include a plurality of configurable logic elements that may be configured to perform mathematical calculations for the FFT. The initial calculations modules may be formed from the configurable logic elements and may be implemented according to a split-radix tree architecture that includes a plurality of interconnected nodes. The initial calculations modules may perform the initial split-radix calculations of the FFT. The butterfly modules may be formed from the configurable logic elements and may be implemented according to the split-radix tree architecture to perform at least a portion of the FFT computation in an order that corresponds to the connection of the nodes of the split-radix tree architecture.

Abstract: A multi-dimensional FFT is calculated upon 2n rows of 2m data values set out end-to-end in memory by traversing the data set as a whole using stride values and block sizes which halve upon each pass through the data. As the data values represent multi-dimensional data, there are one or more dimensional boundaries within the data and as these are crossed the coefficient values being applied by the complex butterfly calculation are adjusted to take account of the manipulation being performed. The linearity of the matrix calculations underlying the butterfly calculation means that the order in which these calculations are performed is not significant and accordingly multiple passes with appropriate coefficient changes can perform a multi-dimensional calculation even if the different components of the calculation in respect of each dimension arise upon different passes through the data set.

Abstract: A system comprises first and second local memory banks; and a reconfigurable ALU array having multiple configurations including: a first for performing an inverse butterfly operation, a second for performing a multiplication operation, a third for performing parallel subtraction and addition, and a fourth for performing an inverse N-point shuffle. The ALU array may obtain input for the inverse butterfly operation from the first bank and store output in the second bank. The ALU array may obtain input for the multiplication operation from the second bank and store output in the first bank. The ALU array may obtain input for the parallel subtraction and addition operation from the first bank and store output in the second bank. The ALU array may obtain input for the N-point inverse shuffle from the second bank and store output in the first bank. The system may further comprise a bit reversal block.

Abstract: For a large size FFT computation, this invention decomposes it into several smaller sizes FFT by decomposition equation and then transform the original index from one dimension into multi-dimension vector. By controlling the index vector, this invention could distribute the input data into different memory banks such that both the in-place policy for computation and the multi-bank memory for high-radix structure could be supported simultaneously without memory conflict. Besides, in order to keep memory conflict-free when the in-place policy is also adopted for I/O data, this invention reverses the decompose order of FFT to satisfy the vector reverse behavior. This invention can minimize the area and reduce the necessary clock rate effectively for general sized memory-based FFT processor design.

Abstract: The present invention relates to an apparatus and method for variable fast Fourier transform. According to an embodiment of the present invention, two n-point fast Fourier transform (FFT) processors are used to generate two n-point FFT output data or one 2n-point FFT output data. The one 2n-point input data is alternately input to the two n-point FFT processors. Each of the two n-point FFT processors selects a twiddle factor for the n-point input data or the 2n-point input data and performs fast Fourier transform. A butterfly operation is performed on signals obtained by performing fast Fourier transform on the 2n-point input data signal, and the processed signals are aligned in an output order. According to this structure, it is possible to realize a fast Fourier transform hardware engine that selectively performs multi-frequency allocation in a base station system that supports the multi-frequency allocation.

Abstract: The solution X0 to an initial system of equations with a Toeplitz coefficient matrix T0 can be efficiently determined from an approximate solution X to a system of equations with a coefficient matrix T that is approximately equal to the coefficient matrix T0. Iterative updates can be performed to improve the accuracy of the approximate solution X.

Abstract: A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.

Abstract: Signal weights corresponding to an initial system of equations with a block coefficient matrix T0 can be obtained from the solution to a system of equations with a block coefficient matrix T. The matrix T is approximately equal to the matrix T0. The signal weights can be used to generate a desired signal.

Abstract: A system and method are disclosed for testing a settling time of a device-under-test (DUT). A method for determining a settling time of a device-under-test (DUT) includes activating a DUT to generate an output signal and mixing the output signal of the DUT and a reference signal to generate a mixed signal. An amplitude threshold is set for the mixed signal relative to an amplitude of the mixed signal and the settling time of the DUT is determined based on a last time that the amplitude of the mixed signal crosses the amplitude threshold relative to the activation of the DUT.

Abstract: A power monitoring device is disclosed. In at least one embodiment, the power monitoring device includes a power parameter measurement unit for calculating the measurement results of basic power parameters according to acquired digital signals of a voltage and/or a current; and a power quality analysis unit including a field programmable gate array, for obtaining power quality analysis results by executing a wavelet transform algorithm, a fast Fourier transform algorithm, an artificial neural net algorithm or a fuzzy logic algorithm in a parallel mode according to the acquired digital signals of voltage and/or current to perform analysis of stationary and transient power quality disturbances. Since the power monitoring device of at least one embodiment of the present invention employs a field programmable gate array, it can perform power quality analysis, power parameter measurements and other peripheral functions with relatively good performance.

Abstract: Parallelism in a processor is exploited to permute a data set based on bit reversal of indices associated with data points in the data set. Permuted data can be stored in a memory having entries arranged in banks, where entries in different banks can be accessed in parallel. A destination location in the memory for a particular data point from the data set is determined based on the bit-reversed index associated with that data point. The bit-reversed index can be further modified so that at least some of the destination locations determined by different parallel processes are in different banks, allowing multiple points of the bit-reversed data set to be written in parallel.

Abstract: An interlace motion artifact detector which identifies video image spatial frequencies characteristic of motion artifacts. The detected frequency is the maximum which can be represented by the vertical sampling rate of the video format (i.e., the Nyquist frequency). This frequency is detected by a pair of partial Discrete Fourier Transforms (DFT) which each calculate only the frequency component of interest. Additional vertical frequency components at one half and one quarter the interlace motion artifact frequency are also detected via a partial DFT. The presence of these lower frequencies acts as an indication of an erroneous motion artifact detection. Additionally, the dynamic range and maximum level of the video data is used as an indication of when to boost the frequency detection levels in areas of low brightness and/or contrast.

Abstract: A cyclic equation setting unit transforms and sets a Taylor series equation for calculating a sine function into a single cyclic equation common to terms of the Taylor series equation, the single cyclic equation having a new known number Q that is defined by multiplying a known number Q and the square of a variable X, shifting the result by a shift number S and then adding a constant K thereto. An adjustment unit adjusts and prepares the shift number S such that within a variation range of the variable X the variable X has a maximum value 1 with the constant K being not greater than 1. A cyclic equation executing unit inputs and converts angle information i to the variable X, and executing the cyclic equation in sequence from higher order term to lower order term for the number of terms of the Taylor series equation to derive a sine function of the angle information i.

Abstract: A method for determining an optimum sampling frequency to be performed by a power analyzer includes the following computer-implemented steps: sampling a time domain signal to obtain a sampling signal according to a predetermined sampling frequency; obtaining two reference sampling signals using higher and lower sampling frequencies compared to the predetermined sampling frequency; transforming the sampling signal and the reference sampling signals to frequency domain signals; computing a sum-of-amplitudes for each of the three frequency domain signals; estimating a minimum sum-of-amplitudes value and a corresponding re-sampling frequency; obtaining a new reference sampling signal using the re-sampling frequency; transforming the new reference sampling signal to a frequency domain signal, and computing a sum-of-amplitudes therefor; and re-estimating the minimum sum-of-amplitudes value and the corresponding re-sampling frequency.

Abstract: A method for establishing a simulating signal suitable for estimating a complex exponential signal includes the following computer-implemented steps: sampling a time domain signal of a physical system to obtain a sampling signal; transforming the sampling signal to a frequency domain signal using Fast Fourier Transform; determining parameters of the frequency domain signal; establishing a simulating signal; establishing a target function which is a deviation of the simulating signal from the sampling signal; obtaining correcting factors; iterating the target function using a gradient method and the correcting factors to obtain three sets of iterated signal parameters; obtaining corrected parameters using quadratic interpolation; and using the corrected parameters to correct the simulating signal, and establishing an updated target function. The simulating signal can be used to estimate dynamic behavior of the physical system if the updated target function converges to a tolerable range.