Abstract: A multiplier of a binary number A by a binary number B may be configured to add each term AiBj with a left shift by i+j bits, where Ai is the bit of weight i of number A, and Bj the bit of weight j of number B. The multiplier may include a first counter associated with the number A and may count modulo n and be paced by a clock. The multiplier may include a second counter associated with the number B and paced by the clock. Switching circuitry may produce the terms AiBj by taking the content of the first and second counters respectively as weights i and j. Shifting circuitry is configured to shift the content of one of the first and second counters when the other counter has achieved a revolution.

Abstract: The invention provides a reconfigurable module allowing morphological operations to be carried out for image processing. The module includes an operational block having five inputs, three outputs, three adders/subtracters and four logic blocks. The logic blocks provide various routings between the three adders/subtracters to enable the outputs to deliver the result of basic operations carried out on the five inputs. The reconfigurable module has a reduced number of components while at the same time allowing various morphological operations to be performed whose parameters can be modified. Furthermore, the reconfigurable module is serially combined to carry out more complex morphological operations. The invention also provides a method for implementing the reconfigurable module allowing an integral image, an eroded image, an expanded image, a distance image or projections along the rows and columns of the original image to be determined starting from an original image.

Abstract: Systems and methods are provided for efficiently counting detected events via a multiplicative group counter. An equivalent class polynomial congruent with a first of a plurality of elements comprising a multiplicative group is represented as a series of binary values. The represented polynomial is subjected to a state transition function as each event is detected, such that the series of binary values is altered to represent a new equivalent class polynomial congruent with a second of the plurality of elements of a multiplicative group. The series of binary values is decoded to determine a number of detected events recorded by the counter.

Abstract: A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.

Abstract: A multiplier and a method multiply, using an array of adders, two binary numbers X and Y defining a matrix [Eni=xn?i·yi], wherein the initial matrix [Eni=xn?i·yi] is transformed into a matrix [Eni=(xn?i?yi)·(yi?1?yi)=(xn?i?yi)·Yi] with Yi=yi?1?yi or [Eni=eni·Yi] with eni=xn?i?yi. A first approximation Un0 and Rn?1i?1 is formed of the sum and carry of the first two rows y0 and y1 of this matrix, and this is used as an input for the following estimation step which is repeated for all the following rows, successively carrying out the addition of the following yi+1 rows up to the last non-zero row, according to a first given series of propagation equations, and then the propagation of the carries Rni?1 is carried out over the zero yi+1 rows according to a second given series of propagation equations, in order to obtain the final result of the product P.

Abstract: The number of multipliers of a particular size that are required to perform a multiplication larger than that size is reduced. In the example of a 36-bit-by-36-bit multiplication, the number of 18-bit-by-18-bit multipliers required may be reduced from four to three. This may be achieved by using recursive decomposition techniques. As discussed in more detail below, if for each of two 36-bit numbers, the “digits” of each respective 36-bit number are added together, and then the two sums are multiplied, the resulting term can be combined additively with the product of the least-significant group of bits of the two 36-bit numbers and the product of the most-significant group of bits of the two 36-bit numbers to provide the desired product. A specialized processing block includes structures to facilitate the recursive decomposition technique.

Abstract: A method and apparatus are described for performing multiplication in a processor to generate a product. In one embodiment, a 64-bit multiplier and a 64-bit multiplicand may be multiplied together over four cycles by merging different partial product (PP) subsets, generated by a Booth encoder and a PP generator, with feedback sum and carry results. The logic inputs of a plurality of multiplexers may be selected on a cyclical basis to efficiently compress (i.e., merge) each PP subset with feedback sum and carry results. A pair of preliminary sum results stored during one cycle may be outputted during a subsequent cycle and processed by a logic gate (e.g., an XOR gate) to generate a feedback sum result that is merged with a feedback carry result and a PP subset. Final sum and carry results may be added to generate the product of the multiplier and the multiplicand.

Abstract: A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.

Abstract: A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M.

Abstract: Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.

Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. Circuitry that controls when an input is signed or unsigned facilitates complex arithmetic.

Abstract: In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.

Abstract: A multiplier includes an operation unit that adds or subtracts a first group selected from a current input data, and a second group selected from a next input data corresponding to the first group to generate an operation result, a Booth's encoder that encodes the operation result according to Booth's algorithm, and generates code data, a partial product generation unit that calculates a partial product from the code data as a first partial product, and calculates, in a case where the first group and the second group are specific combination, a second partial product, and an adder that cumulatively adds an output from the partial product generation unit. The specific combination is a combination in which the highest-order bit of each of the first group and the second group is the same value, and the third least significant bit obtained after the subtraction operation is 1.

Abstract: There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks inputting data of a second bit width different from the first bit width and performing computation; a second network connected to outputs of the plurality of second logic blocks; and a third network connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner.

Abstract: A circuit structure efficiently multiplies a first and second number. The circuit structure includes multipliers for the pairs of three-bit digits of the first number and three-bit digits of the second number. The multipliers produce six-bit partial products from the pair of three-bit digits of the first and second numbers. Each multiplier includes look-up tables receiving the pair of three-bit digits of the first and second numbers. A summing-tree circuit includes adders arranged in a series of levels, the adders in an initial one of the levels producing partial sums from the six-bit partial products from the multipliers, and for each first and successive second ones of the levels in the series, the adders in the second level producing another plurality of partial sums from the partial sums from the first level. A last one of the levels includes the adder that produces a product of the first and second numbers.

Abstract: A programmable integrated circuit device includes a plurality of specialized processing blocks. Each specialized processing block may be small enough to occupy a single row of logic blocks. The specialized processing blocks may be located adjacent one another in different logic block rows, forming a column of adjacent specialized processing blocks. Each specialized processing block includes one or more multipliers based on carry-save adders whose outputs are combined using compressors. Chain-in and chain-out connections to the compressors allow adjacent specialized processing blocks to be cascaded to form arbitrarily large multipliers. Each specialized processing block also includes a carry-propagate adder, and the carry-propagate added in the final specialized processing block of the chain provides the final result. The size of the multiplication that may be performed is limited only by the number of specialized processing blocks in the programmable integrated circuit device.

Abstract: An arithmetic operation circuit includes: an extractor circuit that extracts one or a plurality of bits consecutive from a most significant bit or from a least significant bit of a binary number; a sum register that stores an X-adic sum, where X is an integer more than two; and an update circuit that updates the stored X-adic sum with a value obtained by adding a first X-adic number to be cyclically multiplied by a certain coefficient to the X-adic sum in accordance with the extracted one or plurality of bits.

Abstract: A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a base-2 exponent at compile-time. The mantissa and exponent are preferably combined into a single unit (a word) of memory. At runtime either single multiplication and accumulation or matrix multiplication and accumulation is preferably achieved by a microprocessor or DSP instruction designed to use the mantissa-exponent pairs stored in a word of memory. The microprocessor instruction multiplies a fixed point runtime variable x by the mantissa and the result is shifted to the right or left as indicated by the exponent, which is preferably a 2's complement number. The complete instruction sequence to perform the multiplication can be made reentrant and can be pipelined.

Abstract: The present invention provides processing systems, apparatuses, and methods that support both general processing processor (GPP) and digital signal processor (DSP) features, such as vector and single value multiplication. In an embodiment, fractional arithmetic, integer arithmetic, saturation, and single instruction multiple data (SIMD) operations such as vector multiply, multiply accumulate, dot-product accumulate, and multiply-subtract accumulate are supported. In an embodiment, the process core and/or multiplier multiplies vector values or single values by creating partial products for each desired product. These partial products are added to produce intermediate results, which are combined in different ways to support various GPP and DSP operations.

Abstract: Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N?=Nrt2f mod M+NL and, subsequently, determining N? mod M.

Abstract: Provided is an apparatus for encryption/decryption and electronic signature in a mobile communication environment. A signal processing apparatus, performing modular multiplication in an electronic device, includes a first logic for outputting a signed multiplicand by selectively performing a one's complementary operation on a multiplicand according to a Booth conversion result of a multiplier in modular multiplication; a second logic for outputting a modulus which is signed in the modular multiplication based on a carry input value Carry-in of a current clock, determined from a carry value cin for correction of a previous clock, and on a sign bit of the multiplicand; and a third logic for receiving the signed multiplicand and the signed modulus, and calculating a result value of the modular multiplication by iteratively performing a full addition operation on a carry value C and a sum value S of the full addition operation, found at the previous clock.

Abstract: A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central processing unit. The central processing unit includes a carry save adder configured to add a plurality of partial products obtained from the product of the first term and the second term to obtain a first partial result and a second partial result, a multiplexer configured to output one selected from the group consisting of the second term, the third term, and zero, and an alignment shifter configured to shift an output of the multiplexer to align the output of the multiplexer with the first partial result and the second partial result to obtain a shifted term. The shifted term, the first partial result and the second partial result are added together to obtain a result of the binary operation.

Abstract: Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result.

Abstract: Some embodiments provide a method of performing a mathematical operation on a set of operands. The mathematical operation includes several sub-operations. The method examines several bits of at least one operand at a time and depending on the value of these bits, reconfigures a single logic circuit to perform one of the sub-operations to generate a partial result of the mathematical operation. In some embodiments, the logic circuit is reconfigured by receiving a first set of configuration data that cause the logic circuit to reconfigure to perform a first sub-operation operation and a second set of configuration data that cause the logic circuit to reconfigure to perform a second sub-operation. In some embodiments, the logic circuit receives different inputs based on the value of the bits being examined. In some embodiments, the mathematical operation is multiplication and the sub-operations are addition and subtraction.

Abstract: Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor may be multiplied by a numerator at least in part using a first logic circuit configured to perform multiplication. The first numerical factor may also be multiplied by a denominator. A second numerical factor may be calculated based, at least in part, on an approximation of a square of the difference between unity and the product of the first numerical factor and the denominator. The second numerical factor may be multiplied by the product of the numerator and the first numerical factor at least in part using the first logic circuit, to generate an approximation of a quotient of the numerator and the denominator.

Abstract: A multiplier has a multiplication array in which partial products are generated by performing multiplication between a multiplier and a multiplicand, and a partial product control circuit which generates an enable signal for activating an effective region in the multiplication array corresponding to effective figures of the multiplier and the multiplicand. The effective figures depend on the format of the multiplier and the multiplicand. The partial product control circuit controls the status of the enable signal according to a multiplication command designating the format. The multiplication array is constituted by a dynamic circuit. The dynamic circuit in an initial stage of the multiplication array has a switch which is turned on/off by the enable signal. When the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.

Abstract: A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the value of the physical property for each subset, and applying to the subset of lateral points a step of horizontal transversal statistical processing by using the estimations of the value of the physical property, to verify a hypothesis about the variables manipulated by the integrated circuit.

Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.

Abstract: Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.

Abstract: Provided are a high speed and low power fixed-point multiplier and method thereof. The multiplier includes: a partial product calculation unit for dividing input data into a plurality of bit groups, each bit group having a predetermined number of bits, generating partial products by independently multiplying a fixed coefficient for each bit group, and summing partial products included in a corresponding bit group, to thereby generate a summed partial products; and an adding unit for adding the summed partial products of each bit group generated from the partial product calculation unit.

Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

Abstract: A multiplication or division operation X·K or X·1/K is performed in an electronic circuit. A software circuit area of the circuit calculates a digit shift sv such that psv is an approximate value for K. In a hardware circuit area, the value X is shifted sv digits to the left in the case of multiplication or sv digits to the right in the case of division. The software circuit area calculates a suitable correction factor Kf. The value X is multiplied by the correction factor Kf.

Abstract: A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M.

Abstract: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.

Abstract: A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.

Abstract: A Galois field multiplier is provided, comprising a multiplication circuit for inputting two m bits binary multiplicators and outputting their product, wherein m is an integral power of 2, and the output of said multiplication circuit is consisted of a high bits portion output and a low bits portion output; a memory for storing a Galois field multiplication coefficient array calculated from a selected Galois field primitive polynomial; a first module for performing operation on the output of said multiplication circuit and the Galois field multiplication coefficient array stored in said memory to obtain the product of the two m bits binary multiplicators over Galois field. The Galois field multiplier has small hardware footprint, short response latency and strong universality.

Abstract: Methods and apparatus for converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of ?2, ?1, 0, 1, 2, wherein the set of encoded bits includes: a first bit that is true when the associated number is 2, a second bit that is true when the associated number is ?2, a third bit that is true when the associated number is either negative or zero, and a fourth bit that is true when the associated number has an absolute value of 1.

Abstract: A combining circuit and method combines a plurality of terms in a multiplier circuit. The combining circuit includes a first circuit, arranged to receive a first set of the plurality of terms and to combine the first set of terms to produce a first combined term set. The combining circuit also includes a second circuit, arranged to receive a second set of the plurality of terms and to combine the second set of terms to produce a second combined term set. The combining circuit further includes a third circuit, arranged to receive the first and second combined term sets and to combine the first and second combined term sets to produce a third combined term set. The combining circuit outputs the first combined term set as a first combination result and the third combined term set as a second combination result.

Abstract: Some embodiments provide a novel way of performing a signed multiplication. Each individual bit of a first operand is multiplied by every bit of a second operand to generate partial multiplication results. Each partial result is shiftably added to other partial results except one partial result which is shiftably subtracted. For the partial result that is subtracted, the most significant bit of the second operand is negated and is utilized as carry in of the subtraction operation. The most significant bit of each operand is considered to have a negative sign when generating the partial multiplication results. Also, one of the partial results is appended with the most significant bit of the second operand. Some embodiments utilize a configurable IC that performs subtraction with the same circuitry and at the same cost as addition. The configurable IC also utilizes hybrid interconnect/logic circuits to perform part of the multiplication operation.

Abstract: A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal output. The first and second circuits receive the three-bit block as an input and generate their respective outputs based on the setting of each of the bits. The third circuit receives only the most significant bit of the three-bit block as its input and generates an invert signal output based on the setting of the most significant bit. In each of these circuits, the number of complex gates and transistors is minimized thereby reducing gate delay and power consumption in generating the control signals for performing a Booth multiplication operation.

Abstract: A Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal output. The first and second circuits receive the three-bit block as an input and generate their respective outputs based on the setting of each of the bits. The third circuit receives only the most significant bit of the three-bit block as its input and generates an invert signal output based on the setting of the most significant bit. In each of these circuits, the number of complex gates and transistors is minimized thereby reducing gate delay and power consumption in generating the control signals for performing a Booth multiplication operation.

Abstract: A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table.

Abstract: A multiplication apparatus including a multiplier and multiplicand extractor for dividing the multiplicand into partial multiplicands and dividing the multiplier into partial multipliers, and for generating partial input pairs by combining the partial multiplicands with the partial multipliers, and a multiplication executor including identical partial multiplication modules for receiving the partial input pairs and outputting partial carries and partial products. The apparatus further includes an output generator for combining the partial carries with the partial products according to the execution instruction to generate a final output. For simple multiplications, each of the partial multiplication modules can pass data to and from an adjacent partial multiplication module to calculate the partial carry and the partial product, and pass bits exceeding its own multiplication coverage.

Abstract: A sequential multiplier for multiplying a binary multiplier and a binary multiplicand to produce a final product. A first logic circuit generates a control signal based on the multiplier. A second logic circuit generates a partial product based on the control signal and the multiplicand. A full adder generates a partial sum and a partial carry in each of a sequence of cycles. In the first cycle the partial sum and the partial carry are both initialized to zero. In each said cycle the partial sum, the partial carry, and the partial product are added to generate a new partial sum and a new partial carry. After a last cycle, the partial sum is the final product.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions on a set of inputs. The IC also includes several input select interconnect circuits for selecting the input set supplied to each configurable logic circuit. Each input select interconnect circuit is associated with a particular configurable logic circuit. When a configurable logic circuit is used to perform a multiplication operation, at least one of its associated input select interconnect circuits performs a logic operation that implements part of the multiplication operation.

Abstract: An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.

Abstract: A high-speed integer multiplier unit multiplying operands, wherein each operand can be either signed or unsigned. Type data is received for each operand which indicates whether the corresponding operand is to be treated as signed or unsigned. An extend bit is appended to each operand to provide extended operands, where the extend bit is the most significant bit of the corresponding operand if type data indicates that the operand is signed, and the extend bit is a logic zero otherwise. The extended operands are multiplied using a signed multiplication operation to provide the result. Overflow detection is done in parallel to the multiply operation, thus moving overflow-detection logic from the timing-critical path from the multiplier block's input to its output. The throughput performance of the multiplier unit is improved as a result.

Abstract: A multiplication engine is described in which a decision threshold engine utilizes a Y-adder powers of two shift table to iteratively generate shift-add combinations. The shift-add combinations are output in a sequence with decreasing levels of contribution wherein the accuracy of the associated multiplication increases up to any desired level of accuracy to meet the requirements of the application. The multiplication engine can be used for generating the combinations either statically or dynamically. One embodiment describes a Y-adder hardware slider table engine in which the shift table is implemented with shifters and adders that can be set for active state or pass through state, and selectively summed to generate a product result directly from the table without the need to combine shift and add hardware.

Abstract: Digital mixers which permit mixing of asynchronous signals are constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), an RSFQ D flip-flop, an RSFQ XOR circuit, and an RSFQ T flip-flop. A binary tree arrangement of T flip-flops can be used to provide in-phase and quadrature phase-divided replicas of a reference signal. The mixing elements can be either an XOR circuit, a dual port NDRO circuit functioning as a multiplexer or an RS type NDRO functioning as an AND gate. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.