Abstract: A carry look-ahead circuit for an adder to decrease circuit size and power consumption. The carry look-ahead circuit is composed of 2-input NAND gates 101, 102, 2-input NOR gate 103, AND-NOR type composite gates 201, 202, OR-NAND type composite gate 251, or other gates with 2 or less series stages of transistors inserted between the output terminal and the power source line or the ground line. When the number of series stages of transistors increases, the driving power decreases. Consequently, in order to maintain the same operation speed, it is necessary to increase the transistor size. The use of multi-input NAND gates and NOR gates, makes it possible to suppress the number of series stages of transistors and to reduce the transistor size. As a result, it is possible to decrease the circuit size and power consumption.

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Abstract: A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a Manchester-carry-chain configured bit carry circuit to generate first bit carry signals where a block carry exists in each of the M blocks and second carry bit signals where no block carry exists, based on the bit values; a control circuit to generate, independently of a clock enable signal at a logical level, selection-control signals based upon the block carry signals; and a summation selection circuit to select between the first bit carry signals and the second bit carry signals and to add the carry propagation bit values and the selected carry signals.

Abstract: A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry signal is generated. By forming rules for generating and propagating null-carry signals through blocks and groups of blocks within the adder, a maximum P-channel stack depth of two can be achieved for a four-bit adder block, thereby substantially improving the speed of the null-carry-lookahead adder, compared to a convention carry-lookahead adder that is based on generating and propagating carry signals within the adder.

Abstract: One embodiment of the present invention provides an apparatus for facilitating an addition operation between two N-bit numbers, wherein the apparatus has a regular structure. The apparatus includes a carry circuit for generating at least one carry signal for the addition operation, wherein the carry circuit includes a plurality of logic blocks organized into rows that form approximately logN successive stages of logic blocks. Each of these logic blocks provides current for at most a constant number of inputs in a successive stage of logic blocks. Additionally, within a given stage of logic blocks, outputs from multiple logic blocks are ganged together to drive a signal line that feeds multiple inputs in a successive stage of logic blocks. Furthermore, there are at most a constant number of lateral tracks in a planar layout of signal lines between the successive stages of logic blocks.

Abstract: The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only one of the signals would be high at any time, and the other two would be low. The Pin signal for a bit is true where the bit has a carry in that is the same as the carry in to the block of bits, i.e., the carry in to the block is propagated up to the particular bit. The Kin signal for a bit is true where a carry in to the bit is zero regardless of the carry in to the block, i.e., any carry in to the block is killed before it gets to the bit. The Gin signal for a bit is true where the bit has a carry in of one regardless of carry in to the block, i.e., the carry in to the bit is generated within the block. These signals are used in the calculation of the sum of the operand bits.

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Abstract: A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry signals. In a method for producing a carry logic circuit, a group generate logic function GI, I+1=GI OR GI+1 AND PI is to be performed. When GI+1=CI+1, GI, I+1=CI, arrival times of generate signals GI and GI+1, are investigated. If GI arrives before GI+1, a complex AND-OR-INVERT gate is used, otherwise a cascaded pair of NAND gates is selected. To produce a complementary carry signal, a logic function GI, I+1′=GI′ AND GI+1′ OR PI′ is to be performed. If the generate signal GI′ arrives before GI+1′, a complex OR-AND-INVERT gate is used, otherwise a cascaded pair of NOR gates is selected.

Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

Abstract: A method of image sampling and an apparatus thereof. The apparatus comprises: an adder; a first register, the output of which is fed back to the adder; a first multiplexer, which outputs a ratio or a weighted parameter; a multiplier, which receives an input image value and the output of the first multiplexer; an adder/subtracter, which receives the output of the multiplier; a second multiplexer, which receives the output of the adder/subtracter and the multiplier; and a second register, which receives the output of the second multiplexer. By the method of approximation and recursion, the input image data can be processed in real time to produce the output image data.

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Abstract: A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a unit length. Each carry foreknowledge circuit block has a plurality of arithmetic operating portions (j, i) in correspondence to each bit, that respectively receive a block carry Cin corresponding to the most significant bit in a lower the carry foreknowledge circuit block from the lower carry foreknowledge circuit block corresponding to lower divisional portion, each arithmetic operating portion arithmetically operating the carry Ci on the basis of the block carry Cin, and outputting the carry Ci to the adding circuit, and each arithmetic operating portion (j, i) has a logic circuit portion which receives the block carry Cin and is arranged on an output terminal side.

Abstract: An adding circuit which receives addend data and augend data, each of which consists of a plurality of bits, and sums the addend and augend data, comprises: a plurality of addition blocks, each of which is used to add a predetermined number of bits of the addend data to a like number of bits of the augend data, and for outputting both the result obtained by adding the predetermined number of bits and a carry-out signal, wherein, when a carry-out occurs for one of the addition blocks, in accordance with a carry-out signal from a lower rank and a set comprising the addend data and the augend data, the pertinent addition block responds to the pertinent carry-out, and wherein, when a carry-out does not occur for the addition block in accordance with the set comprising the addend data and the augend data, the pertinent addition block responds to the carry-out and generates a block addition end signal which indicates that the addition performed by the addition block has been completed.

Abstract: One embodiment of the present invention, an eight bit binary adder with a typical latency independent of its width, is described. The adder comprises a four bit adder for calculating bits S3-S0 of the sum, plus four bitslice circuits, one for speculatively calculating each of bits S7-S4 of the sum. The calculation of the carry bit out of each bitslice is limited to the operands bits into that bitslice and the three preceding bitslices. Each bitslice also includes circuitry for detecting a potential error in the speculative sum such that the speculative sum can be corrected when there is a potential error.

Abstract: A carry look-ahead adder capable of adding or subtracting two input signals includes first stage logic having a plurality of carry-create and carry-transmit logic circuits each coupled to receive one or more bits of each input signal. Each carry-create circuit generates a novel carry-create signal in response to corresponding first bit-pairings of the input signals, and each carry-transmit circuit generates a novel carry-transmit signal in response to corresponding second bit-pairings of the input signals. The carry-create and carry-transmit signals are combined in carry look-ahead logic to generate accumulated carry-create signals, which are then used to select final sum bits.

Abstract: An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits are configured to generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. Each generate bit is the logical AND of its corresponding bits in the first and second operand while each propagate bit is the EXOR of its corresponding bits, and each kill bit is the logical NOR of its corresponding bits.

Abstract: A carry-out bit generator determines if a bit pattern from two positive numbers matches one of the patterns for which a carry-out bit would be generated in addition. These patterns include a TnG pattern and a Tm pattern (with a carry-in). Superscript n represents a number between zero and m−1, superscript m represents the number of registers, T represents a 0/1 or 1/0 pair and G represents a 1/1 pair.

Abstract: A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR3 block and an AXOR block for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a sum-lookahead carry signal, respectively. The modified full adder includes an XOR2 block and a MUX2 block for receiving the first sum signal from the sum-lookahead-full adder, a fourth input, and a sum-lookahead carry signal from a backward adjacent adder to generate a second sum signal and a carry signal, respectively.

Abstract: An n-bit carry-skip adder includes a number of carry-skip stages and a logic circuit associated with one or more of the stages. The logic circuit includes split-adder logic and carry-skip logic configured such that a split control signal associated with the split-adder logic is applied to at least one gate of the carry-skip logic, so as to reduce a carry propagation delay of the adder. In an illustrative embodiment, the logic circuit is associated with an (n/2+1)th carry-skip stage of the adder, and the adder is configured to perform two parallel n/2-bit additions when the split control signal is at a first logic level, and to perform a single n-bit addition when the split control signal is at a second logic level. Advantageously, the invention allows the split-adder logic to be incorporated in a manner which minimizes the carry propagation delay without increasing the required circuit area.

Abstract: A digital adder circuit is implemented using a Kogge-Stone architecture. Various embodiments utilize single-ended domino circuits, to which are input single-ended primary addends. Dual-function generator circuits generate differential sum and sum-complement output signals. The use of low VT devices and full CMOS circuitry provides a relatively high degree of noise immunity. Also described are a microprocessor having an ALU incorporating one or more of the adder circuits, as well as a method of adding two numbers which generates differential sum and sum-complement outputs but does not use full-differential domino circuits, thus providing considerable savings in circuit area, circuit conductors, and layout complexity.

Abstract: Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carry-skip paths. In one implementation, such a binary adder includes a network of carry-processing cells for producing kill, generate, and propagate signals and carry-skip cells for bypassing certain bit positions with dual-wire differential signal paths to provide high-speed processing of adding operations.

Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

Abstract: A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a sum of each set of binary numbers. Each set of numbers defines a distinct data path through the adder. For each set of numbers, the system further includes a logic gate for inhibiting a carry path, from each portion of the adder corresponding to each carry path, to a next adjacent carry path. The system isolates two or more contiguous data paths through the fixed-width adder corresponding to each of the two or more sets of two binary numbers. The invention prevents unwanted signals from crossing summing lane boundaries in different processing modes. The same adder logic can thus be used for each processing mode by varying the combination of mode select control signals.

Abstract: A carry look-ahead digital adder that adds a first operand A of n bits and a second operand B of n bits, with n=2m, including: a first block calculating couples of signals Pq and Gq from the bits of rank q, Aq and Bq, of the first and second operand, with Pq=Aq+Bq and Gq=Aq•Bq; and a second block formed of a regular array of elementary cells of identical functions arranged in n rows and m columns, and elementary cells having two couples of inputs {E1, E2} and {E3, E4} and one couple of outputs {O1,O2}, providing O1=E1•E3 and O2=E2•E4+E3; the elementary cells being interconnected to optimize the propagation speed of the internal signals along a tree-like path.

Abstract: A carry lookahead adder having a reduced internal block fanout which is achieved efficiently in terms of the silicon area needed to implement the carry lookahead adder. The carry lookahead adder of the present invention is characterized by a modified tree structure having carry generate/propagate signal operators located in such a manner that the maximum internal block fanout is equal to (adder width)/8 for adders having a width of at least 16 bits. For adders having a width of less than 16 bits, the internal block fanout is 2. The routing complexity is increased in order to implement redundant overlapping carry generate/propagate operations which, in turn, decreases the internal block fanout of the adder. However, increases in routing complexity can be accomplished within the minimum X-by-Y area of each stage of the adder. Therefore, the overall performance of the carry lookahead adder of the present invention can be optimized while meeting minimum area requirements.

Abstract: The present invention provides an improved method and apparatus for performing decimal arithmetic using conventional parallel binary adders. In a first aspect of the present invention, a method for implementing decimal arithmetic using a radix (base) 100 and a method for implementing radix 1000 numbering system are disclosed. The first aspect of the present invention implements decimal arithmetic utilizing radix 100, where one-hundred decimal numbers, 0 through 99, are represented using seven BCD bits. In a second aspect of the present invention, a specialized high-speed radix 100 parallel adder is disclosed.

Abstract: An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. The computation stages for each of the bit positions include a sum computation stage implemented in logic circuitry. For a subset of the bit positions, the corresponding sum computation logic circuitry computes a sum based at least in part on group-generate, group-transmit and intermediate carry signals. Advantageously, the sum computation logic circuitry is configured to exploit differences in delay associated with generation of the group-generate, group-transmit and intermediate carry signals, so as to reduce the total computational delay of the adder.

Abstract: An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. In accordance with an illustrative embodiment of the invention, the prefix trees are interconnected such that carry signals are computed at least partially in parallel. For example, a carry signal computed in an initial stage of a given prefix tree is used in subsequent stages of the given prefix tree without introducing substantial additional delay in computation of other carry signals in other prefix trees associated with higher bit positions. Carries computed for lower bit positions are thus used to compute carries for higher bit positions, but generate, propagate and/or transmit signals may be generated in an initial stage of each of the prefix trees without utilizing a primary carry input signal in the computation. The resulting adder architecture provides reduced logic depth, delay and circuit area relative to conventional architectures.

Abstract: A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (m+2) of logical stages is n=2m+1 and for bit lengths n not of a binary order, the number (m+2) of logical stages is nb0=2m+1, where nb0 is the next largest binary order after n.

Abstract: The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only one of the signals would be high at any time, and the other two would be low. The Pin signal for a bit is true where the bit has a carry in that is the same as the carry in to the block of bits, i.e., the carry in to the block is propagated up to the particular bit. The Kin signal for a bit is true where a carry in to the bit is zero regardless of the carry in to the block, i.e., any carry in to the block is killed before it gets to the bit. The Gin signal for a bit is true where the bit has a carry in of one regardless of carry in to the block, i.e., the carry in to the bit is generated within the block. These signals are used in the calculation of the sum of the operand bits.

Abstract: The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only one of the signals would be high at any time, and the other two would be low. The Pin signal for a bit is true where the bit has a carry in that is the same as the carry in to the block of bits, i.e., the carry in to the block is propagated up to the particular bit. The Kin signal for a bit is true where a carry in to the bit is zero regardless of the carry in to the block, i.e., any carry in to the block is killed before it gets to the bit. The Gin signal for a bit is true where the bit has a carry in of one regardless of carry in to the block, i.e., the carry in to the bit is generated within the block. These signals are used in the calculation of the sum of the operand bits.

Abstract: A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry signal is generated. By forming rules for generating and propagating null-carry signals through blocks and groups of blocks within the adder, a maximum P-channel stack depth of two can be achieved for a four-bit adder block, thereby substantially improving the speed of the null-carry-lookahead adder, compared to a convention carry-lookahead adder that is based on generating and propagating carry signals within the adder.

Abstract: One embodiment of the present invention provides an apparatus for facilitating an addition operation between two N-bit numbers, wherein the apparatus has a regular structure. The apparatus includes a carry circuit for generating at least one carry signal for the addition operation, wherein the carry circuit includes a plurality of logic blocks organized into rows that form approximately logN successive stages of logic blocks. Each of these logic blocks provides current for at most a constant number of inputs in a successive stage of logic blocks. Additionally, within a given stage of logic blocks, outputs from multiple logic blocks are ganged together to drive a signal line that feeds multiple inputs in a successive stage of logic blocks. Furthermore, there are at most a constant number of lateral tracks in a planar layout of signal lines between the successive stages of logic blocks.

Abstract: In an adder circuit, a block carry generation logic over three consecutive digits is produced from the following equations. G0=g2+p2·g1+p2·p1·g0 /g0=/p2+/g2·/p1+/g2·/g1·/g0 In other words, the block carry generation logic /G0 is produced by a single PMOS transistor, a series circuit formed of two PMOS transistors connected in series, and a series circuit formed of three PMOS transistors connected in series. The block carry generation logic G0 is produced by a single NMOS transistor, a series circuit formed of two NMOS transistors connected in series, and a series circuit formed of three NMOS transistors connected in series. Block carry generation logics can be formed in such a way as to achieve not only a reduction of the layout area but also a higher operation rate.

Abstract: The inventive adder can perform carry look-ahead calculations for a bi-endian adder in a cache memory system. The adder can add one of +/−1, 4, 8, or 16 to a loaded value from memory, and the operation can be a 4 or 8 byte add. The inventive adder comprises a plurality of byte adder cells and carry look-ahead (CLA) logic. The adder cells determine which of themselves is the least significant bit (LSB) byte adder cell. The LSB cell then adds one of the increment values to its loaded value. The other cells add 0x00 or 0xFF, depending upon the sign of the increment value, to a loaded value from memory. Each adder performs two adds, one for a carry-in of 0, and the other for a carry in of 1. Both results are sent to a MUX. The CLA logic determines each of the carries, and provides a selection control signal to each MUX. of the different cells.

Abstract: The sum interval detector has two n-bit inputs, a 1-bit carry input, and a 1-bit output, which is activated when the sum of the input values lies within the interval −2p . . . 2p−1 or the like. The circuit utilizes a known method to detect whether a sum is equal to a constant to detect whether the upper n−p bits of the sum are binary 000 . . . 0, i.e. 0, or binary 111 . . . 1, i.e. −1, while the lower p bits of the sum are ignored corresponding to XXX . . . X. The method requires that the carry at position p be known which occurs with a well known, fast carry look-ahead circuit. By adding inverters and two levels of full adders the sum interval detector is capable of deciding whether two effective addresses, which each is a sum of base address plus offset, are so close, that the associated data areas overlap.

Abstract: A multiplexer based adder circuit. The novel adder design is suitable for a number of bit sizes, but in one exemplary embodiment is a 64-bit adder. A complete 16-bit scaled adder is taught. The adder circuit is efficient and reconfigurable in that the adder can be partitioned to support a variety of data formats. The adder can add two 64-bit operands, four 32-bit operands, eight 16-bit operands, or sixteen 8-bit operands. The reconfigurability of the adder for different word sizes is achieved using only a small number of control signals for partitioning without increasing the adder size or reducing its speed. The novel adder circuit is designed using multiplexer circuits and two input inverted logic gates making the adder very fast. The adder design recognizes that pass transistor based multiplexer circuits and inverted logic gates are the fastest circuit elements for standard CMOS logic.

Abstract: An adder circuit can perform of two integers respective consisted of n=k m bits at high speed with a smaller scale circuit than that of an adder circuit employing a carry look ahead circuit. The adder circuit includes m in number of k-bit adding circuits connected in serial connection in such a manner that an carry output in a preceding digit is supplied to a carry input in a following digit, m in number of carry propagation alarm circuits provided corresponding to respective of m in number of k-bit adding means, for outputting carry propagation alarm signal only when carry input of corresponding adding means is propagated to a carry output, and OR circuit for performing OR for performing OR operation of the m in number of carry propagation alarm signals for generating a carry alarm signal, for leading a fixed result of addition from a final digit of the adding means in serial connection after extinction of generation of the carry alarm signal.

Abstract: An adder, a processor (such as a microprocessor or digital signal processor), and methods of adding in such adder or processor. In one embodiment, the adder includes: (1) a first and second units in a first logic layer, the first unit receiving first and second addend and augend bits and generating therefrom a first single group-carry-generate bit and first and second carry-propagate bits, the second unit receiving third and fourth addend and augend bits and generating therefrom a second single group-carry-generate bit and third and fourth carry-propagate bits and (2) a third unit in a second logic layer, coupled to the first and second units, that receives the first and second single group-carry-generate bits and the first, second, third and fourth carry-propagate bits and generates therefrom resulting group-carry-generate and group-carry-propagate bits.

Abstract: A logic gate, an adder and methods of operating and manufacturing the same. In one embodiment, the logic gate includes: (1) a summer, having at least two single-bit inputs and a noise-suppression input with corresponding conductances representing discrete weights, that generates a weighted sum of input binary digits presented at the at least two single-bit inputs and the noise-suppression input and (2) a quantizer, coupled to the summer, that generates an output binary digit at a binary output thereof that is a function of the weighted sum, the noise-suppression input increasing a noise tolerance of the logic gate.

Abstract: According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operands and the second number of operands. The first source register includes a plurality of first operands and the destination register includes a plurality of results. The number of arithmetic processors are respectively coupled to the first operands, second operands and results, wherein each arithmetic processor computes one of a sum and a difference of the first operand and a respective second operand.

Abstract: The present invention comprises a method and apparatus that selectably performs either addition or subtraction on two N-nary operands to generate an intermediate, then final, N-nary final result. If the intermediate result of the operation contains less bits than a full register, the intermediate result is “merged” with the second operand in that unaltered bits from the second operand are bypassed to the final result. Accordingly, the final result and the second operand have an equal number of bits.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries. Each selectable feature may be implemented singly, or in combination with other selectable features.

Abstract: A sum-and-compare circuit is provided which minimizes propagation delay and which minimizes the amount of die area required to implement the sum-and-compare circuit. The sum-and-compare circuit comprises a propagate/generate logic block followed by a carry-lookahead tree structure. The propagate/generate logic block receives a first operand, A, a second operand, B, and a third operand, J. The first operand A corresponds to an addend, the second operand B corresponds to an augend, and the third operand J corresponds to the twos compliment of the constant K. The propagate/generate logic block comprises logic configured to add the operand A to the operand B to obtain a first sum and logic configured to add the first sum to the operand J to obtain a plurality of propagate signals and a plurality of generate signals, which are then output from the propagate/generate logic block to a carry-lookahead tree structure.

Abstract: An apparatus and method that perform partitionable carry-lookahead logic on two N-nary operands. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. The present invention performs carry-lookahead logic to calculate a block carry-lookahead indicator for a grouping, or block, of bits. The present invention forces the block indicator to a “Halt” value if the block comprises the most significant block within a partition, thus interrupting the carry propagation chain on partition boundaries. The present invention supports interruption of the carry propagation chain for both addition and subtraction.

Abstract: A 3x adder for adding 2a to a, where a is a binary number, the binary numbers 2a and a partitioned so that 2a=(xk . . . x0) and a=(yk . . . y0)where xi and yi have the same size for each i=0, 1, . . . , k, where the 3x adder provides the group generate terms for the sums xi+yi, i=0, 1, . . . , k, according to Boolean expressions, where for any sum xi+yi where xi and yi each have size n1+1, the number of Boolean variables in the product terms in the Boolean expression for the group generate terms of xi+yi do not exceed j+1, where j is the largest integer not exceeding ni/2.

Abstract: An apparatus that takes two N-nary operands and selectably performs either addition or subtraction on them to produce an arithmetic result and a carry indicator. Carry-lookahead logic is utilized to create HPG signals for each N-nary dit of the intermediate sum of the two operands and also to create “block” HPG indicators for blocks of dits. In the preferred 1-of-4 embodiment, subtraction may be implemented as four's complement addition. The value of each dit of the intermediate sum is incremented by one before final output if a carry has propagated into the dit.

Abstract: A circuit and method for deriving an adder output bit from adder input bits, a multiplier circuit, a method of multiplying, a microprocessor and digital signal processor (DSP) employing the circuit or the method and a method of selecting weights and thresholds for logic gates. In one embodiment, the circuit includes: (1) first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of ones of the adder input bits and (2) combinatorial logic that generates the adder output bit from the intermediate bits. In one embodiment, the multiplier includes a summer having at least two inputs with corresponding weights, the inputs corresponding to bits of a multiplicand, the weights based on a multiplier, the summer generating a weighted sum of the multiplicand that represents a multiplication of the multiplicand and the multiplier that is a function of the weighted sum.