Abstract: A method and system for configuring at least one communication interface module in a control or automation system includes a communication interface module for coupling at least two field bus systems. At least one first functional unit integrated in the communication interface module implements a connection to a configured superordinate controller via a first communication link on the basis of a first field bus protocol. At least one second functional unit integrated in the communication interface module implements a connection for field devices via a second communication link on the basis of a second field bus protocol. At least one further, third functional unit integrated in the communication interface module is configured to connect further field devices via input and/or output functionalities integrated in the communication interface module, and at least one serial interface integrated in the communication interface module can be used to configure the communication interface module.

Abstract: A method for adjusting a link speed and a computer system using the same are provided. The method is used after executing a boot block code and before executing a bus enumeration procedure. A testing step is executed using a maximum link speed supported by both a bridge and a peripheral device. If the test fails, the link speed is adjusted down until the test succeeds, thus automatically adjusting the link speed of the bridge.

Abstract: An apparatus includes a transceiver device mounted on a printed circuit board and configured to selectively transmit and receive signals at a first data rate or signals at a second data rate. An X2 form factor pluggable connector disposed at one end of the printed circuit board includes first and second pins that respectively convey signals at the first and second data rates between the transceiver device and a system device. A port device disposed at an opposite end of the printed circuit board conveys signals between the transceiver device and a network device. A management circuit determines which of the first and second data rates is selected based on transmissions between the system device and the network device and controls the transceiver device to transmit and receive signal at the first data rate via the first pins and at the second data rate via the second pins.

Abstract: A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.

Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Abstract: A method for adding file based storage hardware to a block based storage system includes detecting, by the file based storage hardware, an electrical coupling between the file based storage hardware and the block based storage system, the block based storage system having a set of logical units (LUs) predefined as file based storage hardware specific LUs. The method includes forwarding, by the file based storage hardware, an initiator record to the block based storage system, the initiator record configured to control access by the file based storage hardware to data stored by the block based storage system and the initiator record having a file based storage hardware specific identifier. The method includes, following the block based storage system associating the initiator record having the file based storage hardware specific identifier with the predefined file based storage hardware specific LUs, establishing a communication path with the block based storage system.

Abstract: A method, computer system and computer program product for generating a configuration status of a computer is provided. A method for generating a configuration status of a computer includes reading a plurality of configuration items of the computer and executing a plurality of rules upon the configuration items that were read, wherein each rule comprises an if-portion including at least one configuration item and a then-portion including an action for storing a configuration status value if the at least one configuration item of the if-portion matches the configuration items that were read. The method can further includes executing an algorithm that reads each of the configuration status values that were stored responsive to executing the plurality of rules and processes the configuration status values so as to produce a final configuration status of the computer and storing a record indicating the final configuration status of the computer.

Abstract: A data storage device includes one or more data paths through electrical contacts of the data storage device. The data paths are operably connected to allow bits to be transferred into and out of the data storage device. The data storage device stores an indication of a number of the one or more data paths in a configuration register. A method includes performing, while the data storage device is operatively coupled to a host device, receiving a command of the host device to read the configuration register and providing the indication via at least one of the one or more data paths. Providing the indication enables indicating to the host device the number of the one or more data paths.

Abstract: A method of routing data in an information handling system can include receiving a notification from a management controller at a basic input/output system (BIOS) that includes a system management interrupt (SMI) handler. The a notification can indicate that the management controller has a data packet bound for a peripheral component interconnect express input/output (PCIe I/O) device coupled to a secondary processor. The method can include generating a system management interrupt at the information handling system via the BIOS SMI handler in response to the notification. The method can also include retrieving the data packet from the management controller via the BIOS SMI handler and sending a payload associated with the data packet from the BIOS SMI handler to the PCIe I/O device.

Abstract: The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.

Abstract: Method and system for configuring a serial interface. The system includes one or more input nodes each coupled to a corresponding serial bus. One or more output nodes are coupled to a respective serial bus, each output node having a respective driver. A voltage detection circuit determines the voltage at a configuration node. Mode of serial bus operation is based on the voltage level detected at the configuration node. In at least one mode of serial bus operation, the configuration node is used as a mode select input and power source for at least one output driver.

Abstract: A method and apparatus for reconfiguring hardware structures to pipeline the execution of multiple special purpose hardware implemented functions, without saving intermediate results to memory, is provided. Pipelining functions in a program is typically performed by a first function saving its results (the “intermediate results”) to memory, and a second function subsequently accessing the memory to use the intermediate results as input. Saving and accessing intermediate results stored in memory incurs a heavy performance penalty, requires more power, consumes more memory bandwidth, and increases the memory footprint. Due to the ability to redirect the input and output of the hardware structures, intermediate results are passed directly from one special purpose hardware implemented function to another without storing the intermediate results in memory.

Abstract: A robust method for addressing each of the participants of a bus system comprising a control unit, and a bus and a plurality of addressable participants connected to the bus, comprising the steps of a) pre-selecting a first number of participants, b) selecting from the pre-selected participants a second number of participants, and c) assigning one or more addresses to them, and repeating the steps a) to c). The selection and pre-selection is based on current sources, specific threshold values, and measurement error. The bus system and addressable device (are also claimed.

Abstract: A circuit board includes a first circuit area, a first processing unit and a conductive pattern. The first circuit area includes a plurality of first electrically contacts. The first processing unit, which includes a ball grid array (BGA) substrate, is disposed on the first circuit area and is electrically connected to the first electrically contacts. The BGA substrate has a plurality of solder balls and a bypass circuit. The conductive pattern is electrically connected to the first electrically contacts.

Abstract: Methods, apparatus and systems for implementing run-time fabric reconfiguration are described herein. In accordance with one aspect, techniques are disclosed for implementing run-time fabric reconfiguration on a System on a Chip (SoC) via use of multiple endpoint fabric interfaces having routing logic that is dynamically reconfigured at run-time by a fabric control unit in response to system-state changes. The endpoint fabric interfaces may be coupled to or integrated in IP blocks that are coupled to a switch fabric, or may be implemented in the switch fabric itself. The run-time fabric reconfiguration techniques may be implemented to for various purposes and/or to address various events, such as node failures, security events, IP or design bugs, feature prototyping, and virtualization.

Abstract: A microcontroller includes I/O pins whose respective functions are configurable by an I/O controller in accordance with user-programmable input. The availability of such configurable I/O pins is extended to low-power or power savings modes of operation during which the I/O controller is powered off or deactivated.

Abstract: In an image processing system, when a user request is received from a client apparatus, an image processing management apparatus determines whether the user request can be processed by the image processing system to generate a determination result, and generate an instruction indicating how the image processing system should operate based on the determination result.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: In a method to operate a magnetic resonance tomography apparatus that includes a number of electronically controlled sub-components, the components and/or the apparatus are controlled by a control unit via sensors and actuators. All relevant configuration data and operating data are stored in respective electronic objects that are stored in an apparatus memory. An electronic object is respectively associated with each component.

Abstract: There is provided a broadcast router that includes a plurality of input cards, a plurality of output cards, at least one programmable device, and a configuration control card. The plurality of input cards input data into the broadcast router. The plurality of output cards output the data from the broadcast router. The configuration control card stores configuration information for configuring the at least one programmable device to perform a first set of functions. The configuration control card is adapted for removal and replacement by at least one other configuration control card that stores other configuration information for configuring the at least one programmable device to perform a second set of functions having a difference from the first set of functions so as to change a functionality of the broadcast router.

Abstract: A peripheral component interconnect express (PCI-E) system has a reconfigurable link architecture. The system comprises a system slot adapted to receive a PCI-E compatible system controller, a plurality of peripheral slots adapted to receive a plurality of peripheral modules, and a reconfigurable switch fabric configured to create a variable number of PCI-E links between the system slot and the plurality of peripheral slots.

Abstract: A striping system and method for distributing a payload of data across a plurality of parallel USB cables from a source to a destination is described. The striping devices reside in the architecture of a source and destination connected by more than one standardized USB bus cable. The striping devices increase the bandwidth between the source and the destination by providing more lanes of data traffic and utilizing segmentation and reassembly to ensure that the data is split up and then reassembled correctly into the original stream at the destination. The striping devices allow for user determination of usability along with self diagnostics as to the source's and destination's ability to handle striping. Other embodiments are described.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: A system for executing applications designed to run on a single SMP computer on an easily scalable network of computers, while providing each application with computing resources, including processing power, memory and others that exceed the resources available on any single computer. A server agent program, a grid switch apparatus and a grid controller apparatus are included. Methods for creating processes and resources, and for accessing resources transparently across multiple servers are also provided.

Abstract: Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device.

Abstract: Configuring expansion component interconnect (‘ECI’) physical functions on an ECI device in a computing system, including: configuring by an ECI device configuration manager, during run-time of the computing system, vital product data to include an ECI physical function configuration, wherein the ECI physical function configuration comprises data describing a type of ECI physical function; retrieving by an ECI device configuration manager, upon a subsequent startup of the computing system, the ECI physical function configuration from the vital product data; and configuring, by an ECI device configuration manager, a physical function of the ECI device to carry out the type of ECI physical function described in the ECI physical function configuration.

Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.

Abstract: Error handling is simplified for a self-virtualizing IO resource that utilizes a physical function adjunct partition for a physical function in the self-virtualizing IO resource to coordinate error recovery for the self-virtualizing IO resource, by restarting each virtual function adjunct partition associated with that physical function to avoid the need to coordinate error recovery within the logical partitions to which such virtual function adjunct partitions are assigned.

Abstract: A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

Abstract: Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system.

Abstract: Each device in an industrial automation system network or other network may have its own associated one or more performance characteristics, such as response time and/or reset time of the network device. Data may be stored representing a plurality of performance characteristics each associated with a different one of a plurality of devices in the network including a first device and a second device. The stored data may be retrieved, representing the performance characteristic of the second device. The first device may communicate over the network with the second device in accordance with the performance characteristic of the second device.

Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

Abstract: A television includes at least two ports (e.g. HDMI ports). The television polls the ports before presenting a user interface that displays some or all of the ports and before toggling between any two of the ports. The polling ascertains whether a device is connected to each of the ports and whether the device is powered. The television modifies the display and/or toggling based on the current state of each port. For example, in toggling, ports that are not connected and ports that are connected to inactive devices are skipped. In another example, when displaying a list of ports, only those ports that are connected to devices appear in the list.

Abstract: A reconfigurable sensor front-end includes a logic block having a storage circuit to store hardware description information and a reconfigurable block including a plurality of circuits. The plurality of circuits are to be set in a first configuration based on the hardware description information and are to be set in a second configuration when the hardware description information changes. The first hardware description information corresponds to a first sensor and the changed hardware description information corresponding to a second sensor.

Abstract: An interface for an industrial controller is provided that enables connection of different types of plug-in I/O modules to the industrial controller. The interface includes several mechanisms, which can be implemented through control logic, circuitry, and/or software, that enable the control/monitoring device to operate in conjunction with different types of plug-in I/O modules. According to certain embodiments, the interface includes setup mechanisms that enable initial communications between the plug-in I/O modules and the control/monitoring device. The interface also may include operational mechanisms that facilitate communication between the plug-in I/O modules and the control/monitoring device during operation. The interface further may include registers that store data for the plug-in I/O modules.

Abstract: A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.

Abstract: An interfacing device is configured to process one or more rules, based on sensor data, to perform a predetermined action. During operation, the device can receive a device configuration that includes a rule for the interfacing device. The rule can include an action description for performing an action, and can include a condition that takes sensor data as input and indicates criteria for performing the action. The device can store the rule in a rule repository, and determines a remote interfacing device that generates data associated with the rule's condition. The device can also subscribe to the data from the remote interfacing device.

Abstract: The subject matter disclosed herein relates to alter an expression of executable instructions via a compiler component for use in ranking of electronic documents.

Abstract: A method of setting an address of a component that includes determining a characterization value associated with a consumable, calculating a number of address change operations based upon the characterization value, and setting a last address generated from the number of address change operations as the new address of the component, wherein the characterization value is determined based upon a usage of the consumable.

Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

Abstract: A wireless connection system capable of reducing a load on a user when constructing wireless connection environment including a host and devices. A wireless connection system comprises a host computer, a first device that has established a wireless connection with the host computer based on first association information, and a second device that has not established the wireless connection with the host computer. The host computer generates second association information for the wireless connection with the second device, and transmits the second association information to the first device by radio. The first device stores the second association information into a removable memory device when equipped with the removable memory device.

Abstract: A method of generating interaction activity information including connecting a second apparatus to a first apparatus capable of communicating with each other, receiving first information about a function that is capable of being performed in the first apparatus, from the first apparatus, and generating second information about a function that is used interactively between the first apparatus and the second apparatus, based on the first information.

Abstract: A method and controller for implementing device physical location identification in a Serial Attached SCSI (SAS) fabric using resource path groups, and a design structure on which the subject controller circuit resides are provided. The device physical location identification includes a Resource Path Group (RPG). Each RPG provides a unique persistent physical locator of a storage device in the system. Each RPG including at least two Resource Paths (RPs) and each RP has a fixed size identifying a type and a series of egress ports. A persistent RPG is stored within the device metadata on the storage device.

Abstract: A computer server system comprises multiple computer server units, each computer server comprising a server processing system. Each computer server comprises a local subsystem access module which is standardized for the multiple computer servers and which provides virtual control function for a single instantiation of a hardware resource of the computer server system, wherein the hardware resource is shared between each of the computer servers.

Abstract: A tunnel for a communication system includes first and second bridges. The first bridge has a first port adapted to couple to a first link and a second port, and has a first programmable bus number and a first programmable function number. The second bridge has a first port coupled to the second port of the first bridge, and a second port, and has a second programmable bus number and a second programmable function number. In a hoist enabled mode, the first bridge forwards a packet on the first link to the second bridge if the second programmable bus number is equal to the first programmable bus number, a bus number of the packet is equal to the first programmable bus number, and a function number of the packet is equal to the second programmable function number.

Abstract: This invention concerns a computer communication method using asynchronous messages in a distributed software architecture, for example of type AAA-MOM (Agent Anytime Anywhere - Messages Oriented Middleware), including a disconnectable platform such as a smartcard. This communication is carried out between firstly a card agent (CA), stored in a removable platform (31, 32), connectable to a terminal (21, 22), and secondly at least one standard software agent (AS). This standard agent can be stored in this computer network (1), in another renmovable platform. A message sent by the card agent (CA) to a standard agent (AS) or sent by a standard agent AS) to the card agent (CA), is stored in the network by at least one intermediate agent (CEPA,CAPA) managing the communications of this card agent (CA) with network (1).

Abstract: A semiconductor device capable of implementing system configurations corresponding to various PCIe topologies is provided. A RAM stores one or more configuration registers that define function information of a PCIe device. A Link control unit decodes a request received from a PCIe host and outputs a decoded result to a CPU. The CPU reads a corresponding configuration register from the RAM based on the decoded result received from the Link control unit, and generates a response to the request and causes the Link control unit to transmit the response. Thus, system configurations corresponding to various PCIe topologies can be implemented.

Abstract: For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.

Abstract: A connector assembly includes first and second connectors, a flexible printed circuit board, first and second peripheral component interconnection express (PCIe) slots, and a jumper card. When the jumper card is plugged into the first PCIe slot, pins of the jumper card are connected to pins of the first PCIe slot for transmitting signals to the pins of the first PCIe slot and to the pins of the first connector in that order. When the first connector is connected to the second connector, signals at the pins of the first PCIe slot are transmitted to pins of the second PCIe slot.

Abstract: A video/sound signal switching and distributing device makes connections to a plurality of video/sound signal receiving devices to be connected at startup of a system and performs authentication between itself and the plurality of video/sound signal receiving devices, thereby acquiring key selection information about a video/sound signal transmitting device and holding the key selection information. Even when another video/sound signal receiving device is connected to the video/sound signal transmitting device while one video/sound signal is already in the middle of displaying a view of the video/sound signal, the video/sound signal transmitting device and the video/sound signal switching and distributing device can again establish a connection without redoing mutual authentication. Hence, disconnection and re-connection of the video/sound signal can be performed without interruption of the video/sound signal being displayed for viewing purpose.