Abstract: An electronic device including a multi-protocol serial nonvolatile memory interface is disclosed. The interface includes: a first line operative to perform functions of a first chip select line when the interface operates as a SPI of the electronic device; a second line operative to perform functions of a second chip select line when the interface operates as the SPI of the electronic device; a third line operative to perform functions of a clock line when the interface operates as either the SPI or an I2C interface of the electronic device, and a fourth line configured to perform functions of a mast-out-slave-in (MOSI) line and a master-in-slave-out (MISO) line when the interface operates as the SPI of the electronic device, the fourth line further operative to perform functions of a serial data line when the interface operates as the I2C interface of the electronic device.

Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.

Abstract: A wireless universal serial bus (USB) system that includes a wireless USB host, a first wireless USB device, and a second wireless USB device. The wireless USB host is configured to wirelessly transmit a beacon over a wireless USB network based on a wireless USB protocol. The first and second wireless USB devices are configured to exchange wireless packets with the wireless USB host. The beacon designates the wireless USB network address access times for the first and second wireless USB devices.

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies.

Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Abstract: A universal serial bus (USB) signal test device includes a printed circuit board. A first connector, a second connector, and a number of USB hub integrated circuit (ICs) are arranged on the printed circuit board. The USB hub ICs are connected in series. A USB signal is passed through the USB hub ICs and an auxiliary test device in that order. The USB signals are measured with an oscilloscope after being passed through the USB hub ICs and the auxiliary test device.

Abstract: A system and method for managing logins and/or conducting data storage transactions, for example in a network interface. One exemplary embodiment comprises a method for interfacing a mass storage target system with a plurality of initiators. The method includes creating a data structure in local memory of a network interface chip to, at least in part, manage one or more logins; storing information comprising service parameter information m the data structure; and receiving a login request for a login comprising service parameter information. The method further includes comparing the service parameter information of the login request to the service parameter information stored in the data structure; determining, based at least in part on said comparing, to utilize the data structure to manage the login; and managing the login with the network interface chip using at least the data structure.

Abstract: A bus detection and control method for a mobile industry processor interface system is disclosed, wherein a host is coupled to a slave with a mobile industry processor interface bus. The bus detection and control method includes steps of detecting statuses of the mobile industry processor interface bus and the host, to output a control signal; and outputting one of a predefined signal corresponding to an initial state and a transmission signal outputted to the mobile industry processor interface bus by the host as a reception signal of the slave according to the control signal.

Abstract: There is disclosed a method, system and computer readable medium for transferring data in a LAN-free environment, in particular for a tape backup or restore operation. Data of a client partition of a first server is sent to a partition of a LAN-free server through the Local Area Network (LAN). The data sent is then converted from TCP/IP protocol to Fiber Channel protocol. The converted data is sent to a Storage Area Network (SAN) through a Fiber Channel card and finally to a tape library. An advantage is thus to mutualize and virtualize resources, in particular Fiber Channel cards. Storage Area Network tape drives are shared using such host bus adapter cards. Certain embodiments avoid the reconfiguration of Storage Area Network tape drives when the client partition moves to a new hardware.

Abstract: Methods and apparatus for enhancing control-plane security of a network-accessible service are described. In accordance with a security policy, one or more control servers are selected to perform administrative operations associated with configuration of a service instance at a particular instance host of a network-accessible service. The control servers may differ in security properties from the instance host. In response to a configuration request directed at the instance host, administrative operations are implemented at the selected control servers. A low-level command is issued for execution to the instance host from a control server. A result of the low-level command is obtained at the control server and is used to determine a response to the configuration request.

Abstract: A mobile terminal and a method are provided for power saving. The mobile terminal monitors changes of data on a UART bus, acquires current operating states of a Bluetooth chip and a main control chip on the mobile terminal, and when detecting that there is no data on the UART bus, the main control chip controls a Bluetooth module to enter into a power saving mode. By adopting the technical scheme described, once it is detected that there is no data on the bus, the Bluetooth module will be enabled to enter into a state of power saving mode immediately, which ensures that the Bluetooth module is always in the state of power saving mode when there is no service ongoing, thereby increasing the standby time of the mobile terminal to the maximum extent, and improving the level of the user experience.

Abstract: A method, system, and computer program product for a diagnostic heartbeat throttling are provided in the illustrative embodiments. A component, executing using a processor and a memory in a data processing system, sends diagnostic heartbeat packets over a communication link at a first rate, wherein a diagnostic heartbeat packet is a packet comprises a header, a set of heartbeat parameters, and a set of diagnostic attributes. The component detects a change in data traffic over the communication link. The component changes a rate of sending diagnostic heartbeat packets from the first rate to a second rate responsive to the change in the data traffic over the communication link.

Abstract: In aspects of serial interface for FPGA prototyping, an advanced crossbar interconnect (AXI) bridge structure enables serial data communication between field programmable gate arrays (FPGA) in a system-on-chip (SoC). The AXI bridge structure includes a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA. A transmit (TX) engine is configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link. The AXI bridge structure also includes a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract AXI data signals from the additional AXI data packet. The parallel interface is further configured to provide the additional AXI data signals to the AXI component.

Abstract: An apparatus and a method of controlling clock signals for a master device and a slave device are disclosed. The controlling apparatus includes: a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; and a control module receiving a first clock signal from the master device via the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device via the second connection port; wherein when the first clock signal is switched from a first logic level to a second logic level, the control module controls the first connection port to maintain the second logic level in a time interval.

Abstract: A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.

Abstract: In order to configure network nodes as part of the planning and setting-up of an in particular real-time-based and isochronous data transmission between the network nodes, a method and apparatus are proposed, wherein a node is connected via the network to the apparatus which is programmed in such a way that, in response to at least one item of configuration-related information specified by an operator, it generates a set of configuration data which are necessary for configuring at least the one node and transmits at least a subset of this generated set of configuration data to the node via the network.

Abstract: Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.

Abstract: An operation mode switching method for a memory storage apparatus, a memory controller and a memory storage apparatus using the method are provided. The operation mode switching method includes receiving at least one access command from a host system and determining whether the access command conforms to a predetermined pattern. If the access command conforms to the predetermined pattern, an operation mode of the memory storage apparatus is switched from a first mode to a second mode. The access command includes a first write command including a write string, and the memory storage apparatus executes an operation corresponding to the write string. Accordingly, the method switches the operation mode of the storage memory apparatus by determining the pattern of the access command, so as to simplify the procedure of switching the operation mode and effectively decrease the probability of switching the operation mode incorrectly.

Abstract: A protocol adapter for in-vehicle networks that provides diagnostics, analysis and monitoring. The protocol adapter has a pass-through feature (voltage translator)/smart mode that allows the protocol adapter to emulate older boxes. Visual indicators (LEDs) indicate the pass through feature is in operation. LEDs also indicate activity on the RS232 bus between the adapter and a PC. Single color and multiple color emitting LEDs indicate a program is being executed and identify the program that is being executed. The protocol adapter supports RP1202 and RP1210, J1708 and J1939 and J1939 Transport Layer. The protocol adapter has a Real Time Clock, Standard COMM port connection, 7-32 Volt Supply and is CE compliant. The adapter can be used wirelessly.

Abstract: A gateway device is provided. The gateway device for relaying communication between an automotive network communication device and an industrial field bus communication device includes: a Controller Area Network (CAN) input unit for receiving a CAN input data frame from an external; and a conversion unit for converting the received CAN input data frame into a Modbus output data frame according to a predetermined method.

Abstract: A method of resource-synchronizing data that is transmitted on a communication link having at least one data lane, between a first device and a second device, wherein the second device has a resource that is accessible based on an access schedule. In one operation, a timing offset of the second device based on the access schedule is determined, followed by delaying the transmission of data from the first device to the second device through the communication link by an amount of time equal to the timing offset so that the data is received at the resource when the resource is accessible according to the access schedule.

Abstract: Embodiments of the invention are generally directed to transmission of multiple protocol data elements via an interface utilizing a data tunnel over a control channel. An embodiment of an apparatus includes a transmitter or receiver for the transmission or reception of data; a processing element for handling the data of the apparatus; and a connector for the transfer of the data, the connector to connect to a data channel and to connect to a control channel. The processing element is to provide for transfer of data of a first protocol in the control channel, the transfer of data via the control channel including the use of one or more generic commands of the first protocol for the transfer of data of a second protocol. Data of the second protocol is optimized before the data of the second protocol is sent over the first protocol, and the data transfer in the data channel and data transfer in the control channel are simultaneous at least in part.

Abstract: Systems and methods for buffering or delaying data packets to facilitate optimized distribution of content associated with the data packets are disclosed. Data packets sent from content providers may be received by a service provider, where information associated with the data packets may be identified. The identified information may be used to associate the data packets with an intended destination for the data packets and identify a type of the data packets, such as a video data packet. Video data packets (and other data packets) may be buffered or delayed such that more time-critical data packets may be accelerated into one or more QAM channels carrying the content. The delayed data packets may be time-sliced into the one or more QAM channels, which may displace empty slots or gaps that may waste bandwidth associated with the QAM channels.

Abstract: A port multiplier dynamically determines and reports its identity based on a number of supported downstream port connections. The number of supported downstream port connections can dynamically change. The port multiplier identifies devices connected to its downstream ports, whether storage devices or other port multipliers. Based on a total number of downstream ports, the port multiplier reports its identity upstream. The upstream reporting can be to another port multiplier, or the host device if directly connected to the host device. The port multiplier receives storage address space allocation from upstream based on its reported identity, and allocates the storage address space to its downstream ports.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: A data transport system for transporting data and auxiliary signals over an optical link comprises a transmitter, a receiver and an optical link. The transmitter and receiver are coupled to a first end of the optical link. The optical link includes a number of optical channels. A controller is coupled to the transmitter and the receiver, and controls the transmitter and the receiver to operate in a first state when data are detected at an input of the transmitter. Data are transported via the data transport system in the first state. The controller controls the transmitter and the receiver to operate in a second state when the data are detected as absent at the input of the transmitter. Data are prevented from being transported via the data transport system in the second state.

Abstract: Provided is a communication system that can aim to prevent unauthorized communications, i.e., to improve the reliability of communicated messages. A communication system comprises a plurality of ECUs connected to a communication line such that the plurality of ECUs can communicate communication messages. Each of the plurality of ECUs has a unique ID and also has a plurality of dummy IDs defined, as substitute candidates, from the unique ID. The ECU further has a defined pattern in which to cause one of the plurality of dummy IDs to be selected as a dummy ID that is a substitution object to be converted to the unique ID. Among the plurality of ECUs, the selection conditions of the substitution objects based on the pattern are synchronized, and the unique ID, which has been added to a communication message, is converted to a dummy ID on the basis of the pattern.

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

Abstract: A method of encoding a digital bus message information, in particular a wake-up bus message information or configuring data, on a bus system, the method comprising: encoding a predetermined part of digital bus message information bits by means of sub-patterns in a stream of line symbols on at least one bus line, wherein sub-patterns consist of successive dominant and recessive phases, comprised of recessive and dominant line symbols, wherein a recessive phase is comprised of at least two recessive line symbols in order to establish a ratio of successive dominant and recessive phases that corresponds to a value of the predetermined part. A respective digital bus message, particularly for use on a bus system, is to be encoded in accordance with the method.

Abstract: Disclosed herein axe reconfigurable ports and methods for doing the same.

Abstract: A method for identifying an application usable with an accessory is provided. The method includes receiving an accessory identifier associated with the accessory, identifying an application protocol associated with the accessory identifier, identifying an application that supports the application protocol, and providing information about the application to a user device. A method for identifying an accessory usable with an application is also provided. The method includes receiving information about an application, determining an application protocol associated with the application, determining an accessory that supports the application protocol, and providing information about the accessory to a user device.

Abstract: Methods and apparatus for enabling Fast Context Switching (FCS) operation of an enhanced Serial Attached SCSI (SAS) expander and initiator for switching between one or more concurrently established connections including at least one Serial Advanced Technology Attachment (SATA) target device connection. Features and aspects hereof provide for enhanced logic within a SAS expander and/or initiator to detect the completion of an exchange over a first connection between an initiator device and a SATA target device and to allow switching to another (a second) connection without closing the first connection.

Abstract: A device and method for providing performance information about a processing device. A stream of performance data is generated by one or more devices whose performance is reflected in the performance data. This performance data stream is then provided to a parallel port for outputting thereof.

Abstract: Safe bus devices use a safety protocol in order to transmit safe data encapsulated in an industrial Ethernet message via an Ethernet-based field bus. However, this restricts the safe bus device to a certain combination of safety protocol and industrial Ethernet protocol. In order to be able to use a safe bus device 12, 14, 151 more flexibly, it is provided that, to transmit the safety-oriented data, the industrial Ethernet protocol uses the session layer 5 and/or presentation layer 6 of the safety protocol, which is independent of the industrial Ethernet protocol, instead of the session layer 5 and/or presentation layer 6 which is implemented in the industrial Ethernet protocol, whereby such a bus device 12, 14, 151 becomes independent of the industrial Ethernet protocol.

Abstract: A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one.

Abstract: A method for setting addresses of slave devices in a communication network is provided. In the communication network, a master device identifies address-collided slave devices and requests the address-collided slave devices to return their unique identification data. The master device sets addresses of the address-collided slave devices so that each of the slave devices in the communication network has a different address from one another.

Abstract: Methods and apparatus, including computer program products, are provided for communications control in a dual row connector. In one aspect there is provided a method. The method may include coupling a first data connector including a pair of communication control pins and another pair of communication control pins, wherein the pair further comprises a first communication control pin located at a first row of the first data connector and a second communication control pin located at a second row of the data connector, wherein the other pair further comprises a third communication control pin located at the first row of the first data connector and a fourth communication control pin located at the second row of the first data connector. Related apparatus, systems, methods, and articles are also described.

Abstract: A serial interface comprises a clock line, a request line, a ready line, a master-to-slave data line, and a slave-to-master data line. A master device transmits a clock signal to a slave device over the clock line. In a first transaction, the master device sends a master transmission request signal to the slave device over the request line; in response, the slave device sends a slave transmission accept signal over the ready line, which causes the master device to transmit binary data to the slave device over the master-to-slave data line. In a second transaction, the slave device sends a slave transmission request signal over the ready line; in response, the master device sends a master transmission accept signal over the request line, which causes the slave device to transmit binary data to the master device over the slave-to-master data line. In at least one of the transactions, the master and slave devices transmit binary data at the same time as each other.

Abstract: A PCIe Fabric that includes an IO tier switch, hub tier switches, and a target device connected to one of the hub tier switches. The IO tier switch is configured to receive a TLP from a client, make a determination that an address in the TLP is not associated with any multicast address range in the first IO tier switch and is not associated with any downstream port in the first IO tier switch, and, based on the determinations, route the TLP to the first hub tier switch via a upstream port on the IO tier switch. The hub tier switch is configured to make a determination that the TLP is associated with a multicast group, and, based on the determination, generate a rewritten TLP and route the rewritten TLP to a target device via a downstream port on the hub tier switch.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a CAN device is disclosed. The CAN device includes a TXD input interface, a TXD output interface, an RXD input interface, an RXD output interface, and a traffic control system connected between the TXD input and output interfaces and between the RXD input and output interfaces. The traffic control system is configured to detect the presence of CAN Flexible Data-rate (FD) traffic on the RXD input interface and if the traffic control system detects the presence of CAN FD traffic on the RXD input interface, disconnect the RXD input interface from the RXD output interface and disconnect the TXD input interface from the TXD output interface.

Abstract: A system can include a host device and a remote terminal. The host device can include a host terminal, the host terminal including a host configuration manager to allocate a data lane to an I/O protocol and a protocol multiplexer to carry out allocation of the data lane based on the allocation of the configuration manager. The remote terminal can include a remote configuration manager. The remote configuration manager is to communicate with the remote configuration manager via a control bus to detect connection of an I/O device to an I/O port and to allocate the data lane to the I/O protocol.

Abstract: A military standard-1760 (MIL-STD-1760) interface bridge can include a housing, a translator device, and an energy storage device. The housing can include a MIL-STD-1760 connector on a first end and a weapon side connector on a second end. The translator device can translate a MIL-STD-1553B remote terminal (RT) protocol to a weapon side signaling protocol and translate the weapon side signaling protocol to the MIL-STD-1553B RT protocol. The energy storage device can be coupled to the operating power of the MIL-STD-1760 connector and can be configured to provide power to the translator device for a duration after the power from the MIL-STD-1760 connector is disconnected.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.

Abstract: A communication interface hub includes multiple ports, where one of the ports is an upstream port operative to be in direct and/or indirect communication with a host and at least one other of the ports is a downstream port operative to be in direct and/or indirect communication with at least one device. At least one hub core is coupled to the ports and implements at least one physical hub, and at least one virtual hub core is coupled to the ports and implements at least one virtual hub. The virtual hub is detectable as at least one physical hub by the host to cause the host to allocate an additional time delay in waiting for responses to signals output by the host.

Abstract: The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

Abstract: A start/stop condition detection circuit is coupled to receive the SDA and SCL signals from an IIC Bus. The circuit generates a first signal in response to an edge of the SDA signal and generates an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal. The first and second signals are logically combined to generate an output signal. The particular directions of the edges of the SDA and SCL signals that the circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection.

Abstract: In one embodiment, a computer system comprises one or more processors, a circuit board assembly having at least one SATA port, a general purpose input/output port proximate the SATA port, signal generating logic to generate a signal when the general purpose input/output port is coupled to a connector, and a memory module communicatively connected to the one or more processors and comprising logic instructions stored in a computer readable medium which, when executed on the one or more processors, configure the one or more processors to configure the SATA port according to the signal generated by the signal generating circuitry.

Abstract: A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: Methods and systems for processing transaction packets at a serial interface are disclosed. The method includes receiving transaction information at a serial interface. The method further includes executing one or more pipelined operations based on the transaction information, where the operations relate to processing of the transaction packet. The method is performed such that the serial interface is configured to send and receive transaction packets at a line speed of the serial bus.