Abstract: An application processor includes a central processing unit, a root complex that communicates with at least one external device under control of the central processing unit and generates a state change interrupt when an operation state changes, and an interrupt aggregation and debug unit that performs debugging on at least one component associated with the state change interrupt depending on the state change interrupt.

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Abstract: A SOM circuit board includes a main body having a first face surface, an opposing second face surface, a first side surface, an opposing second side surface, a first end surface, and an opposing second end surface. The first and second side surfaces have maximum lengths along a longitudinal direction which are greater than maximum lengths of the first and second end surfaces along a lateral direction. The SOM circuit board further includes a plurality of computing components, each of the plurality of computing components mounted on one of the first face surface or the second face surface. The SOM circuit board further includes an input/output connector mounted on the second face surface. The SOM circuit board further includes a plurality of mounting holes extending along the transverse direction through and between the first face surface and the second face surface.

Abstract: The present invention discloses an asynchronous serial communication system and method. The asynchronous serial communication system may include a semiconductor device having two terminals and configured to receive a voltage required for an operation from data transmitted through one terminal; and a controller configured to perform asynchronous serial communication with the semiconductor device with two terminals. The asynchronous serial communication system may perform asynchronous serial communication between the semiconductor device and the controller in order to write or read data through the one terminal.

Abstract: In one embodiment, a method includes detecting a slave device at a master device, determining at the master device if the slave device is configured for I2C (Inter-Integrated Circuit) or SPE (Single Pair Ethernet) based on an output at the slave device, and selecting an I2C mode of operation at the master device if the slave device is configured for I2C, or selecting an SPE mode of operation at the master device if the slave device is configured for SPE. Data and control are selected from an I2C controller at the master device in the I2C mode of operation and selected from a physical coding sublayer at the master device in the SPE mode of operation.

Abstract: Technologies for facilitating communication between a master programmable logic controller and one or more target drives are disclosed. In an illustrative embodiment, a remote device emulation appliance is configured to receive a communication from a master programmable logic controller that is formatted according to a remote input/output protocol unusable by the target drive. The remote device emulation appliance converts the communication from the remote input/output protocol to a drive protocol usable by the target drive to control operations of the drive and transmits the converted communication to the target drive. The remote device emulation appliance may also convert communications received from the target drive from the drive protocol usable by the target drive to the remote input/output protocol and transmit such converted communications to the master programmable logic controller.

Abstract: A method for transmitting messages in a data bus system, wherein the messages can be transmitted in the form of data frames by a data bus and a data frame that is to be sent by a bus subscriber is checked for a piece of changeover information, which method is furthermore distinguished in that changeover of the rise time and/or edge shape of edges of bit pulses of the data frame that is to be sent is performed on the basis of the presence of a defined value of the piece of changeover information. In addition, a corresponding transceiver and to an electronic control unit is disclosed.

Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.

Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.

Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node, a second computer node and a control unit. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; (B) transmitting, by the first BMC and to the control unit, a control signal that corresponds to the reset command; and (C) transmitting, by the control unit and to the second BMC, a reset signal that corresponds to the control signal, so as to trigger reset of the second BMC.

Abstract: Methods, systems, and computer programs are presented for routing packets on a network on chip (NOC) within a programmable integrated circuit. One programmable integrated circuit comprises a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, an internal network on chip (iNOC) comprising iNOC rows and iNOC columns, an external network on chip (eNOC) connected to the iNOC rows and the iNOC columns, and a field programmable gate array Control Unit (FCU) for configuring programmable logic in the plurality of clusters based on a first configuration received by the FCU. The FCU is connected to the eNOC, where the FCU communicates with the plurality of clusters via the iNOC and the eNOC. The FCU is configured for receiving a second configuration from the programmable logic in the plurality of clusters for reconfiguring a component of the programmable integrated circuit.

Abstract: A network-displaced direct storage architecture transports storage commands over a network interface. In one implementation, the architecture maps, at hosts, block storage commands to remote direct memory access operations (e.g., over converged Ethernet). The mapped operations are communicated across the network to a network storage appliance. At the network storage appliance, network termination receives the mapped commands, extracts the operation and data, and passes the operation and data to a storage device that implements the operation on a memory.

Abstract: This disclosure relates generally to bus interface systems for mobile user devices. In one embodiment, the bus interface system includes a first bus interface subsystem that operates in accordance with a one wire bus protocol, a second bus interface subsystem that operates in accordance with a Mobile Industry Processor Interface (MIPI) radio frequency front end (RFFE) bus protocol, and a translation bus controller that translates commands between the first bus interface subsystem and the second bus interface system. The translation bus controller is configured to implement cross over bus operations between a master bus controller that operates in accordance with in the one wire bus protocol and a slave bus controller in the second bus interface system. In this manner, the translation bus allows the master bus controller to be the master of different bus systems that operate in accordance with different bus protocols.

Abstract: Embodiments of the present disclosure disclose communication methods and systems, electronic devices, and computer clusters. The method includes: separately creating a corresponding thread for at least one of a plurality of target devices, where the created thread corresponding to the target device includes a communication thread and a message processing thread, and the message processing thread includes a message sending thread and/or a message receiving thread; and communicating with a corresponding target device on the basis of the corresponding created thread.

Abstract: An intrinsically-safe handheld field maintenance tool includes a controller, a process communication module, and a display. The process communication module is configured to communicate with a field device using a process communication protocol. The display is coupled to the controller. A user interface module is also coupled to the controller and is configured to receive user input. The controller is configured to detect a user input help request and provide a video output on the display in response to the user input help request.

Abstract: Process control systems for operating process plants are disclosed herein. The process control systems include control modules that are decoupled from the I/O architecture of the process plants using signal objects or generic shadow blocks. This decoupling is effected by using the signal objects or generic shadow blocks to manage at least part of the communication between the control modules and the field devices. Signal objects may convert between protocols used by control modules and field devices, thus decoupling the control modules from the I/O architecture. Generic shadow blocks may be automatically configured to mimic the operation of field devices within a controller executing the control modules, thus partially decoupling the control modules from the I/O architecture by using the shadow blocks to manage communication between the control modules and the field devices.

Abstract: Described herein are systems, methods, and software to enhance virtualization connection management for virtual remote direct memory access (RDMA) devices. In one implementation, virtual machines may register with a hypervisor for the virtual machines, wherein the registration for each virtual machine includes at least one address for the virtual machine. Once registered, the hypervisor may identify a packet placed in a queue pair from a physical RDMA interface and determine whether a destination address in the packet corresponds to a virtual machine. If the destination address corresponds to a virtual machine, then the hypervisor may provide a callback to the virtual machine, wherein the callback provides access to the packet in the virtual machine as if the packet received at a virtual RDMA interface of the virtual machine.

Abstract: Disclosed herein are systems and techniques for digital interfaces over a two-wire communication bus. For example, an electronic device to interface between a two-wire communication bus and a non-native digital interface may include: a digital interface to support a first digital interface protocol; and a transceiver, coupled to the digital interface, to couple to a link of the two-wire communication bus and to receive data via the link, wherein the data includes commands in accordance with a second digital interface protocol different from the first digital interface protocol; wherein the digital interface is to transmit the commands to a peripheral device in accordance with the second digital interface protocol.

Abstract: A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.

Abstract: According to some possible implementations, a monitoring device may receive a set of inputs from one or more drivers of a device connected to a bus. The one or more drivers may be capable of driving a bus line of the bus, and the bus may connect multiple devices capable of driving the bus line. The monitoring device may determine a length of time over which the set of inputs maintains a value indicating that the bus is not idle. The monitoring device may compare the length of time and a threshold. The monitoring device may output a signal based on comparing the length of time and the threshold.

Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.

Abstract: A sensor control arrangement may comprise a host controller, a remote sensor interface, a power/data bus extending between the host controller and the remote sensor interface, and an electromagnetic sensor configured to receive an AC signal from the host controller via the power/data bus, and send an a sensor signal to the remote sensor interface via the power/data bus.

Abstract: A system is provided relating to a peripheral component interconnect express bus bar. In use, the bus bar includes a circuit board and at least two electrical interface surface mount connectors attached to the circuit board, each of the at least two electrical interface surface mount connectors configured to be connected to a respective add-in card. Further, at least one power connector is attached to the circuit board and connected to at least one electrical interface surface mount connector of the at least two electrical interface surface mount connectors, and is configured to receive power and distribute the power to the at least two electrical interface surface connectors.

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include configuring multiple servers coupled to a network as a software defined storage (SDS) grid. A first given server receives, via the network, an input/output (I/O) request from a host computer, and determines a location of data associated with the I/O request. In some embodiments, each of the servers maintains a local grid data map that store locations for all data managed by the SDS grid. Upon identifying, in its respective local grid data map, that a second given server is configured to process the I/O request, the first given server forwards the I/O request to the second given server for processing, and upon receiving a result of the I/O request from the second given server, the first given server conveys the result of the I/O request to the host computer.

Abstract: Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy according to protection schemes can occur directly at an IP interface or within an interconnect, such as within a packet-based NoC. Designs include SoCs, hardware description language code describing functions within SoCs, and non-transient computer readable media that store such source code.

Abstract: A method, a computer system, and a computer program product to perform a directory lookup in a first level cache for requested cache line data. A first processor core can detect that the requested cache line data is not found in a plurality of sets of data in the first level cache and detect that existing cache line data stored in a least recently used data set stored in the first level cache is in an exclusive state, wherein the existing cache line data stored in the least recently used data set is to be overwritten by the requested cache line data retrieved from a second level cache. Furthermore, the first processor core can send a request for the requested cache line data and a physical address of the least recently used data set to the second level cache and execute additional instructions based on the first level cache and data retrieved from the second level cache.

Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

Abstract: A semiconductor device includes a first intellectual property block (IP block) which includes a function unit and an interface unit; a first clock control circuit which controls a first clock source; a second clock control circuit which transmits a first clock request to the first clock control circuit, and controls a second clock source which receives a clock signal from the first clock source; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block; wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the function unit.

Abstract: In an example, an apparatus may include a memory comprising a number of groups of memory cells and a controller coupled to the memory and configured to track respective invalidation velocities of the number of groups of memory cells and to assign categories to the number of groups of memory cells based on the invalidation velocities.

Abstract: In general, embodiments of the technology relate to a method and system for performing fast ordered writes in a storage appliance that includes multiple separate storage modules. More specifically, embodiments of the technology enable multicasting of data to multiple storage modules in a storage appliance, where the order in which the write requests are processed is the same across all storage modules in the storage appliance.

Abstract: A peripheral device class identifier is generated for a class of peripheral devices, and is used to identify a setup record that indicates how to install or otherwise set up the class of peripheral devices on a computing device. The peripheral device class identifier is a combination of three components: a vendor identifier, a namespace identifier, and a namespace entry identifier. The vendor identifier is an identifier of the vendor of the class of peripheral devices. The namespace identifier is an identifier of different collections or groups of types of peripheral devices or types of functionality of peripheral devices. The namespace entry identifier is an identifier of a particular type of peripheral device (or particular functionality) of the different collections or groups of types of peripheral devices (or types of functionality of peripheral devices).

Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Abstract: Synchronization events associated with cache coherence are monitored without using invalidations. A callback-read is issued to a memory address associated with the synchronization event, which callback-read either reads the last value written in the memory address or blocks until a next write takes place in the memory address and reads a newly written value.

Abstract: Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

Abstract: This disclosure describes systems, methods, and apparatus for a combined LED driver and emergency backup battery system. The LED driver can include current regulation circuitry as well as a bus enabling charging and discharging of an energy storage device from and to the bus. A master controller can control charging and discharging of the energy storage device via a controller of an energy storage management system, and also communicate with the current regulation circuitry to control a balance of power between an AC mains, the energy storage device, and driving of an LED light source. Accessories may be coupled to the bus and receive low voltage power from the bus and optionally receive commands from the master controller and provide sensed data back to the controller. A wireless network interface to the master controller can enable system states based on electrical power company indications and instructions.

Abstract: Disclosed are techniques for downloading of filtering rules onto a mobile device. The described technique includes determining, from among at least two lists of filtering rules intended for downloading onto a mobile device, a priority sublist with a high indicator of frequency of actuation of the filtering rules from the list. The priority list is downloaded onto the mobile device. Each of the remaining non-downloaded lists of filtering rules is broken up into parts of a certain size, and a set of groups of filtering rules is formed, in each of whose groups is placed not more than one part of each remaining non-downloaded list of filtering rules. The groups of filtering rules are downloaded onto the mobile device with a certain interval of time until said formed set of groups is fully downloaded.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

Abstract: A communication apparatus includes a first communicator configured to receive signals of a plurality of standards containing a first network signal as a transmitted and received signal for a network, a second communicator configured to receive a second network signal as a transmitted and received signal for the network, a selector configured to select one of the first and second network signals, and a controller configured to control the first and second communicators and the selector. The first communicator includes a first confirmer configured to confirm a reception of the first network signal among the signals of the plurality of standards for the first communicator, and a first operation mode setter configured to set an operation mode to the first communicator.

Abstract: In one embodiment, a method includes identifying insertion of a plug at a port of power sourcing equipment for delivery of Power over Ethernet, the plug connected to one end of a cable with another plug connected to an opposite end of the cable, checking for resistors at each of the plugs, determining a power rating of the cable based on the resistors located at the plugs, and powering the port to a power level based on the power rating. An apparatus is also disclosed herein.

Abstract: A system and method includes generating, with a configuration controller, a configuration bitstream including configuration bits to dynamically define the configuration of a reconfigurable integrated circuit by setting a state of a subset of configuration state memory units. The configuration controller accesses individual configuration state memory units of the subset according to a scan path through the configuration state memory units traversed according to a delay factor based, at least in part, on clock frequency of a clock signal produced by a configuration clock and configures the individual configuration state memory units with corresponding configuration bits of the configuration bitstream.

Abstract: A data card enclosure method and system comprising data card connectors and host interface connectors on a data card housed in the data card enclosure. The data card enclosure method and system provided for connecting the data card connectors and host interface connectors to external communications ports. One or more of the data card connectors may be repurposed as one or more host interface connections or one or more of the host interface connectors may be repurposed as one or more data card connectors.

Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

Abstract: Embodiments of the present invention disclose an access request scheduling method and apparatus. The method includes: receiving a to-be-enqueued access request, and determining a memory that the to-be-enqueued access request requests to access; writing the to-be-enqueued access request to one queue in one access queue group corresponding to the memory; selecting one candidate access queue from each candidate access queue group, as a to-be-scheduled queue; selecting, from the to-be-scheduled queues according to an access timeslot of each memory, alternative queues that can participate in scheduling in a current clock period; selecting, from the alternative queues, a specified queue in scheduling in the current clock period; extracting a to-be-scheduled access request from the specified queue; and granting an access authorization to the to-be-scheduled access request.

Abstract: A method for implementing a configurable on-chip interconnection system. The method comprises: in an interconnection system, master devices set bit widths of bus identifiers of the master devices, wherein the bit widths of the bus identifiers of the master devices are the same (301); and in a memory access process, the mater devices interact, by means of interconnection matrices only, with slave devices according to the bus identifiers (302). Also provided are a system and apparatus for implementing the method, and a storage medium.

Abstract: An inter-integrated circuit bus arbitration system includes a first master circuit, a second master circuit, an analog switch circuit, an initial state identification circuit, and a selection control circuit. When the first master circuit is initiated to transmit data, the initial state identification circuit generates a first initial pulse signal. When the second master circuit is initiated to transmit data, the initial state identification circuit generates a second initial pulse signal. If the first initial pulse signal leads the second initial pulse signal, the selection control circuit generates a first control signal to make the analog switch circuit establish electrical connections between the first master circuit and an external data line and an external clock line when receiving the first control signal.

Abstract: A connecting device able to allocate master and slave roles between two intelligent devices having On-The-Go functions, depending on the intelligent device connects at a first point in time to one of two connectors, the connecting device also includes a control circuit connected between the two connectors. The control circuit between the connectors maintains and controls the master-slave relationship between the two intelligent devices.

Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. System on chip designs may employ a plurality of NOCs with different configuration parameters to customize the system to the application or workload characteristics.

Abstract: The techniques described herein automatically and programmatically harmonize data, and map variable names from a dataset to standards of domains for data in the dataset. Each variable may be stored in a table which holds related groups of variables. The variables may be named by defining mappings, each mapping including two mapping rules. A first mapping rule maps a domain of the standard to the table, while a second mapping rule maps a variable within the table to a variable within the domain. When a mapping rule exists that provides an exact match between a variable name and a standard, an auto-mapping feature may be applied that automatically maps the variable name to the standard. If no exact match exists, then an analysis is performed to determine the most likely mapping candidate.

Abstract: A bidirectional bus system that includes a bus master having a first transmitter coupled to a bidirectional bus. The first transmitter transmits a signal in a first voltage range onto the bus. The bus master has a first receiver coupled to the bus. A bus slave having a second transmitter coupled to the bus is included. The second transmitter transmits a signal in a second voltage range onto the bus, where the bus slave having a second receiver is coupled to the bus. The first receiver is configured to interpret the signal in the first voltage range to indicate an idle state while the second receiver interprets the signal in the first voltage range as indicating data. The second receiver interprets the signal in the second voltage range as indicative of an idle state while the first receiver interprets the signal in the second voltage range as indicating data.