Abstract: A method includes assigning a priority to each of a plurality of protocol activities to produce stack priority information for each of a plurality of protocol stacks. The method further includes dynamically adjusting the priority of each of the plurality of protocol activities in the stack priority information based on a network maintenance activity and based on a rejection or an acceptance of the corresponding protocol activity by a dynamic multi-protocol manager (DMM). The method further includes providing the stack priority information to the DMM.

Abstract: A first set of storage accesses of a storage system are identified. The first set of storage accesses are associated with a first user. A first plurality of storage access notifications is sent to a first message queue associated with the first user based on the first set of storage accesses. A first message queue timeout value of the first message queue is set based on at least one characteristic associated with the first set of storage accesses.

Abstract: In certain aspects, a memory system includes at least one memory device and a memory controller coupled to the at least one memory device. The memory controller may be configured to determine a current power consumption value indicating total concurrent power consumption of executing a plurality of memory operations in parallel. The memory controller may also be configured to determine an addon power consumption value indicating additional power consumption of executing a subsequent memory operation. The memory controller may be further configured to determine whether a summation of the current and the addon power consumption values exceeds a predetermined power consumption threshold. After determining that the summation of the current and the addon power consumption values does not exceed the predetermined power consumption threshold, the memory controller may be configured to execute the subsequent memory operation in parallel with the plurality of memory operations.

Abstract: Systems and methods for managing file operations over shared content in the presence of two or more heterogeneous file systems. A virtual file system provides data consistency pertaining to asynchronous interactions between the heterogeneous storage systems. Operations of the virtual file system include receiving a file system call from a first storage environment for performing one or more data operations at a second storage environment. After receiving the file system call, the virtual file system issues file system calls to the second storage environment and records a first set of metadata. To determine if and when the one or more data operations at the second storage environment have completed, the virtual file system accesses a second set of metadata from the second storage environment. The two sets of metadata are compared. If there are differences, then the virtual file system performs time delays until the two sets of metadata agree.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

Abstract: The examples include methods and apparatuses to store events in a queue for an EC, Storing events in a queue for an EC can include receiving a message from a core FW of an EC and identifying an event corresponding to the message. Storing events in a queue for an EC can also include accessing a priority associated with the event and adding the event and the priority to a queue to be processed by the EC.

Abstract: An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value.

Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order.

Abstract: A motherboard includes a connector, a multiplexer and a controller. The connector is configured to selectively couple a Redundant Array of Independent Disks (RAID) card. The connector is configured to generate a switching parameter. The multiplexer is coupled to the connector. The multiplexer is configured to detect the switching parameter. The controller is coupled to the multiplexer. The multiplexer either receives a software RAID establishment signal from the controller or it receives a hardware RAID establishment signal from the RAID card, according to the switching parameter.

Abstract: Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

Abstract: Disclosed herein are systems and method for managing blocks of data and metadata. In one aspect, an exemplary method comprises, receiving, by a virtual block device (VBD), a request from a file system, wherein the request includes one or more of: a type of operation requested by the file system, including one of a read operation or a write operation, and/or an indication as to whether the request is for a block of data or a metadata of the file system, when the request includes the indication as to whether the received request is for a block of data or a metadata, selecting, based on the indication, one of two or more separate storage locations associated with the requested block of data or a metadata respectively, and accessing the determined storage location to perform the requested operation on the block of data or the metadata in the storage location.

Abstract: Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.

Abstract: A semiconductor device includes a control circuit and an address generation circuit. The control circuit generates a write column address signal, a write bank selection signal and an internal write bank selection signal from a command/address signal during a write operation. The control circuit also generates a read column address signal, a read bank selection signal and an internal read bank selection signal from the command/address signal during a read operation. The address generation circuit outputs the write column address signal as a bank group address signal in synchronization with the write bank selection signal and the internal write bank selection signal or outputs the read column address signal as the bank group address signal in synchronization with the read bank selection signal and the internal read bank selection signal.

Abstract: A storage infrastructure and method for efficiently handing block I/O requests. An infrastructure is described that includes flash memory and a controller that includes: a two dimensional (2D) linked list structure for temporarily storing BIO requests, wherein each BIO request specifies a set of LBAs and wherein the 2D linked list structure includes N vertical linked lists; a BIO request loader that applies a hash function to each LBA in a received BIO request to associate each LBA to one of N hash values, and loads the received BIO request into a horizontal linked list in the 2D linked list structure in which each LBA resides within a vertical linked list based on an associated hash values; and a linked list manager that determines which LBAs in the 2D linked list structure are eligible for processing and when a horizontal linked list can be removed.

Abstract: An information handling system includes an accelerator that advertises, via a single peripheral component interconnect express endpoint, to a processor a plurality of queues from different drives. The processor writes commands and maps each command to target a particular one of the queues. The accelerator performs a queue level logical separation for the mapped command to be processed by the target queue.

Abstract: Embodiments are directed to a bus bridge transfer protocol in a bus bridge system that uses a tag based transfer protocol to identify transactions. The bus bridge may receive a protocol request from an initiator that does not use the tag based transfer protocol. A designated tag consistent with the tag based transfer protocol may be assigned for use in requests from the non-tag conforming initiator. When receiving a request from the non-tag conforming initiator, an initiator flag is set to indicate that the request is from the non-tag conforming initiator and that the response should be forwarded to the non-tag conforming initiator. When receiving a request from a tag conforming initiator, if the request includes the designated tag, the initiator flag is set to indicate that the response should be forwarded to and that the designated tag is being used in a request from the tag conforming initiator.

Abstract: In an example, a method of arbitrating memory requests may include tagging a first batch of memory requests with first metadata identifying that the first batch of memory requests originates from a first group of threads. The method may include tagging a second batch of memory requests with second metadata identifying that the second batch of memory requests originates from the first group of threads. The method may include storing the first and second batches of memory requests in a conflict arbitration queue. The method may include performing, using the first metadata and the second metadata, conflict arbitration between only the first batch of memory of requests and the second batch of memory requests stored in the conflict arbitration queue, which may include at least one other batch of memory requests stored that originates from a group of threads different from the first group of threads stored therein.

Abstract: A method of configuring a Universal Serial Bus (USB) connection between a first and second devices, the USB connection comprising a plurality of data channels, each having a pair of signal links, each signal link including a port at either end of the connection, and a signal wire formed of one or more physical wires extending between corresponding ports. Each of the signal links are configured with a first direction for transmission of data. The first direction is determined based on an initial required data transmission capacity in each direction between the first and second devices. Thereafter, depending on required capacity in the different directions, a selection is made which of the signal links should change their direction of transmission from the first direction to a second direction and a redirection signal is sent to each of the selected signal links to cause the change in direction of transmission.

Abstract: An approach to virtualizing a coherent memory hardware accelerator is provided comprising creating a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table, receiving an Input/Output (I/O) request to use the coherent memory hardware accelerator, generating an I/O operation associated with the I/O request, wherein the I/O operation is passed to the coherent memory hardware accelerator, receiving a map request from the coherent memory hardware accelerator, creating an entry in the reserved virtual address space in the segment table, creating a hardware page table map request for mapping a memory address associated with the client LPAR and returning the reserved virtual address space to the coherent memory hardware accelerator, wherein the coherent memory hardware accelerator has remote direct memory access to memory associated with the client LPAR for performing an acceleration of one or more processes.

Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Abstract: In one embodiment, a set of memory circuits is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional memory circuits, and accordingly the memory circuits can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified-memory circuits and a traditional memory controller, additionally contains encoding and decoding circuitry. In such a system, data are encoded and at least one indicator bit is issued when writing to the modified-memory circuits. The modified-memory circuits in turn store the at least one indicator bit with the encoded data. When the encoded data are read from the modified-memory circuits, the data are transmitted across the bus in their encoded state along with the at least one indicator bit. The logic integrated circuit then decodes the data using the at least one indicator bit to return the data to their original states.

Abstract: This disclosure describes techniques for supporting inter-task communication in a parallel computing system. The techniques for supporting inter-task communication may use hardware-based atomic operations to maintain the state of a pipe. A pipe may refer to a First-In, First-Out (FIFO)-organized buffer that allows various tasks to interact with the buffer as data producers or data consumers. Various pipe implementations may use multiple state parameters to define the state of a pipe. The hardware-based atomic operations described in this disclosure may modify multiple pipe state parameters in an atomic fashion. Modifying multiple pipe state parameters in an atomic fashion may avoid race conditions that would otherwise occur when multiple producers and/or multiple consumers attempt to modify the state of a pipe at the same time. In this way, pipe-based inter-task communication may be supported in a parallel computing system.

Abstract: A system and method are provided for controlling access to memory to support processing of a master control operation. A data control portion is configured to carry out a plurality of data access operations on the memory device, including read, write, and read-modify-write operations for selectively addressed storage locations defined in the memory. An error control portion executes to detect error in a data segment as stored in the memory. The error control portion corrects a data segment read from the memory device for at least one type of detected error. A command control portion generates commands for actuating the data access operations of the data control portion. The command control portion includes a corrective writeback unit executable responsive to detection of correctable error in a data segment to actuate a read-modify-write operation to the data segment's storage locations. The corresponding storage locations of the memory are thereby adaptively scrubbed.

Abstract: A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

Abstract: A data storage device includes a non-volatile semiconductor storage device and a controller that is configured to issue first and second read requests in that order, to read data from the non-volatile semiconductor storage device, in response to receiving a read command, and store read responses to the first and second read requests in a queue in the order they are received. The queue is a circular buffer having a write pointer, a read pointer, and a special read pointer associated therewith, the write pointer being advanced each time contents are written into the buffer, the read pointer being advanced when oldest valid contents in the buffer are read, and the special read pointer being advanced when valid contents in the buffer, excluding the oldest valid contents, are read. As a result, instead of sorting read responses associated with the read command prior to storing them in the queue, the read responses are stored in the queue in the order they are received.

Abstract: A cache and a method for performing data copying are provided. The cache includes a copy logic and be connected to a processor through a first bus and to a memory controller through a second bus, which is different from the first bus. Moreover, the copy logic may perform data copying through the second bus based on a data copy command received from the processor.

Abstract: Remotely synchronizing data communicated in an electronic computing system. Ordered writing of a data set of discrete data packets (data) and a following associated semaphore packet (semaphore) from a source electronic device (source) to a bridge interface device (bridge). Relaxed writing of the data set from the bridge to discrete target memory addresses (targets) of a data-consuming electronic device (consumer), wherein the order of the data and the semaphore written to the targets is different than the order of the data and semaphore written with the ordered writing. Monitoring, by the consumer, the relaxed writing of the semaphore to one of the targets. Issuing a synchronization command to the bridge upon detection of the semaphore having been written to the one target. Sending a synchronization confirmation reply from the bridge after all of the data has been written to the targets.

Abstract: A processor generates stream information indicating a stream of access on the basis of the positional relationship on a storage device among a plurality of accessed first data blocks. The processor associates sequence information representing the positional relationship on the storage device with a plurality of second data blocks prefetched in a memory on the basis of the stream information. When a certain second data block is accessed, the processor searches for another second data block that is determined to be earlier in the order of access made by the stream than the certain second data block, on the basis of the sequence information. The processor removes the found second data block from the memory.

Abstract: A method for transmitting a response to a command from a server in a wireless communication system, according to one embodiment of the present invention, is implemented by a terminal, and comprises the steps of: receiving a command from a server; implementing the command until a timeout expires; transmitting to the server, a first response including an identifier for the command if the implementation of the command is not completed until the timeout expires; and transmitting a second response including the result of the command and the identifier after the implementation of the command is completed.

Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.

Abstract: A multi-port data storage device that can be used simultaneously by both a direct-attached device and a network-attached device, comprising a hard disk drive (HDD), a DAS port, an NAS port, and a controller for controlling access to the HDD by the DAS port and the NAS port.

Abstract: Methods, apparatuses, and systems for handling transactions received after a configuration request, the method, for example, comprising: receiving a configuration change request by a transaction-handling logic block; performing a configuration change by the transaction-handling logic block in response to the configuration change request, wherein the logic block is to handle transactions received prior to receipt of the configuration change request differently than transactions received after receipt of the configuration change request; receiving, by the transaction-handling logic block, a first transaction before receiving the configuration change request; receiving, by the transaction-handling logic block, a second transaction after receiving the configuration change request and before the configuration change is complete; differentiating the first transaction from the second transaction based on the order in which the first and second transactions were received relative to receipt of the configuration chang

Abstract: Generally, this disclosure provides systems, methods and computer readable media for management of sockets and device queues for reduced latency packet processing. The method may include maintaining a unique-list comprising entries identifying device queues and an associated unique socket for each of the device queues, the unique socket selected from a plurality of sockets configured to receive packets; busy-polling the device queues on the unique-list; receiving a packet from one of the plurality of sockets; and updating the unique-list in response to detecting that the received packet was provided by an interrupt processing module. The updating may include identifying a device queue associated with the received packet; identifying a socket associated with the received packet; and if the identified device queue is not on one of the entries on the unique-list, creating a new entry on the unique-list, the new entry comprising the identified device queue and the identified socket.

Abstract: The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

Abstract: Implementations of the present disclosure involve a system and/or method for joining read requests for the same data block sent to a storage appliance. The system and method is configured to receive the first read request for the data block at an I/O layer of the storage appliance. The I/O layer is configured to manage obtaining data blocks from one or more storage devices on the storage appliance. The system and method may then receive a second read request for the data block at the I/O layer of the storage appliance. The first and second read request may then be joined at I/O layer and only a single copy of the data block is returned to a cache in response to the first and second read requests.

Abstract: The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

Abstract: An interface includes a first hardware register field to store respective chunks of a command directed to a device and respective chunks of a response to the command from the device. The interface also includes a second hardware register field to store a size of the command and a size of the response. The first and second hardware register fields are accessible by the device and by a processor external to the device that generates the command, in response to memory not being available to buffer the command and the response.

Abstract: Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.

Abstract: A mechanism is provided to optimize performance of a storage system. A plurality of I/O requests is received. A subset of the plurality of I/O requests is selected. The size of each I/O request of the subset of the plurality of I/O requests is less than a predetermined size, but the combined size of the subset of the plurality of I/O requests is greater than the predetermined size. Furthermore, the subset of the plurality of I/O requests is associated with a single logical unit number. A data transfer command which includes the subset of the plurality of I/O requests is generated. The data transfer command is transmitted.

Abstract: Techniques are disclosed to implement a scheduling scheme for a crossbar scheduler that provides distributed request-grant-accept arbitration between input group arbiters and output group arbiters in a distributed switch. Input and output ports are grouped and assigned a respective arbiter. The input group arbiters communicate requests indicating a count of respective ports having data packets to be transmitted via one of the output ports. The output group arbiter attempts to accommodate the requests for each member of an input group before proceeding to a next input group.

Abstract: Methods and systems for processing transaction packets at a serial interface are disclosed. The method includes receiving transaction information at a serial interface. The method further includes executing one or more pipelined operations based on the transaction information, where the operations relate to processing of the transaction packet. The method is performed such that the serial interface is configured to send and receive transaction packets at a line speed of the serial bus.

Abstract: A method and a system for accessing data are provided. A management module is used for receiving multiple transmission data and multiple identification codes from application programs respectively and storing the transmission data to a queue according to a receiving order. One of the transmission data from the queue is obtained by the management module according to a delivering order, and the obtained transmission data is transferred to a corresponding device through an inter-integrated circuit (I2C) driving module. The management module is used for receiving response data from the device through the I2C driving module and then transferring the received response data to the corresponding application program.

Abstract: A circuit may include a queue, a monitor, and a controller. The queue may receive and store a plurality of commands from a plurality of buses to access a shared set of registers. The monitor may monitor the plurality of commands in the queue to determine whether a period of time needs to be reserved for selected commands from one of the plurality of buses. The controller, if the period of time needs to be reserved, based on the period of time determined by the monitor, may disable acceptance of commands from buses other than the one of the plurality of buses, may execute the selected commands for the one of the plurality of buses, and may allow more than one of the plurality of buses access to results of the selected commands.

Abstract: In one form, a memory module includes a first plurality of memory devices comprising a first rank and having a first group and a second group, and first and second chip select conductors. The first chip select conductor interconnects chip select input terminals of each memory device of the first group, and the second chip select conductor interconnects chip select input terminals of each memory device of the second group. In another form, a system includes a memory controller that performs a first burst access using both first and second portions of a data bus and first and second chip select signals in response to a first access request, and a second burst access using a selected one of the first and second portions of the data bus and a corresponding one of the first and second chip select signals in response to a second access request.

Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.

Abstract: In a network protocol processing system in which variables of each of TCP transmission processing and TCP reception processing depend on each other, asynchronous parallel processing is realized between a transmission processing block and a reception processing block for updated protocol processing. Specifically, the system includes a high priority queue for transferring control data to be processed with high priority, a low priority queue for control data other than the above control data, and priority control means for distributing the control data to two kinds of queues. When a request for session establishment and the session disconnection of a new TCP session is issued from an application during transmission of TCP data, data related with the session establishment and the session disconnection is notified preferentially through the high priority queue, and other control data is transferred through the low priority queue.