Abstract: A bus system includes: a first connection apparatus and a second connection apparatus carrying-out an exchange in accordance with a predetermined protocol; a bus through which the first and second connection apparatuses are connected to each other; and a bridge inserted between the first connection apparatus and the bus, and carrying out an exchange with the second connection apparatus in accordance with the predetermined protocol instead of the first connection apparatus when receiving a disconnection instruction for the first connection apparatus.

Abstract: A SAS expander that includes a virtual device manager and a communications manager. The virtual device manager is to generate a virtual device table comprising virtual device PHYs associated with virtual device drivers for host device drivers to allow communication between the host device drivers. The communications manager is to receive a request from a first host device driver of a first host to communicate with a second host device driver of a second host, and in response to receipt of the request, establish communication between the first host device driver and a virtual device PHY associated with a virtual device driver of the second host device driver.

Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: Transaction identifier expansion circuitry is provided, along with a method of operating such circuitry. The transaction identifier expansion circuitry interfaces between a master device and interconnect circuitry used to couple the master device with a plurality of slave devices to enable transactions to be performed. Transaction analysis circuitry is responsive to each transaction in a sequence of transactions initiated by the master device, to compare at least one attribute of the transaction with predetermined attributes indicative of the target slave device for that transaction. Based on the comparison, an initial transaction identifier is then mapped to one of a plurality of revised transaction identifiers, such that the revised transaction identifier is dependent on the target slave device.

Abstract: In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed.

Abstract: The present invention relates to a far-end control method with a security mechanism including a host transmitting an identification code through the PSTN (Public switched telephone network) to the I/O control device of the far-end. The I/O control device has a CPU to receive the identification code and judge whether the identification code matches with the predetermined value stored therein; if the identification code matches with the predetermined value, the mobile internet connection between the host and the I/O control device is activated to enable the host to mutually transmit information or signals with a far-end control device from the I/O control device through the mobile internet, and the connection will be disabled after the information or signal transmission is completed.

Abstract: In one embodiment, a system includes a memory and a first bridge unit for processor access with the memory coupled with an input-output bus and the memory. The first bridge unit is configured to receive requests from the input-output bus to read or write data receive requests from the MFNU to free memory and choose among the requests to send to the memory on a first memory bus. The system also includes a second bridge unit for packet data access with the memory coupled with a packet input unit, packet output unit, and the memory. The second bridge unit is configured to receive requests to write packet data from the packet input unit, receive requests to read packet data from the packet output unit, and choose among the requests from the packet input unit and the packet output unit to send to the memory on a second memory bus.

Abstract: In one embodiment, a system includes a memory and a first bridge unit for processor access with the memory coupled with an input-output bus and the memory. The first bridge unit is configured to receive requests from the input-output bus to read or write data receive requests from the MFNU to free memory and choose among the requests to send to the memory on a first memory bus. The system also includes a second bridge unit for packet data access with the memory coupled with a packet input unit, packet output unit, and the memory. The second bridge unit is configured to receive requests to write packet data from the packet input unit, receive requests to read packet data from the packet output unit, and choose among the requests from the packet input unit and the packet output unit to send to the memory on a second memory bus.

Abstract: In one embodiment, a system comprises a memory, and a first bridge unit for processor access with the memory. The first bridge unit comprises a first arbitration unit that is coupled with an input-output bus, a memory free notification unit (“MFNU”), and the memory, and is configured to receive requests from the input-output bus and receive requests from the MFNU and choose among the requests to send to the memory on a first memory bus. The system further comprises a second bridge unit for packet data access with the memory that includes a second arbitration unit that is coupled with a packet input unit, a packet output unit, and the memory and is configured to receive requests from the packet input unit and receive requests from the packet output unit, and choose among the requests to send to the memory on a second memory bus.

Abstract: The present invention discloses a method for scheduling queues based on a chained list.

Abstract: A scheduler provided according to an aspect of the present invention provides higher priority for data units in a low priority queue upon occurrence of a starvation condition, and to packets in a high priority queue otherwise. The scheduler permits retransmission of a data unit in the lower priority queue when in the starvation condition, but clears the starvation condition when the data unit is retransmitted a pre-specified number of times. As a result, the data units in the higher priority queue would continue to be processed, thereby avoiding a deadlock at least in certain situations.

Abstract: A remote control system for a vehicle of a type including a data communications bus extending throughout the vehicle and connecting a plurality of vehicle devices within the vehicle may include a remote transmitter and a vehicle remote function controller being responsive to the remote transmitter. The vehicle remote function controller may include a controller data link interface. The remote control system may include a multi-controller data bus adaptor for adapting the vehicle remote function controller to communicate via the data communications bus and may include an adaptor data link interface coupled to the controller data link interface. The multi-controller data bus adaptor may be operable with a given set of controller codes for the vehicle remote controller from among a plurality of different sets of controller codes for a plurality of different vehicle function controllers.

Abstract: A bus control circuit includes a first bus to which a first circuit is connected, a second bus to which a second circuit is connected and a control circuit that transfers data between the first circuit and the second circuit, wherein the control circuit monitors completion of the processing of an access request that is resident in the control circuit.

Abstract: Example embodiments provide various techniques for initiating read-ahead requests. A rate at which applications is requesting data from a data storage device is identified. Additionally, a length of time in retrieving or servicing the data from the data storage device is also identified. The identified rate and length of time in retrieving the data are used to determine when read-ahead requests should be sent to pre-fetch data.

Abstract: An electronic system including modules connected in a ring network is provided. The modules communicate via ring interfaces. The ring interfaces are connected by inter-module links that include a control bus and combined address and data bus. The ring interfaces send and receive single-cycle transactions. The control bus signals the type of transaction and the source and destination modules. The ring interfaces forward transactions to their destinations and may send new transaction when a cycle is empty. Each read operation uses a read request transaction containing an address that is responded to with an acknowledgment transaction that includes the requested data. Each write operation uses two write requests, one containing an address and one containing data. The destination module signals completion of the write operation by sending an acknowledgment transaction.

Abstract: Methods and apparatus related to techniques for translating requests between a full speed bus and a slower speed device are described. In one embodiment, a translation logic translates requests between a full speed bus (such as a front side bus, e.g., running relatively higher frequencies, for example at MHz levels) and a much slower speed device (such as a System On Chip (SOC) device (or SOC Device Under Test (DUT)), e.g., logic provided through emulation, which may be running at much lower frequency, for example kHz levels). Other embodiments are also disclosed.

Abstract: A method is described and presented for creation of an optimized schedule for execution of a functionality by means of a time-controlled distributed computer system, in which the distributed computer system and the functionality have a set of (especially structural and functional) elements of at least one element class and the elements are at least partially in a dependence. The method according to the invention, in which the task is solved, is initially and essentially characterized by the fact that the dependences between the elements are recognized, classified and the elements are assigned to corresponding dependence classes, and that optimization of schedule occurs by coordination of elements of at least one dependence class.

Abstract: When a virtual tape of the main storage system is updated, journal data is created. The journal data is transmitted to the disaster recovery storage system asynchronously with the timing at which the write data is received. The journal data includes a marker to notify of the start of updating and a marker to notify of the completion of updating. The disaster recovery storage system prohibits the use of the copy destination data during the period from start of updating until completion of updating, and permits referencing the copy destination data during other periods.

Abstract: A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available.

Abstract: In certain systems, local requests require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency associated with retrieval of associated information that is not immediately available. Logic operates for each local request to access the local memory to ascertain whether the associated information corresponding to the local request is present. If the associated information is present, a request is placed in an output request queue to service the local request. If the associated information is not present, a request is placed on a bypass path to retrieve the associated information. Requests issue from the bypass path with priority over requests from the output request queue. Useful work is thereby done during the latency of associated information retrieval. The arrangement is useful in a TLB in an MMU.

Abstract: According to an aspect of the embodiment, a message queuing unit of the message processing apparatus stores received messages. A message reception control unit receives a notification of destinations of messages, extracts only the messages for current processes based on a process control table recording current or standby of processes, and transmits the messages to corresponding applications as current processes. On the other hand, the message reception control unit does not transmit the messages to the applications as standby processes.

Abstract: An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued.

Abstract: In a hierarchical bus structure employing a fixed-priority bus access arbitration scheme, accurate arbitration of bus access requests can be carried out even in situations where priority levels are updated according to a system operation mode. In each of a plurality of superordinate hierarchical bus circuits, access requests from respective bus masters included in each corresponding bus master group are arbitrated according to priority levels assigned thereto, and based on the result of the arbitration, a priority communication signal PRA/PRB indicating a priority level of each access-request-permitted bus master is fed to a subordinate bus controller. In a subordinate hierarchical bus circuit, under control of the subordinate bus controller, access request arbitration is carried out according to the priority communication signal PRA/PRB to select a superordinate hierarchical bus circuit or bus master having the highest priority level.

Abstract: System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

Abstract: Included are embodiments for a method for servicing memory read requests. At least one embodiment of a method includes receiving read requests from the I/O device; testing predetermined fields from the read requests to predict a type of read request; and when the type of request is predicted to be a data read request, then route the read request to a first queue. Additionally, some embodiments include when the type of request is predicted to be a control read request, then route the read request to a second queue, wherein the second queue has a higher priority than the first queue; determining which of the first queue and second queue to read; retrieving at least one of the read requests from the determined queue; and processing the retrieved read request.

Abstract: An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.

Abstract: The invention discloses a system and method for reordering the request queue of the hardware accelerator, wherein, the request queue stores therein a plurality of coprocessor request blocks (CRBs) to be input into the hardware accelerator.

Abstract: An operating method applied to an out-of-order executive bus system includes: according to dependency constraints, linking requests using the bus system to form dependency request links having an order; and processing the order of the requests according to the dependency request links. In addition, a bus system is provided. The bus system includes a request queue and a dependency request link generator. The request queue receives and stores a newly received request including at least a link tag. The dependency request link generator generates N dependency request links according to dependency constraints of N link tags of the newly received request, where N is any positive integer. Each link tag of the newly received request is implemented to indicate a link relation with respect to an order of the newly received request and a plurality of unserved requests preceding the newly received request.

Abstract: The disclosure relates to a method and apparatus to efficiently address livelock in a multi-processor system. In one embodiment, the disclosure is directed to a method for preventing a system bus livelock in a system having a plurality of processors communicating respectively through a plurality of bus masters to a plurality of IO Controllers across a system bus by: receiving at an MMIO state machine a plurality of snoop commands issued from the plurality of processors, identifying a first processor and a second processor from the plurality of processors, each of the first processor and the second processor having a first number of snoop commands in the input queue and a second number of responses in the output queue, the first number and the second number exceeding a threshold; issuing a burst prevention response to the first processor and the second process.

Abstract: A computer-implemented device provides security events from publishers to subscribers. There is provided a message bus, configured to contain a plurality of security events. Also provided is a receiver unit, responsive to a plurality of publishers, to receive the plurality of security events from the publishers. There is also a queue unit, responsive to receipt of the security events, to queue the plurality of security events in the message bus. Also, there is a transport unit, responsive to the security events in the message bus, to transport the plurality of security events in the message bus to a plurality of subscribers.

Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Abstract: In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold.

Abstract: An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data. The first and second data each forms a packet being one of a posted, completion, and non-posted packets. The first and second frequencies are independent of each other and bounded within first and second frequency ranges, respectively. A queue structure stores packets used in a credit-based flow control policy.

Abstract: A data processing apparatus and method are provided for connection to interconnect circuitry, in order to enable the data processing apparatus to act as a master device to initiate transactions conforming to an interconnect protocol associated with the interconnect circuitry. The data processing apparatus has a main controller for executing a programmable sequence of instructions including a transaction sequence of instructions used to process a transaction to be initiated by the data processing apparatus. The transaction sequence of instructions is programmed dependent on the interconnect protocol. The data processing apparatus further has an interconnect interface unit comprising a plurality of queues including at least one send queue for issuing outbound payload information to the interconnect circuitry, and at least one receive queue for receiving inbound payload information from the interconnect circuitry.

Abstract: A computer-implemented device provides security events from publishers to subscribers. There is provided a message bus, configured to contain a plurality of security events. Also provided is a receiver unit, responsive to a plurality of publishers, to receive the plurality of security events from the publishers. There is also a queue unit, responsive to receipt of the security events, to queue the plurality of security events in the message bus. Also, there is a transport unit, responsive to the security events in the message bus, to transport the plurality of security events in the message bus to a plurality of subscribers.

Abstract: In a hierarchical bus structure employing a fixed-priority bus access arbitration scheme, accurate arbitration of bus access requests can be carried out even in situations where priority levels are updated according to a system operation mode. In each of a plurality of superordinate hierarchical bus circuits, access requests from respective bus masters included in each corresponding bus master group are arbitrated according to priority levels assigned thereto, and based on the result of the arbitration, a priority communication signal PRA/PRB indicating a priority level of each access-request-permitted bus master is fed to a subordinate bus controller. In a subordinate hierarchical bus circuit, under control of the subordinate bus controller, access request arbitration is carried out according to the priority communication signal PRA/PRB to select a superordinate hierarchical bus circuit or bus master having the highest priority level.

Abstract: A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method for determining and communicating the existence of a hybrid bus is disclosed. A method for determining a path to a senior border node is disclosed, as is a method for identifying a senior border node Various methods for properly issuing gap tokens within a beta cloud are disclosed.

Abstract: A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

Abstract: A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message when it cannot supply the requested data in a short period of time. When the responding agent knows that the requested data will shortly arrive in its buffers, it may first send an identification signal to the requesting agent, indicating to the requesting agent that it should prepare to receive the data shortly. After one or more bus clock cycles, the responding agent may then subsequently send the corresponding data message to the requesting agent.

Abstract: A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Abstract: A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.

Abstract: The invention increases performance of HTTP over long-latency links by pre-fetching objects concurrently via aggregated and flow-controlled channels. An agent and gateway together assist a Web browser in fetching HTTP contents faster from Internet Web sites over long-latency data links. The gateway and the agent coordinate the fetching of selective embedded objects in such a way that an object is ready and available on a host platform before the resident browser requires it. The seemingly instantaneous availability of objects to a browser enables it to complete processing the object to request the next object without much wait. Without this instantaneous availability of an embedded object, a browser waits for its request and the corresponding response to traverse a long delay link.

Abstract: A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

Abstract: A low latency peripheral device sharing system has a host computer with an operating system, a kernel memory buffer, applications, device specific drivers, and a peripheral server driver. The server driver intercepts function calls invoking the local serial ports, and passes standard serial data from the application to a local area network. A device server on the local area network reads the data using a hybrid read block (semi-blocking read), and writes the data to the FIFO registers of the serial device and the remaining data to a queue for the serial device. Finally, the device server times the serial data and returns an intercharacter interval timer flag to the host computer to terminate a read operation.

Abstract: The disclosure relates to a method and apparatus to efficiently address livelock in a multi-processor system. In one embodiment, the disclosure is directed to a method for preventing a system bus livelock in a system having a plurality of processors communicating respectively through a plurality of bus masters to a plurality of IO Controllers across a system bus by: receiving at an MMIO state machine a plurality of snoop commands issued from the plurality of processors, identifying a first processor and a second processor from the plurality of processors, each of the first processor and the second processor having a first number of snoop commands in the input queue and a second number of responses in the output queue, the first number and the second number exceeding a threshold; issuing a burst prevention response to the first processor and the second process.

Abstract: An operating method applied to an out-of-order executive bus system includes: according to dependency constraints, linking requests using the bus system to form dependency request links having an order; and processing the order of the requests according to the dependency request links. In addition, a bus system is provided. The bus system includes a request queue and a dependency request link generator. The request queue receives and stores a newly received request including at least a link tag. The dependency request link generator generates N dependency request links according to dependency constraints of N link tags of the newly received request, where N is any positive integer. Each link tag of the newly received request is implemented to indicate a link relation with respect to an order of the newly received request and a plurality of unserved requests preceding the newly received request.

Abstract: A data processing device with an efficient mechanism for controlling bus priority of multiple processors. The device has a data memory that is accessible to the processors via each processor's individual control bus and a common control bus. A bus selector is disposed between the individual control buses and the common control bus and controlled by a bus arbiter that resolves bus requests on the individual control buses from the processors attempting access to the data memory. The bus arbiter sends a selection command to the bus selector, thereby permitting a specified processor to reach the data memory. A bus monitor counts bus requests and conflicts between them, determines priority of each processor attempting access to the data memory according to the count results, and sends a wait command signal to low-priority processors so as to delay their access to the data memory.

Abstract: Techniques are described herein for expanding the range of data targeted in I/O requests made by clients, so that the expanded range results in aligned I/O operations within the file system. Data that is included in the expanded range, but was not actually requested by the client, is trimmed off the data chunk returned by the file system, so that the client receives only the data required by the client. The blocks that contain the partially-read data are cached, so that they can be provided to the clients in response to subsequent I/O requests, without having to retrieve the blocks again from the file system. The I/O requests of multiple clients are handled by a read scheduler that uses a single global queue for all such requests. When appropriate, the read scheduler creates companionship relationships between the requests, and services the “companion” requests based on the data returned for the requests with which the companion requests are associated.