Abstract: Disclosed is a transmit media access controller having a transmit interface unit configured to receive packet data, transfer control signals and control information from an upper layer. The transmit media access controller also includes a transmit controller for processing the packet data based on the control information received from the upper layer. The transmit control block is bi-directionally coupled to the transmit interface unit. While the packet data is being processed, new control information may be received by the in communication with the transmit controller. The transmit media access controller further includes an interface unit configured to receive packet data from the transmit cyclic redundancy check unit before being transmitted to a physical layer.

Abstract: A method and circuit interface for multiplexing an input port and an output port of a microprocessor into a single external interface, wherein the input port and the output port never operate at the same time, is normally active upon a battery cycle, includes a resistor network, a level shifter and a power supply. The resistor network is coupled between the output port and the single external interface for receiving an input signal from the single external interface for receipt by the input port and for receiving an output signal from the output port for receipt by the single external interface. The level shifter is coupled to the input port and the resistor network for translating the input signal from the resistor network into a second input signal recognizable by the input port. The power supply is coupled to the resistor network and the level shifter for providing power to the input port so as to enable the input port to recognize the second input signal.

Abstract: A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to the different layers, GET, CHECK and PROCESS, for appropriate handling by that portion of each stage. In the GET layer, partial words passing through each stage are analyzed to determine whether they constitute an encounter pair. In the CHECK layer a determination is made as to whether the word selected by the GET layer requires further modification. Finally, in the PROCESS layer operations are performed on the words themselves based upon control messages from the other layers. The layers of the processor communicate with each other using suitable communication paths such as First In First Out registers.

Abstract: A storage target device controller (such as an embedded controller in a SCSI disk drive) processes multiple commands concurrently in accordance with the methods and structures of the present invention. Each command is stored within its own context within the target device controller to retain all unique parameters required for the processing of each command. Processing of multiple commands permits switching of command contexts within the target device to improve utilization of resources associated with the target device. For example, when a first, active, command context is prevented from further processing due to the status of the disk channel, an inactive command context may be swapped with the active command context to better utilize the host channel communication bandwidth. Similarly, a first active command context may be configured to automatically switch to a linked command context upon completion of processing to further ease management of multiple contexts.

Abstract: To reduce access frequency to a CPU for recording/reproducing digital audio data, a control system of FIFO memories of the invention applied to an sound codec apparatus comprises means (2, 4, 7, 9 and 10) for controlling a first and a second FIFO memory (3 and 8) to store recording data sequentially and to output stored recording data sequentially when the apparatus is used exclusively for recording; and controlling the first and the second FIFO memory to store the reproducing data sequentially and to output the stored reproducing data sequentially when the apparatus is used exclusively for reproducing.

Abstract: Data formats (page description data, intermediate data and raster data) for compositing respective ones of first to fifth pages with each other are previously determined. An interpreter and a renderer convert the respective pages to the data formats for compositing the same with each other. A page requiring no conversion is not converted. After the conversion, the pages expressed in the page description data, the intermediate data and the raster data are subjected to first composition, second composition and third composition respectively. The composition and the conversion can be dispersively performed, to enable processing in a short time without increasing the quantity of data in individual processing. Thus provided are an apparatus for and a method of processing printing data, which can process data in a short time with high throughput.

Abstract: Methods and associated apparatus for performing concurrent I/O operations on a common shared subset of disk drives (LUNs) by a plurality of RAID controllers. The methods of the present invention are operable in all of a plurality of RAID controllers to coordinate concurrent access to a shared set of disk drives. In addition to providing redundancy features, the plurality of RAID controllers operable in accordance with the methods of the present invention enhance the performance of a RAID subsystem by better utilizing available processing power among the plurality of RAID controllers. Under the methods of the present invention, each of a plurality of RAID controllers may actively process different I/O requests on a common shared subset of disk drives. One of the plurality of controllers is designated as primary with respect to a particular shared subset of disk drives.

Abstract: A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To permit parallel flow-through operation, each of the two buffers is organized into a number of fixed-sized pages that are accessible via the peripheral bus only one page at a time. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two pages in a data path simultaneously: one for receipt and another for transmission.

Abstract: A system for serializing and synchronizing data stored in a tape drive emulation system utilizes a physical lock system and control data MUTEXes to assure serialization.

Abstract: A wired modem normally plugs directly into a computer and connects to a telephone system by wired connection to a wall jack. This same modem can be used in a wireless configuration by plugging it into a single-module base station unit located near the wall jack and containing a baseband-to-wireless transceiver. A single module remote station plugs into the computer in place of the modem, and contains another baseband-to-wireless transceiver for communicating wireless data with the base station. The base and remote stations duplicate very little of the functionality performed by the modem, making the modem easily replaceable in either wired or wireless configurations.

Abstract: A modular distributed I/O system includes a computer coupled to module banks through a network bus. A module bank includes a communication module, terminal bases, and I/O modules. The adjoined terminal bases form a local bus mastered by the communication module. The I/O modules connect to the local bus through terminal bases. I/O modules are pluriform and programmable. The communication module maintains a memory image of the configuration state of each I/O module resident in the module bank. A memory image persists when an I/O module is removed from its terminal base. The memory image is used to configure a new I/O module which is inserted into the same terminal base. The communication module monitors for communication failure on the network bus, and is configured to capture the state of the module bank and automatically restore this captured state after a power-loss event. The terminal bases realize a local bus which includes a parallel bus, a serial bus, and an address assignment bus.

Abstract: Distributed digital signal processing is executed by a number of processing elements. Signal processing processes are scheduled for individual processing elements according to the data flow principle. To this end, the flow of signal samples is subdivided into data tokens, each of which has several samples. A process is started in a processing element in response to the detection of a data token presented so as to undergo the process. The detection is processed by a control unit which, in response thereto, allocates a communication connection between a first processing element producing the relevant data token and a second processing element which is to process the data items present in the data token. Scheduling is thus achieved by allocation of the communication connection. Furthermore, in order to avoid deadlock problems, restrictions are imposed as regards the execution sequence of processes.

Abstract: A solution to the problem of undesired serialization of bus controlled instrument measurement delays for multiple instances of programmatically controlled measurement processes is to configure the bus operations and the control programs to allow the issuance of a command within the context of a first collection of such instruments, without having to wait for the corresponding data before issuing commands within the context of a second collection. This is done by instructing the equipment in the collection to signal that they have data instead of the more customary immediately issued "@ address talk", which is then followed by the delay needed by the equipment to make the measurement. Instead, the "have data" signals are associated with the devices that originated them and then the bus instructions that request the data are issued. In conjunction with this, the usual bus I/O commands in the controlling programs may be replaced with calls to a library that operates in just this fashion.

Abstract: A data input-output device includes a single memory, an input interface unit for storing data in the memory, an operation unit for fetching the data from the memory, for performing operations on the data, and for updating the data in the memory when necessary, an output interface unit for transmitting the data in the memory that has been operated on by the operation unit to outside of the device, and a bus control unit for setting a priority for each of these units and for controlling memory access by these units according to the priorities every time a predetermined number of bytes of data is transferred.

Abstract: Potable multimedia terminal which is small and consumes low power, can process a large quantity of multimedia data such as video and audio data. Portable multimedia data input/output processor can be made smaller by using a pen as an input device and can also process a large quantity of multimedia data at a high speed by adopting a PCI bus as a local bus of a system. To retrieve, compress, and decompress multimedia data, main components of this portable multimedia data input/output processor are comprised of audio codec for compressing and decompressing audio data, video codec controller for compressing and decompressing video data, and multimedia processor for transmitting audio data to wireless communication controller and video data to video codec controller and to graphic processor. The method for retrieving multimedia data includes steps of receiving data, de-interleaving received data into audio, video, and graphic data, decompressing the data, and outputting the data to output device.

Abstract: The invention relates to a method and an arrangement for operating a bus system having at least one master unit and at least one slave unit, having a bus and a bus control unit for the bus arbitration and for controlling the data transfer. The data transmission is split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus is cleared for the data transmissions of other master units in a first data transmission configuration, or the bus is blocked between the request data transfer and the response data transfer, in a second data transmission configuration and slave units. In the case of a response transfer, the master and slave are changed round.

Abstract: In a microcontroller, a synchronous serial port is coupled to a DMA unit such that a series of DMA writes to the synchronous serial port can be followed by a series of DMA reads from the synchronous serial port, all without intervention or the execution of the microcontroller.

Abstract: In a data transfer system in which when a first to fourth terminals require reading data, the data are read out of a first to fourth storages to be stored in a first and second buffer memories while a first and second virtual groups of storages are alternately switched every constant cycle, and thereafter a first and second data sending units send the data stored in the first and second buffer memories to the terminals; on the other hand, when the first to fourth terminals require writing data, received data is divided in a way to distribute the process loads of data read and data write of the divided data equally into a first and second data transfer units. At the same time, the data are stored in the first and second buffer memories of the first and second data transfer units, and thereafter the data are written into the first to fourth storages while switching the first and second virtual groups of storages alternately.

Abstract: To implement full gathering of data transfers from a processor to a system bus without adding many levels of logic to the write enable logic for transaction queue entries or reducing the processor operating frequency, gatherable combinations are divided and gathering is performed in multiple stages operating in parallel. During the first stage, a subset of the full gathering is performed between incoming transactions and the last transaction received, coalescing the two transfers into a single transaction entry if one of the possible combinations within the subset is satisfied. During the second stage, existing queue entries are tested for the remainder of the full gather combination set and merged if a combination within the remaining subset is satisfied.

Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

Abstract: An improved system and method for the transference of data with minimal delay and loss is disclosed. Primarily useful in maintaining the flow of an isochronous data stream, the present invention minimizes delay through the use of a shared buffer for both the data source and destination and without reliance upon an interrupt to transfer data. The present invention minimizes data loss through the use of a double buffer, the size of which is adjusted to accommodate interrupt latency without increasing transference delay.

Abstract: An apparatus and method is provided for caching data in a universal serial bus (USB) system. In one embodiment, the present invention employs a host computer coupled to an I/O device via a USB. The host computer includes a data cache for storing data retrieved from the I/O device. The data cache allows data to be returned to the host computer upon request without accessing the I/O device via a USB transaction. A cacheability look-up table and cache table are provided to ensure the integrity of data returned to the host computer. Requested data is returned from the I/O device if the cacheability look-up table indicates the requested data is noncacheable. Data is returned from the data cache if the cache table indicates the requested data is available in the cache as valid data. If the cache table indicates the requested data is not available in the cache as valid data, the requested data is returned from the I/O device along with data stored in predetermined I/O device addresses.

Abstract: An information recording and reproducing apparatus according to the present invention includes a read-ahead history buffer which is used as a ring buffer. A read-ahead operation is performed, every time a reproduction request is made by a host device, so as to maintain the read-ahead data after the last block for which reproduction has been requested at a predetermined value. Data which has already been requested by the host device and has not been overwritten by the read-ahead operation is treated as history data. As a result, data centered around (i.e., preceding and following) the last block for which the host device has requested reproduction is always secured as cache data.

Abstract: A computer network peripheral device transfers received data packets to a storage unit of a host computer system on a nonsequential data packet portion by portion basis instead of a sequential whole data packet by whole data packet basis of the prior art. Any received data packet is segmented into a plurality of data packet portions, and the data packet portions may be transferred in a nonsequential order. Such nonsequential transfer of data packet portions to the storage unit of the host computer system may optimize efficient data processing of the data packets by the host computer system.

Abstract: In the UNIX Operating System, modifying the kernel routine Physio, to enable a single system call to set up a number of concurrent direct memory access (DMA) channels between memory and the data buffers of a device. Many character device drivers use the UNIX Physio facility for I/O. The traditional implementation of Physio handles I/O in a serial manner by performing gather-write or scatter-read operations. This invention is an enhancement to Physio to support parallel I/O operations.

Abstract: When a transmission request reception process controller accepts a request to transmit information, the information is read from a memory in order of addresses generated by an address generator. A transmission information generator adds addresses of the information to the read information, for transmission to the transmission requester. When accepting another request to transmit the same information while the information is being transmitted, the transmission request reception process controller causes the information to be transmitted to the latter transmission requester starting at the current point in the information being transmitted to the former transmission requester. After generating the last address of information, the address generator returns to the top address and again continues generating the addresses of the information. The information read from the memory according to the generated addresses is transmitted from output circuits 14 and 16.

Abstract: The present invention includes a method of providing data to a memory device to be read at a first frequency comprising the steps of writing data to a memory device at a second frequency; blocking the writing of data after a predetermined amount of data is written; and writing data to the memory device in response to an address. Also included is a monitor circuit comprising a monitor state machine coupled to receive inputs including a comparison result, count signals and a load enable, and configured to output a data enable signal in response to the inputs.

Abstract: A data processing device 100 uses a portion of a random access memory 111 as an input buffer for holding a portion of a stream of data which is received by an input interface 130. Likewise, a portion of a memory 121 is used as an output buffer for holding a portion of processed data which is output by an output interface 140. A processing unit 110 within the processing device manages the flow of input and output data. The input interface asserts an I/O request 860 when it receives a data word, and the output interface asserts an I/O request 870 when it needs a data word. In response to an I/O request, fast interrupt circuitry inserts a ghost instruction which is formed by doppelganger circuitry into an instruction sequence which is being accessed from a ROM 112. The ghost instruction performs the requested data transfer.