Abstract: An interface architecture includes a plurality of pipelines each controlled by a respective line processor. An onboard ESCON protocol conversion device distinguishes customer data to be stored on a disk or read from disk versus header information. Transmit and receive frame dual port rams store transmitted frame and received frame information, stripping frame/header information from user data. Data to be stored in Global Memory is stored temporarily in FIFOs. An assembler/disassembler in each pipeline receives data from FIFOs (on a write), and transfers data to FIFOs (on a read). A buffer dual port ram (DPR) is configured to receive data for buffering read operations from and write operations to the GM. Data transfers between the assembler/disassembler and the buffer DPR pass through Error Detection And Correction circuitry (EDAC). A plurality of state machines arranged as an Upper Machine, Middle Machine and Lower Machine facilitate movement of user data between DPR and Global Memory (GM).

Abstract: A handheld computer which contains an LCD display having a digitizing surface to allow pen input. Internal storage takes several forms, such as a large flash ROM area, battery-backed up RAM and an optional hard disk drive. Several alternative communication paths are available, such as the previously mentioned modem, a parallel printer port, a conventional serial port, a cradle assembly connected to the host computer, and various wireless short distance techniques such as radio frequency or infrared transmission. The computer can readily communicate with other sources, particularly to a host desktop computer, to allow automated synchronization of information between the host and the handheld system. Preferably the remote synchronization is performed at several user selectable levels. When the handheld computer is in a cradle and actively connected to the host computer, automatic capture of updated data in the host computer is performed.

Abstract: The present invention is a method and apparatus for exchanging information between an electronic book and a cartridge. The electronic book has an on-board storage and the cartridge contains a cartridge storage. It is determined if the cartridge is present. If the cartridge is present, a transfer mode is identified. The information between the on-board storage and the cartridge storage is then transferred according to the identified transfer mode.

Abstract: The present invention is a method and apparatus for enhancing interface between a host and a point of deployment (POD) module having parallel signal paths carrying parallel signals of a transport stream. The parallel signals operate at a parallel clock rate. An interface card has a serial portion to provide serial signal paths carrying serial signals between the host and the POD module. Each of the serial signals corresponds to the parallel signals. Each of the serial signals operating at a serial clock rate.

Abstract: A system for monitoring issuance of interrupt and transaction commands without involving central processor units of computer systems. The system employs a fabric controller to manage transaction commands among and host devices. The system employs an interrupt controller to manage interrupt commands issued by devices. The system further employs a concurrent bridge to support communication between the controllers and at least one host device. With this system, congestion due to control and data traffic is minimized and a more efficient operation of central processor units is achieved.

Abstract: A method and apparatus for coupling multiple computer peripherals to a computer system through a single I/O port is disclosed. The inventive apparatus includes an interface device having a first connector for coupling to the I/O interface of a computer system, a second connector for coupling a first computer peripheral to the I/O port and a third connector for coupling a second computer peripheral to the I/O port so that both peripherals are simultaneously coupled to the I/O port. Within the housing of the preferred embodiment of the interface device, control and data lines for receiving data associated with the I/O interface are coupled from the first connector to the third connector and control and data lines for transmitting data associated with the I/O interface are coupled from the first connector to the second connector. By separating the transmit and data functions of the I/O interface so they may be routed to separate connectors, computer peripherals of difference types, i.e.

Abstract: A multiple-media duplicating system concurrently copies digital data from a master media to several copy media. The system includes a master input/output (“I/O”) port and several copy I/O ports equal in number to the number of copy media. A special I/O port, coupled in parallel to each of the copy I/O ports, effects a concurrent transfer of digital data from the master media to all of the copy media. The system may further include a circuit which effects copying of data from the master media to the copy media while concurrently preventing conventional direct access to devices that contain the media. A particularly preferred embodiment further includes an adjustable, variable-frequency generator that is coupled to the digital logic circuit, and supplies a clock signal to the digital logic circuit which determines a rate at which digital data is copied from the master media in parallel to the copy media.

Abstract: The bridge module is connected between at least two bus systems and is suitable for serial data transfer of binary data from one of the bus systems to the other one of the bus systems. A single memory device is provided for buffer storage of the data during a data transfer. The data transfer, which is controlled exclusively by the data to be transmitted, is thus carried out in a simple manner and completely automatically, without the interposition of a processor unit. It is thereby possible very easily and thus also at an attractive cost to specify a module which is suitable for the data transfer between different bus systems.

Abstract: A communication system includes a communication control section which may receive bus use requests of both of a DV camera/recorder (50) which becomes an output machine on a serial bus (60D) and a DV deck (40) which becomes an input machine on the serial bus (60D), may check whether or not the serial bus (60D) which were requested to be used is in use, may open the serial bus (60D) to the DV camera/recorder (50) and the DV deck (40) which issued the use requests, may protect a connection between the DV camera/recorder (50) and the DV deck (40), may open a serial bus (60A) to an IRD receiver (10) and a mini disc (20) which issued use requests and which may protect a connection between the IRD receiver (10) and the mini disc (20).

Abstract: A method using a Reflective Timing Signal to automatically adjust the timing parameters of an asynchronous bus to compensate for its physical extension.

Abstract: The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A cooperative interconnection technique in accordance with the invention utilizes an inter-cluster move instruction specifying a source cluster and a destination cluster to copy a value from the source cluster to the destination cluster. The value is transmitted over a designated interconnect structure within the processor, and the inter-cluster move instruction is separated into two sub-instructions, one of which is executed by a unit in the source cluster, and another of which is executed by a unit in the destination cluster. These units may be, e.g.

Abstract: An apparatus, program product and method utilize an event-driven communications interface to support communications between multiple logical partitions in a logically-partitioned computer. The event-driven communications interface is at least partially disposed within a partition manager that is accessible to each of the logical partitions. Events are typically passed between logical partitions in the form of messages that are passed first from a source logical partition that initiates the event, through the partition manager, and then to a target logical partition to which the event is directed, while maintaining the independent address spaces associated with the logical partitions.

Abstract: A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To permit parallel flow-through operation, each of the two buffers is organized into a number of fixed-sized pages that are accessible via the peripheral bus only one page at a time. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two pages in a data path simultaneously: one for receipt and another for transmission.

Abstract: A plurality of state machines arranged into three functional units, an Upper Machine, Middle Machine and a Lower Machine facilitate movement of user data between a buffer memory and a Global Memory (GM) in a data transfer interface. The Middle Machine controls all data movement to and from the GM. Although not directly in the data path, it is responsible for coordinating control between elements that comprise data transfer channels. The Middle Machine is interconnected to and provides control and coordination between the Upper and Lower sides of the buffer memory. The Lower Machine connects to a data assembly mechanism of each pipe. The Upper Machine connects to the backplane, which in turn connects to Global Memory. The actual data transfers between the buffer memory and GM are controlled by the Upper Machine, and transfers between the buffer memory and the data assembly mechanism are controlled by the Lower Machine.

Abstract: A handheld computer which contains an LCD display having a digitizing surface to allow pen input. Internal storage takes several forms, such as a large flash ROM area, battery-backed up RAM and an optional hard disk drive. Several alternative communication paths are available, such as the previously mentioned modem, a parallel printer port, a conventional serial port, a cradle assembly connected to the host computer, and various wireless short distance techniques such as radio frequency or infrared transmission. The computer can readily communicate with other sources, particularly to a host desktop computer, to allow automated synchronization of information between the host and the handheld system. Preferably the remote synchronization is performed at several user selectable levels. When the handheld computer is in a cradle and actively connected to the host computer, automatic capture of updated data in the host computer is performed.

Abstract: In a data linking method of extracting data of a host data base on a computer into a portable remote terminal, an item definition data base which defines a record attribute, an object storage data base which stores object data on a record basis, a relation definition data base which defines relations among object data and a definition data base which defines relations among the respective data bases, and conducts synchronous processing of writing.

Abstract: An output system having a data processor and an printer or other output device for outputting data in a specific format, which is sent from the data processor, to which is installed driver software for controlling the output device. Whether the data on output request passes the driver software is determined in sending data to the output device. Data are prohibited from being sent to the output device for output requests on which data bypasses the driver software.

Abstract: Disclosed is a system and method for processing a data access request (DAR). A processing unit, such as a storage controller, receives a DAR, indicating data to return on a channel, such as a channel connecting to a host system, and priority information for the received DAR. The processing unit retrieves the requested data for the received DAR from a memory area, such as a cache or direct access storage device (DASD), and determines whether there is a queue of data entries indicating retrieved data for DARs to transfer on the channel. The queued DARs include priority information. The processing unit processes at least one data entry in the queue, the priority information for the data entry, and the priority information for the received DAR to determine a position in the queue for the received DAR. The processing unit then indicates that the received DAR is at the determined position in the queue and processes the queue to select retrieved data to transfer on the channel to the host system.

Abstract: A method and apparatus for communicating a configuration operation throughout an integrated circuit chip is disclosed. The present invention receives a configuration operation having a configuration word. The configuration word is stored in a defer register until the configuration word can be communicated to one or more target local configuration registers, which are the registers in which the configuration word is to be stored and/or used. During the time period during which the configuration word is stored in the defer register, subsequent operations including operations having configuration data associated with the configuration word are delayed. In one embodiment, operations are caused to retry if a configuration word is stored in the defer register. The configuration data associated with the configuration word is received after the defer register has been cleared. After the configuration data has been received, subsequent operations are blocked for a predetermined period of time.

Abstract: A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Abstract: The present invention provides for an apparatus for transferring information in a network computing system environment. The apparatus comprises of a main storage and an information transfer interface mechanism in processing communication with the main storage. The interface mechanism is capable of coupling to a plurality of input/output devices. The apparatus also comprises of means for transferring a packet of data between the interface mechanism and the main storage and means for concurrently transferring and processing a plurality of other packets of data between the interface mechanism and said main storage.

Abstract: A system for compressing data and transferring the compressed data between a plurality of apparatus within a short period of time includes a dividing unit for dividing data into a plurality of divided strings of byte data, a compressing unit for concurrently compressing the strings of byte data which have been divided by the dividing unit, an expanding unit for concurrently expanding the compressed strings of byte data which have been transferred, a mixing unit for mixing the divided groups of byte data which have been compressed by the compressing unit, a distributing unit for distributing the groups of byte data which have been mixed by the mixing unit and transferred, and a combining unit for combining the groups of byte data which have been expanded by the expanding unit.

Abstract: Error correction and detection for time-multiplexed binary 72-tuples over 18 wires to detect a wire fault. A syndrome is computed using a parity check matrix, where circuits for realizing the parity check matrix multiplication can be realized with only two levels of XOR gates and in which the computation is pipelined to process the time-multiplexed binary 72-tuple.

Abstract: An improved method and apparatus for performing burst read operations in a nonvolatile memory includes a burst read device coupled to the nonvolatile memory, wherein the burst read device senses a page of data from the nonvolatile memory, latches the page of data, synchronously reads the data one word at a time, and senses a next page of data concurrently with the synchronous reading.

Abstract: Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.

Abstract: A command queuing engine in a target controller ASIC automatically detects sequential commands received from an initiator and generates a linked list of data transfer descriptors for the sequential commands. The data transfer descriptors are automatically processed by the command queuing engine to reduce command overhead from interrupt processing by a microprocessor in the target controller, thereby improving the performance of the target controller.

Abstract: A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two memory portions in a data path simultaneously: one for receipt and another for transmission. Specifically, each data path uses a memory portion to hold data that is currently being received, while using another memory portion containing data that was previously received for simultaneous transmission from the host adapter. Each of the data paths transfers data in a continuous manner irrespective of the context (e.g.

Abstract: An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single ten bit word and compensates for DC imbalance by inverting selected words in the transmission sequence to correct for a DC imbalance resulting from the transmission of a prior unbalanced word. One or more encoding lookup tables are employed at the encoder to map each byte into a ten bit run length limited code for serialization and transmission over the serial data link. A second decoding lookup table is employed at the decoder to map the received 10 bit run length limited code into the original 8 bit value.

Abstract: The present invention provides for a computer program product for use with a computer system having a main storage device in processing communication with an information transfer interface mechanism capable of coupling to a plurality of input/output devices. The computer program device comprises of a data storage element included in the main storage device having a computer usable medium with computer readable program means for receiving and retrieving data and computer readable code means for concurrently receiving multiple packets of data from said interface mechanism. It also includes computer readable code means for concurrently storing multiple packets of data concurrently in said data storage element as well as computer readable code means for storage and retrieval of multiple packets of data concurrently between said interface mechanism and said data storage element.

Abstract: A method of transferring image data between an initiator device and a target device using a IEEE 1394 standard bus. The present invention combines management functions, command functions, and isochronous data transfer to achieve the transfer of image data. The present invention discovers a target configuration using IEEE 1394 reads of a target configuration read only memory space. As part of the management function, the present invention uses a modified asynchronous data transfer protocol to establish a connection between the initiator and the target. Next, the present invention uses command functions to begin a job to transfer image data over an isochronous channel. Also, the present invention uses asynchronous data transfer to exchange printer job language commands to end a job.

Abstract: A programmable sideband port is provided. The programmable sideband port contains a register with a plurality of memory locations each being connected to a bit in the port. The port is programmable by a processor which has access to all the memory locations.

Abstract: A method and apparatus for parallel communication from a PC to an external device. The apparatus is connected between the PC and the external device. The apparatus is encoded so that its identity can be read by the PC and the external device. The PC then communicates with the external device through the apparatus, informing the external device of the communication mode that the PC uses to communicate. In response, the external device communicates through the apparatus to inform the PC of the communication mode that it uses. Subsequently, the PC transmits information to the apparatus for retransmission to the external device. As a result of the data it has previously obtained from the PC and the external device, the apparatus configures itself so that it can optimize the transmission of information from the PC to the external device. The method is the method of receipt and processing of the data used to optimally configure the apparatus of the invention.

Abstract: A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation—one which might affect the storage hierarchy as perceived by other devices within the system—is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the “sync” instruction supported by the PowerPC™ family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes.

Abstract: A microcontroller comprising a first memory 2 used by a CPU1 to perform arithmetic operations; a second memory 3 for a multitask process for storing data transferred from an external device 30 during the arithmetic process of CPU1; bus switches 4 and 5 for switching over the connection of data buses of CPU1 and the external device 30; and an address supply portion 7, which is connected to the address bus of the external device 30 while the second memory 3 is connected to the data bus of the external device 30, and which generates address signals by which to store data from the external device, wherein this microcontroller can perform a multitask process without adopting an expensive device such as a dual port RAM.

Abstract: An output method and apparatus, a storage medium, and an output control program product are provided for sequentially receiving a plurality of control information for setting an output environment based on externally supplied data, and controlling the setting of the output environment in accordance with the first received control information.

Abstract: When a transmission request reception process controller accepts a request to transmit information, the information is read from a memory in order of addresses generated by an address generator. A transmission information generator adds addresses of the information to the read information, for transmission to the transmission requester. When accepting another request to transmit the same information while the information is being transmitted, the transmission request reception process controller causes the information to be transmitted to the latter transmission requester starting at the current point in the information being transmitted to the former transmission requester. After generating the last address of information, the address generator returns to the top address and again continues generating the addresses of the information. The information read from the memory according to the generated addresses is transmitted from output circuits 14 and 16.

Abstract: A technique for controlling an interactive presentation is disclosed. In one embodiment, a processing device receives at least one of a plurality of commands, wherein each of the plurality of commands corresponds to a respective operation the performance of which is directly associated with controlling a particular aspect of the interactive presentation. The processing device processes each of the received commands such that each corresponding operation is performed to control a particular aspect of the interactive presentation.

Abstract: A system and method for providing transaction indivisibility in a transaction processing system through the use of commonly-accessible modules for monitoring and maintaining proper source message sequencing is provided. A source message is transmitted from the host processing unit upon recovery of a failure of the host processing unit, where the source message includes information destined for the database, and an identifying sequence number. The identifying sequence number is compared to a stored sequence number, where the stored sequence number is associated with an immediately preceding source message received prior to the failure of the host processing unit. A source message indivisibility failure is indicated where the identifying sequence number is not consecutive with respect to the stored sequence number, while the source message is added to a message execution queue if the identifying sequence number is consecutive with respect to the stored sequence number.

Abstract: A computer system (100) comprises a processor (110), a memory (300), an interface (101) and peripheral devices (120-1, 120-2, 120-3). The interface has a pointer generator (160), a port (150), a decoder (170), and a parameter register (180). The port (150) transmits data words D(k) (380-k) from the memory (300) to the peripheral devices (120-1, 120-2, 120-3) or vice versa. Communication parameters are stored as parameter sets {P.sub.m } in parameter fields (185-m) of the parameter register (180). The decoder (170) selects a parameter set {P.sub.i } using from control words C(k) stored in the memory (300). Data queues can simultaneously be transmitted to two or more peripheral devices (120-1, 120-2, 120-3).

Abstract: A method and computer program product are provided for paging control using a reference structure in a computer system. The reference structure is scanned to identify a next selected entry for an IO range building routine. The next selected entry is compared with a set hardlimit value. Responsive to the next selected entry being greater than the hardlimit value, the IO range building routine is exited. A shortlimit value is identified. The next selected entry is compared with the identified shortlimit value. Responsive to the next selected entry being greater than the identified shortlimit value, the IO range building routine is exited. A first array is used for storing entry IDs for selected entries found from scanning the reference structure and a second array is used for tracking blocks of storage used for the selected entries.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.

Abstract: A method of controlling a parallel port for connecting multiple devices is disclosed. The method controls the connection between a computer and one of the peripheral devices by way of using the different on-line codes corresponding to the peripheral devices respectively. Further, a common off-line code is set and shared by all peripheral devices. When the off-line code is sent out, all peripheral devices are disconnected from the computer, and the control status of the previous on-line device is backed up for the use of recovering the previous on-line state. Furthermore, a parallel port for connecting multiple devices is also proposed to incorporate with the controlling method such that the computer can switch the on-line state between an on-line peripheral device and the other peripheral standby devices.

Abstract: A high performance peripheral interface device is coupled to a computer via a computer bus and is coupled to a peripheral via a peripheral bus. To speed accessing of consecutively addressed data (the nth datum and the n+1th datum) from the peripheral, the interface device reads the n+1th datum from the peripheral: 1) before the computer has requested the n+1th datum from the interface device, and 2) while the computer is accessing the nth datum from the interface device.

Abstract: A memory device with a small computer system interface reads and writes mass data at high speed. The memory device includes a plurality of flash memories and a control circuit for allowing the flash memories to write and read data by page and to erase the data by block.

Abstract: A data processing system, integrated circuit device, program product, and method thereof utilize a service interface to provide external access to a plurality of cores integrated into an integrated circuit device. The service interface, which may be utilized to perform external data transfer through a service access port in connection with a predetermined service operation, is separate from any function interface that is utilized during regular operation of the device. The service interface includes a plurality of core interface units integrated with selected cores on the device and coupled to the service access port through a master interface unit that is configured to request at least one of the core interface units to initiate execution of a predetermined service operation.

Abstract: An apparatus for and method of implementing a novel buffer based full duplex communication system is disclosed. The disclosed invention is particularly useful in native signal processing systems wherein heavy contention of processor resources typically exist, such as in systems running multi-tasking operating systems. The communication system of the present invention includes a receiver, transmitter, echo canceler, CODEC and telephone hybrid. The major components of the system operate on a buffer of input samples consisting of a set of input bits. The communication system operates to generate a buffer of output samples consisting of a set of output bits. The invention utilizes a novel buffer switching mechanism to optimize the tradeoff between processing response time, on one hand, and robustness to interrupt latency and processor implementation on the other hand.

Abstract: A method and apparatus for handling outgoing communication requests in an information handling system in which outgoing communication packets are accumulated into a block that is written to an input/output (I/O) device. For each I/O device there is generated a blocking factor representing a predetermined number of packets that are accumulated before the block is written to the I/O device, as well as a push interval representing a maximum period of time for which any packet in the block can be stalled. Upon the arrival of a new outgoing packet, the packet is added to the block, and the block is written to the I/O device if either the block now contains the predetermined packets or any packet in the packet has been waiting for more than the push interval. A timer running asynchronously with the arrival of outgoing requests periodically pops to write the block to the I/O device if it has been waiting overlong, even if no new requests have arrived.

Abstract: In a contactless memory card system, a means is provided for sending a transmission wait request signal to the memory card when yet-to-be-passed received data remains in both the serial data receiving circuit and received data buffer via an electromagnetic coupling interface section, thereby preventing overrun errors even when the reading by a microcomputer of reader/writer received data is slow.

Abstract: A three port FIFO buffer circuit uses off the shelf static RAM and dedicated shallow, e.g. 16 word, FIFOs in a multi-level caching scheme. The circuit results in multiple, reconfigurable, deep (e.g. up to 32k word) FIFO buffers. The preferred embodiment of the invention provides a buffer that comprises a bank of 32k word RAM, six dual port 16-word FIFOs, and associated sequencing logic. The sequencing logic includes RAM address registers/counter associated with each of the six FIFOs, and manages the movement of data into and out of the RAM.