Abstract: According to the present invention, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is disclosed. The memory controller includes N page status registers each of which includes four page timers such that each of the page timers store a period of time between a last issued command to the particular page and a predicted next access to the memory, wherein the next access to the same page can be “close”, “open”, “write” or “read”. An incoming new command is received and it is then determined how long a particularly page access has to wait before the issue. An appropriate contents of a command timing lookup table is selected by the new command. A new time value is written into appropriate page timers that has to be inserted between the new command and a possible next access to the same page.

Abstract: The present invention combines features of an executable process with the need for multiple application programs to share a single input device. The present invention provides an executable program implemented as a process that allows multiple applications to communicate with a single input device. This is achieved by loading the input device control executable program as a process. The executable program is a server thus allowing multiple application programs to interface with the same input device. The multi-instance input device control (MIIDC) executable program responds to each application program request as if the input device is open for the calling application program. Each application program is thus enabled to communicate with the input device instance without interrupting the operation of other application programs communicating with the input device. The input device instance keeps track of all the connections to it and multiplexes and resolves conflicting requests.

Abstract: A keyboard is programmatically adapted to enable an application in a run time environment to distinguish operator keys (ALT/CTRL), not otherwise recognizable on a standard keyboard and special keys not otherwise recognizable on a non-standard keyboard by the application, when actuated. In one embodiment, a native Dynamic Link Library (DLL) is created in memory to capture the keystroke stream and maintain state information about the keyboard. A Java Native Interface (JNI) is created in the DLL and provided to a Java application. At initialization time, the Java application loads the native DLL with extended program instructions relating to key recognition in its static constructor. The Java application receives notification when an ALT or CTRL key is actuated. At that time the Java application calls the native DLL to receive the extended program instruction to determine whether the right or left ALT or CTRL key was actuated.

Abstract: A stream of data words is sent from a memory thru a controller and an external data buffer to an I/O device by a method which includes the steps of: 1) transferring a segment of the stream of data from the memory into the controller while concurrently sending a subsegment of the segment from the controller thru the data buffer to the I/O device via a transmission burst in which the receipt of individual parts of the subsegment are not acknowledged by the I/O device; 2) receiving a signal in the controller from the I/O device at any time during the sending step, to terminate the transmission burst; 3) subsequently receiving a signal in the controller, from the I/O device, to restart the transmission burst beginning with a selectable part of the last subsegment that was sent; 4) removing from the controller, only the portion of the segment which precedes the selectable part of the subsegment; and, 5) repeating the above steps until the stream of data is received in its entirety by the I/O device.

Abstract: A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage means, comprises a plurality of channel processors for conducting a data-input-and-output process to the data storage means in correspondence with a command contained in data (a frame) sent from the host processing device through the channel, and a channel processor, among the plurality of channel processors, is assigned for executing the data-input-and-output process for the data (frame) according to a type of command contained in the data (frame). Thus, the storage control device of the present invention can use the full-duplex channel efficiently.

Abstract: In a heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems, an I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least one disk connected to the I/O subsystem B in a magnetic tape library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: In a data transmission apparatus, a list generator produces a list of auxiliary information by appending a corresponding ID code to each item of the auxiliary information, based on a table of the ID codes previously assigned to the items of the auxiliary information, to thereby access a desired auxiliary information content in the list with reference to the ID code appended thereto.

Abstract: A need to store data between a producing stage and a consuming stage commonly arises in digital processing applications. However, factors such as fabrication process limitations and circuit area constraints may restrict the amount of available storage. A novel method and apparatus for data buffering are disclosed which use less data storage than would be required by double buffering techniques.

Abstract: An intelligent bus listening device, and a method which may be implemented as a computer program product, listens to SCSI commands on a first SCSI bus of a SCSI system via a listening connection to the first SCSI bus. The listening device is separately coupled via an interface to a second bus for communicating commands onto the second bus. A processor is coupled to the listening connection and to the second bus interface, the processor receiving the first commands from the first SCSI bus, converting the first commands to second commands related to the first commands, and providing the second commands to the second bus interface.

Abstract: A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Abstract: An open network system for supporting input/output (I/O) operations for non-standard I/O devices are disclosed. The system includes a server coupled to a plurality of I/O devices through an open network and an extended open system protocol that supports communication with devices that are not personal computers (PCs). These devices include magnetic stripe readers, check readers, smart card readers, credit card terminals, screen phone terminals, PIN pads, printers, and the like. The extended open network protocol includes tags which identify device and input operations and attributes which identify the location, data exchange method, and data variable names for the retrieval, acquisition, and submission of data between the server and I/O devices. Preferably, the open network protocol is implemented in a Hyper Text Transport Protocol (HTTP).

Abstract: A request interface device and method for operating the device and its components are described. The request interface device comprises a bus interface unit (BIU) and a requesting device. The requesting device generates a transfer request for data or command information, along with state information determining the manner in which the requester will transfer the data or command information associated with the request once the transfer request is granted. The transfer request and the associated state information are sent to the BIU, freeing the requester to generate new requests wile the first transfer request is waiting to be granted. The transfer request and associated information is stored in a queue within the BIU while the BIU logic gains access to the host bus.

Abstract: A serial communication system, which can improve a communication speed even when it takes long time to perform a process in accordance with a command. A serial communication apparatus includes a first and a second microcomputer, each of which has a relationship of a master/a slave. Each of the first and the second microcomputer has a CPU, a ROM, a RAM, a communication control portion, a serial communication block and so on. A serial communication clock (SCLK) is continuously sent from the first microcomputer to the second microcomputer. The serial communication block of each of the microcomputers has a pair of exchangeable shift registers. Each of the communication control portions reads a signal (SRXD) sent from the opposite side microcomputer by 16 clocks, and performs processes based on a process command in the read signal (SRXD) during the next 16 clocks.

Abstract: A Transfer Progress Alert Module and a method for optimizing processing of a data transfer load, in a data communication system is provided. The data transfer load is divided in individual data blocks. The device and method simultaneously perform pipelined operations on different individual data blocks, thus optimizing the overlap of pipelined operations. The method includes initializing the transfer by selecting a pre-defined individual data block size and determining a key for selecting and monitoring transfers with transfer addresses within a pre-determined address region. The method then continuously repeats following steps until all monitored individual data blocks from the data transfer load are processed. First, the incoming individual data blocks are transferred on a bus between a peripheral device and a memory, and the Transfer Progress Alert module is used for monitoring the individual data blocks having transfer addresses determined to belong in the pre-determined address region.

Abstract: The present invention has as an object thereof to efficiently execute a plurality of I/O commands in a secondary storage device. The tags of the I/O commands which are issued from a data processing device to a secondary storage device comprise the tag A part and the tag B part. The same value is attached as the tag A part to a group of I/O commands which are to be executed in a continuous manner. Values of the tag B parts are provided in order to distinguish I/O commands having the same value of the tag A part. In the secondary storage device, when an I/O command is received from the data processing device, when it is shown by the tag B part that the I/O command is the first command in an I/O command group, or alternatively, when an I/O command having the same tag A part value is not stored in the queue, the I/O command received is added to the final end of the queue.

Abstract: A memory LSI with compressed data inputting and outputting function provides reduction of data transfer amount and whereby to expand effective passband width with restricting transfer loss upon transfer of variable length compressed data. Data size detection circuit detects a size of a compressed data input from an external device on the basis of a compression information added to the compressed data and indicative of a size of data after compression. A data input and output circuit and an instruction decoder are operated for a period necessary for writing operation to write in the compressed data in a memory cell array. The data size detection circuit detects size of the compressed data held in the memory cell array on the basis of the compression information upon reading out to operate the data input and output circuit and the memory cell array for a period necessary for reading operating to read out compressed data to the external device.

Abstract: Signals are transmitted through a plurality of transmission channels, each including at least a pair of signal lines for transmitting an interface signal, between a transmitter and a receiver. A predetermined signal is modulated by a modulator with a high-frequency signal, and the modulated signal is provided to a signal line of one of the plurality of transmission channels. A demodulator receives the modulated signal transmitted via this signal line, and demodulates the modulated signal from the signal line based on the frequency of the high-frequency signal. According to the above-described configuration, an interface control method and apparatus which can newly exchange other data and control signals while conforming to existent interface specifications are provided.

Abstract: A method for transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data. Each of a plurality of devices within the computer system responds to the request and indicates the location of the device and whether the device contains the requested data. The data is then transferred to the requesting device from one of the devices containing the data within the plurality of devices to the requesting device. The device selected to transfer the data to the requesting device has the closest logical proximity to the requesting device which results in a quick transfer of data.

Abstract: A method and apparatus for providing mirroring of off-line storage data in a computer system. In one embodiment of the present invention, a computer system includes an application program, a plurality of storage devices, at least one storage driver that provides an interface between the application program and the plurality of storage devices, and a mirror driver that receives an I/O request from the application program requesting access to one of the plurality of storage devices, duplicates the I/O request to create a plurality of I/O requests, and sends the plurality of I/O requests to the storage driver so that each of the plurality of storage devices receives and processes one I/O request. In embodiments of the present invention, the computer system further includes a mirror application that communicates with the mirror driver to establish mirror sets of the plurality of storage devices.

Abstract: An initiator holds commands corresponding to ORBs issued to a target in an I/O request queue until it receives a completion response from the target. The target has read and write execution agents, and processes commands from the initiator. When a connection between the initiator and target is disconnected, and is connected again, the initiator deletes all ORBs, and generates and issues ORBs again to the target on the basis of the commands held in the I/O request queue. Upon processing an ORB, the target holds an identifier of the ORB whose processing is in progress, and the address of a buffer which is undergoing a read or write. After re-connection, the target compares the held identifier with the identifier of an ORB re-issued by the initiator. If the two identifiers match each other, the target restarts the read or write from the held address.

Abstract: In a computer system including one or more hosts coupled via a host bus to each other and a cached host memory, an Input/Output processor providing data to peripheral devices and an I/O bus disposed between the hosts and the Input/Output processor for transfer of information therebetween, an inbound queue structure receives message information from one of the hosts, and an outbound queue structure sends message information from the I/O processor to one of the hosts. Each of the queue structures comprises a pair designated as a free-list buffer and a post-list buffer. The free-list buffer of the inbound queue structure and the post-list buffer of the outbound queue structure are locally coupled to the hosts so that message information transfers between these two buffers and the hosts without incurring I/O bus read operations.

Abstract: A method of transferring file of the present invention by the two simultaneous data transmissions comprises the steps of transmitting data in a forward direction starting from a first specified position to a bottom in the file, and transmitting data in a backward direction starting from a second specified position to a top in the file. And a method of transferring file in FTP of the present invention comprises the steps of establishing a control connection, establishing multiple data connection, dividing a file into segments from each arbitrary point in the file, transferring segments through each of the multiple data connections, respectively, and synthesizing file from the segments transferred through the multiple data connections.

Abstract: A digital signal processor and digital signal processing method are provided, which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled data in a manner corresponding to respective kinds of signal processing with a small amount of hardware even in the case where the manner of storing and reading sampled data to be processed with respect to a memory device is different between the plural kinds of signal processing. A storage device stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing. A counter updates a count value thereof every sampling period and generates the updated count value as a basic address.

Abstract: A low-level portion of the operating system of a computer system is separated from an intermediate-level portion of the operating system. The low-level portion, including hardware-specific code, is stored in a relatively small read-only memory (ROM), while at least part of the intermediate-level portion is stored as a compressed ROM image on a disk or other mass storage device, which may be located remotely from the computer system. Upon power-up or reset of the computer system, the code in the ROM is executed to read the compressed ROM image into random access memory (RAM) of the computer system. The compressed image is then decompressed and executed as part of the boot sequence. Once decompressed, the portion of RAM storing the intermediate-level code is write-protected in the memory map, and the code in boot ROM is deleted from the memory map. Memory space in RAM that is allocated to the intermediate-level code but not used is returned to the operating system for use as part of system RAM.

Abstract: Processing circuiter 100 is provided having a passive data transfer capability. Processing circuitry 100 includes a bus 116, a first subsystem 105 coupled to bus 116 through first passive transfer logic 120a, and a second subsystem 108 coupled to bus 116 through second passive transfer logic 120b. Processing circuitry 100 further includes control circuitry 101/103 coupled to bus 116 for initiating a passive data transfer between first and second subsystems 105 and 108, first and second passive transfer logic 120a and 120b there after controlling exchange of data between the first and second subsystems 105 and 108 independent of the control circuitry 101/103.

Abstract: A portable music player computational device having a digital signal processor, for processing information, and a microcontroller connected to the digital signal processor by an electronic bus, one or more semiconductor memory devices connected to the digital signal processor by a second electronic bus, where the microcontroller controls the transfer of electronic information to and from one of said memory devices, one or more input sources connected to said microcontroller, said input sources providing information for the operation of said music player, one or more output devices connected to said digital signal processor where said microcontroller controls the transfer of electronic information to one or more of said output devices.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: The present invention provides fiber channel networks the ability to logically disconnect without closing an exchange pair wherein the control unit signals the channel that the channel can elect to keep the exchange open by sending the channel a status command. A preferred status command to permit the channel to keep the exchange open includes an End Connection=‘0’ with Channel End=‘1’ and device end=‘0’.

Abstract: A plurality of state machines arranged into three functional units, an Upper Machine, Middle Machine and a Lower Machine facilitate movement of user data between a buffer memory and a Global Memory (GM) in a data transfer interface. The Middle Machine controls all data movement to and from the GM. Although not directly in the data path, it is responsible for coordinating control between elements that comprise data transfer channels. The Middle Machine is interconnected to and provides control and coordination between the Upper and Lower sides of the buffer memory. The Lower Machine connects to a data assembly mechanism of each pipe. The Upper Machine connects to the backplane, which in turn connects to Global Memory. The actual data transfers between the buffer memory and GM are controlled by the Upper Machine, and transfers between the buffer memory and the data assembly mechanism are controlled by the Lower Machine.

Abstract: A high-speed memory system is disclosed for use in supporting a directory-based cache coherency protocol. The memory system includes at least one data system for storing data, and a corresponding directory system for storing the corresponding cache coherency information. Each data storage operation involves a block transfer operation performed to multiple sequential addresses within the data system. Each data storage operation occurs in conjunction with an associated read-modify-write operation performed on cache coherency information stored within the corresponding directory system. Multiple ones of the data storage operations may be occurring within one or more of the data systems in parallel. Likewise, multiple ones of the read-modify-write operations may be performed to one or more of the directory systems in parallel. The transfer of address, control, and data signals for these concurrently performed operations occurs in an interleaved manner.

Abstract: A network multifunction peripheral server permits simultaneous processing of print and scan jobs from one or more networked clients. The server of the invention connects to a network through a network interface unit, preferably capable of communication via a plurality of predetermined network protocols. It includes one or more ports for connection to a multifunction peripheral through a communication link. Separate print and scan data flows are established for each port by the server. The server also establishes separate logical channels to the port through a protocol which allows multiple logical channels per communication link. Print and scan jobs are handled simultaneously for a single multifunction peripheral through separate print and scan data channels logically established by the server.

Abstract: An interface between a network communication card and an industrial controller allows rapid asynchronous buffering using two buffers and two associated registers for each data direction. A reading of the buffers is proceeded by an attempt to copy from the write designation register to the read designation register checking the equality of the register values and then reading from the buffer designated by their common value. Conclusion of the reading sets the write destination register to zero. Writing of the buffers is proceeded by a checking of the read designation register for zero value and then writing to other than the last buffer indicated by the write designation register. If the read designation register is non-zero, then the writing occurs to the opposite buffer of that in the read designation register. The write designation register is then updated to indicate the buffer written to.

Abstract: A computer has one or more different device drivers, and one or more different devices are connected through respective device drivers. The devices to be connected include a storage device or an information processing device. In the computer, a file inside or outside of the computer is accessed in response to an access request generated inside. In the computer, based on data type of the file, which one of the device driver is to be used for the delivery of the file is determined. When a device driver used for the delivery of the file is specified among one or more device drivers as a result of determination, the file is transferred through the specified device driver to the unit connected to the device driver. Therefore, when a file is accessed in response to a request generated in the computer, the accessed file is automatically transferred and delivered to that device which requires the file, among one or more devices connected to the computer.

Abstract: A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory and transmitted in a weakly ordered fashion over a bus to a graphics device. The graphics device reorders the incoming data into the same order as which the data was written into the contiguous region of system memory, thereby allowing the use of order dependent encoded commands with the weakly ordered bus interface.

Abstract: The present invention is related to methods and systems for context switching within a disk controller, allowing controller processors to efficiently switch between multiple tasks. In a first mode, a first memory is used to temporarily store data being transferred between a disk storage device coupled to the disk controller and a bus coupled to the disk controller. The transfer is managed by a disk controller processor. A first context is stored in a second memory coupled to the disk controller processor. In a second mode, the first memory is used to store a second context for later use by the disk controller processor. At least a portion of the first context information stored in the second memory is swapped with at least a portion of the second context information stored in the first memory at least partly in response to a first event. The swapped portion is then swapped back to the second memory in response to a second event.

Abstract: A system and a method to transfer data between a host computer and a storage device. The storage controller architecture is organized into its functional modules based on whether a module primarily performs a control function or a data transfer function. The data paths that connect various functional units (for example, switching unit, parity logic, memory module, etc.) may then be sized to the required bandwidth. This effectively makes the iops (I/O operations per second) and bandwidth capability of a storage controller scalable independently of each other. A data transfer command from a host computer is decoded and translated into one or more data transfer commands by the control module in the storage controller. The control module then sends a list of translated commands to the host. Parity calculation, caching, one or more RAID levels and other relevant data transfer information may also be included as part of the translated set of commands.

Abstract: The present invention is a method and apparatus for performing a multimedia function. A data port receives the input data. A shared memory is coupled to the data port for storing the input data. A multimedia syntax is coupled to the shared memory for processing the input data based on a configuration information. The multimedia syntax corresponds to the multimedia function.

Abstract: A method and circuit for controlling a FIFO buffer such that the buffer can accommodate more than one data block simultaneously without overlapping data between adjacent data blocks. The FIFO buffer has a read-pointer address register and a write-pointer address register and a bank of write-capture registers including at least a first pair and a second pair. The first pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a first data block written to the FIFO buffer register while the second pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a second data block written to the FIFO buffer. The first pair and second pair alternate in capturing and saving beginning and ending addresses of a plurality of data blocks written to the FIFO buffer.

Abstract: An output data path scheme including a feedforward portion may be configured to drive a data signal from a selected local bus line onto a global bus and a feedback portion may be configured to drive the data signal from the global bus onto a deselected local bus line. A first sense amplifier may be configured to drive the data signal onto the selected local bus line. A second sense amplifier may be coupled to the deselected local bus line and may be configured to tristate.

Abstract: An open network system for supporting input/output (I/O) operations for non-standard I/O devices are disclosed. The system includes a server coupled to a plurality of I/O device through an open network and an extended open system protocol that supports communication with devices that are not personal computers (PCs). These devices include magnetic stripe readers, check readers, smart card readers, credit card terminals, screen phone terminals, PIN pads, printers, and the like. The extended open network protocol includes tags which identify device and input operations and attributes which identify the location, data exchange method, and data variable names for the retrieval, acquisition, and submission of data between the server and I/O devices. Preferably, the open network protocol is implemented in a Hyper Text Transport Protocol (HTTP).

Abstract: A system and method for communicating with a serial communications device using multiple virtual ports. The multiple virtual ports are mapped to device names using a port router. The virtual ports are accessed to provide a communications port, or to provide a command/status port for accessing status and performance information about the communications device. The virtual ports may be used to establish a communications connection and, concurrently, to run a second application that monitors the communications speed. The communications speed may be displayed to the user in real-time.

Abstract: Data having a small amount of data, such as still image data, is transmitted by using asynchronous packets. A source apparatus writes data which can be selected from a data source block into a data descriptor within a memory. Then, the source apparatus transmits the data read from the data descriptor to a receiver apparatus by using asynchronous packets. The receiver apparatus can also write data which can be selected from the data source block into a data descriptor within a memory.

Abstract: In a wireless and/or wireline communications system (100), a method (400-536) and apparatus (200) for minimizing an amount of data (300) communicated between a source device (107, 108, 112 or 114) and a destination device (107, 108, 112 or 114) in order to modify an electronic document stored at said destination device. Said method and/or apparatus employs method steps and apparatus structure for editing a version of the electronic document stored at the source device via a set of input commands to create an edited version of the document. Thereafter, the set of input commands are transmitted to the destination device in order to modify the version of the electronic document stored at the destination device when the set of input commands are smaller in size than edited version of the document.

Abstract: Signals are transmitted through a plurality of transmission channels, each including at least a pair of signal lines for transmitting an interface signal, between a transmitter and a receiver. A predetermined signal is modulated by a modulator with a high-frequency signal, and the modulated signal is provided to a signal line of one of the plurality of transmission channels. A demodulator receives the modulated signal transmitted via this signal line, and demodulates the modulated signal from the signal line based on the frequency of the high-frequency signal. According to the above-described configuration, an interface control method and apparatus which can newly exchange other data and control signals while conforming to existent interface specifications are provided.

Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations.

Abstract: The present invention relates to an ATM-LAN(Asynchronous Transfer Mode-Local Area Network) switch, and in particular to an information transferring apparatus between processors of the ATM-LAN which is capable of efficiently performing an information transfer between a plurality of processors which perform an information transmission and receiving operation through a backplane based on the Ethernet protocol. The information transfer apparatus between processors of an ATM-LAN switch according to the present invention is capable of implementing an efficient information transfer between processors by providing a backplane sub-board for thereby checking an information transfer state between the processors without using a large number of devices for an Ethernet communication. In addition, it is possible to enable a stable information transfer between processors in the case of a hot swap and dual operation by providing a control logic to the backplane sub-board.

Abstract: A system for transferring game saves between a game console and a personal computer. The system includes a game save editor that allows a user to edit game saves stored in memory of a computer. The game save may be obtained from a hard disk of a personal computer or a memory card in a game console.

Abstract: In a write process of compressed data #1, data transfer for one sector from a CPU to an HDD, and a local write for one sector by the HDD repeat themselves for 256 sectors. During the write process period, the system BIOS compresses data of the next data block by utilizing the period in which a local write is made by the HDD. That is, upon completion of data transfer for one sector, the system BIOS waits for completion of the local write for one sector by the HDD, and then transfers the next data for one sector. During that local write completion wait period, the system BIOS compresses the next data.

Abstract: A computer comprises a medium drive configured to reproduce data recorded in a video recording medium and an audio recording medium. When a reproduction switch is turned on if the computer is not powered, it is determined whether the video recording medium or the audio recording medium is loaded. If the video recording medium is loaded, the operating system is activated and the reproduction application is also activated.

Abstract: A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for controlling access to the memory; and at least one data buffer for buffering data to be written to or read from the memory. A burst controller is provided for issuing burst instructions to the memory access controller, and the memory access controller is responsive to such a burst instruction to transfer a plurality of data words between the memory and the data buffer in a single memory transaction. A burst instruction queue is provided so that such a burst instruction can be made available for execution by the memory access controller immediately after a preceding burst instruction has been executed.