Abstract: A method and apparatus for a mutiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of mutiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).

Abstract: A controller is presented comprising one or more initiators coupled to one or more targets via a transaction bus and a corresponding number of data busses. The initiator(s) receive transaction requests from external logic, buffer the transaction and assign it a unique identifier, which is passed to an appropriate target via the transaction bus. The targets receive and queue the unique identifier until it can process the transaction, at which time it prompts the initiator to provide it the buffered transaction via a data bus dedicated to the target.

Abstract: A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data block from the source destinations; (B) writing the data block to a first of the plurality of destinations; and (C) writing the data block to a second of the plurality of destinations. Addresses of the first and second destinations are previously stored.

Abstract: A system and method for using a switch to route graphics data and data for a peripheral data on an interconnect is disclosed. A graphics card includes a switch that is communicatively coupled to a computer system. The switch receives graphics data and data for a peripheral device from the computer system via a first link. The switch routes the data for a peripheral device to a console via a second link and routes the graphics data to a graphics controller via a third link. The graphics controller forms a part of the graphics card and is communicatively coupled to the switch via the third link, wherein the graphics controller generates a video signal to drive a video display.

Abstract: The data processor for processing operation data stored in a memory connected to an external bus in the order of operations includes: an interface section for holding a parameter required for transfer of the operation data; an operation section receiving the operation data from the interface section for performing predetermined processing; and an operation memory for storing the operation data transferred. The interface section sequentially transfers the operation data from the memory connected to the external bus to the operation memory using the parameter, and sequentially transfers the operation data from the operation memory to the operation section.

Abstract: A method and system for flexibly and efficiently assigning channel path identifiers (CHPIDs) used by operating system software in computer systems to identify the communication path to I/O devices via channels. To avoid wasted CHPIDs, which may be limited in number, CHPIDs are assigned only to channels which are installed on and configured to the computer system. The CHPIDs may be re-assigned concurrently with ongoing system operations via a user interface and/or an imported, pre-defined CHPID mapping.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Abstract: A direct memory access control system supplies the respective status signals indicating timings of the read data effective state or writable state between the input/output interface and memory interface, both interfaces maintain the read data effective state and writable state of the input/output memory and synchronous memory under control until the later timing comes up. Consequently, it is possible to match the read data effective timing and writable timing of the synchronous memory and input/output memory, thus making possible flyby transfer of data between both memories.

Abstract: An architecture for data retrieval from a plurality of coupling queues. At least first and second data queues are provided for receiving data thereinto. The data is read from the at least first and second data queues with reading logic, the reading logic reading the data according to a predetermined queue selection algorithm. The data read from by reading logic and forwarded to an output queue.

Abstract: The present invention provides an improved method and system for link detection and handling. The method includes detecting one of the plurality of link sectors; generating an interrupt signal; determining a buffer method selection; buffering the plurality of data sectors only, if a link skip buffer method is selected; and buffering the plurality of data sectors and the plurality of link sectors, except for a link block, and allocating a sector in a buffer for the link block, if a link buffer method is selected. The present invention provides a hardware approach to link sector detection and handling. Instead of passing the data to a system software prior to link sector detection, the method and system in accordance with the present invention performs the link sector detection in the controller hardware. When the controller detects the link sectors, it automatically either skips or buffers the link sectors depending upon the configuration of the controller.

Abstract: A method for flow control by a SCSI system using a Packetized SCSI Protocol includes transferring a data packet information unit in a Packetized SCSI Protocol Data Out phase between a SCSI initiator and a SCSI target over a SCSI bus. The method also includes generating a signal on said SCSI bus by said SCSI target in said Packetized SCSI Protocol Data Out phase to indicate whether another data packet information unit is to be accepted in said Packetized SCSI Protocol Data Out phase by said SCSI Target.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A buffer circuit for a peripheral interface circuit in an I/O node of a computer system. A buffer circuit includes a first buffer and a second buffer. The first buffer may be configured to store a plurality of selected packet commands within a plurality of storage locations. The second buffer is coupled to the first buffer and may be configured to store a plurality of index values. Each index value corresponds to one of the storage locations in the first buffer. The buffer circuit further includes a write logic circuit that is coupled between the first buffer and the second buffer. The write logic circuit may be configured to successively read each of the plurality of index values from the second buffer and to cause a selected packet command to be stored in each storage location corresponding to each of the plurality of index values within the first buffer.

Abstract: A buffer circuit for rotating outstanding transactions. A buffer circuit includes a buffer and a command update circuit. The buffer may be configured to store packet commands that belong to a respective virtual channel of a plurality of virtual channels. The packets may be stored in the buffer to await transmission upon a peripheral bus. Once a given packet is selected for transmission, a peripheral bus cycle corresponding to the given packet command may be generated upon the peripheral bus. The command update circuit may be configured to generate a modified packet command in response to receiving a partial completion indication associated with the peripheral bus cycle. The command update circuit may also be configured to cause the modified packet command to be stored within the buffer.

Abstract: A data transfer control system receives a command packet ORB (SBP-2) transferred through a bus BUS1 (IEEE1394), and issues a command included in the ORB to a device connected with a bus BUS2 (ATA (IDE)/ATAPI). The data transfer control system sets a sufficiently large fixed DMA data length irrespective of the type of the issued command, and instructs start of DMA transfer to or from the device connected with the bus BUS2. The data transfer control system aborts the DMA transfer when a device connected with BUS2 informs of completion of command processing. As the fixed DMA data length, a value greater than a storage capacity of a storage or a value greater than a data length which can be designated by a command is employed. The data transfer control system issues a command included in the ORB to a device connected with the bus BUS2 without decoding the command.

Abstract: A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.

Abstract: The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst clock. Command capture logic receives command information in response to the system clock. A storage element is responsive to the command capture logic for storing certain command information such as write commands. A two stage pipeline receives the command information from the storage element in response to the burst clock and outputs the command information in response to the system clock. Methods of operating the apparatus are also disclosed.

Abstract: A semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read out data; a read address decoding means for independently decoding an address of a read memory cell in response to a read address; a write address decoding means for independently decoding an address of a write memory cell in response to a write address; a data reading means for reading data of a memory cell addressed by the read address decoding means; a data writing means for writing data to a memory cell addressed by the write address decoding means; and an address delay means by which a write address decoded by the write address decoding means is delayed by a predetermined time from a read address decoded by the read address decoding means, wherein the predetermined time is set as a predetermined plurality of times of basic synchronization pulse periods so that the data read modify write operation is accomplis

Abstract: An open network system for supporting input/output (I/O) operations for non-standard I/O devices are disclosed. The system includes a server coupled to a plurality of I/O devices through an open network and an extended open system protocol that supports communication with devices that are not personal computers (PCs). These devices include magnetic stripe readers, check readers, smart card readers, credit card terminals, screen phone terminals, PIN pads, printers, and the like. The extended open network protocol includes tags which identify device and input operations and attributes which identify the location, data exchange method, and data variable names for the retrieval, acquisition, and submission of data between the server and I/O devices. Preferably, the open network protocol is implemented in a Hyper Text Transport Protocol (HTTP).

Abstract: The object of the present invention is to speed up data transfer between processes required when there is a variable duplicatively assigned to a plurality of processes (duplicatively assigned variable) and any process among the plurality of processes substitutes data into the duplicatively assigned variable. In a distributed memory type parallel computer for executing a plurality of processes using a plurality processing devices connected via a communication network, each of the processing devices for executing at least one process among the plurality of processes comprises a scheduler for scheduling data transfer of the substituted data to each process if the process substitutes data into a variable a duplicatively assigned throughout the plurality of processes, and transfer means for carrying out data transfer via the communication network in accordance with the scheduler. Appropriate scheduling speeds up data transfer.

Abstract: The invention is directed to techniques that include an error detection code (e.g., a CRC code) and cleared bytes (e.g., zeroes) with data (e.g., CKD data). The use of cleared bytes with CKD data enables detection of corrupt CKD data by simply generating a CRC code based on an entire data block and comparing that generated CRC code with an initial CRC code appended to the CKD data within that data block. One arrangement of the invention is directed to a data storage system that includes a circuit having a memory pipeline that receives a stream of data elements, and provides a series of byte groups that includes the stream of data elements, an error detection code and a set of cleared bytes to a set of storage devices. Each of the series of byte groups provided by the memory pipeline has a same byte width. The inclusion of the error detection code and the set of cleared bytes enables consistent alignment of each byte group in the series.

Abstract: A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source port (460-461), a channel controller (410-412) and a destination port (460, 461). Channel to port buses (CP0-CP2) are representative of parallel buses that are included in the read address bus (RA). Similar parallel buses are provided for a write address bus and a data output bus, not shown. Port to channel buses (PC0-PC1) are representative of parallel buses that are included in data input bus DI. Scheduling circuitry (420, 421) includes request allocator circuitry, interleaver circuitry and multiplexer circuitry and selects one of the channel to port buses to be connected to an associated port controller (460, 461) on each clock cycle for providing an address for a transaction performed on each clock cycle.

Abstract: A low-level portion of the operating system of a computer system is separated from an intermediate-level portion of the operating system. The low-level portion, including hardware-specific code, is stored in a relatively small read-only memory (ROM), while at least part of the intermediate-level portion is stored as a compressed ROM image on a disk or other mass storage device, which may be located remotely from the computer system. Upon power-up or reset of the computer system, the code in the ROM is executed to read the compressed ROM image into random access memory (RAM) of the computer system. The compressed image is then decompressed and executed as part of the boot sequence. Once decompressed, the portion of RAM storing the intermediate-level code is write-protected in the memory map, and the code in boot ROM is deleted from the memory map. Memory space in RAM that is allocated to the intermediate-level code but not used is returned to the operating system for use as part of system RAM.

Abstract: A circuit and associated methods of operation for a standardized scatter/gather list processor component within DMACs and intelligent IOPs. The standardized circuit architecture and methods provide a register interface and associated processing capabilities to simplify firmware processing to save and restore context information regarding block transfer operations that are paused and resumed prior to completion. Furthermore, the invention provides for architecture and associated methods for processing of standard scatter/gather list elements by a standardized scatter/gather list processor embedded within DMACs and IOPs. Specifically, as applied in the context of SCSI or Fiber Channel IOPs, the scatter/gather list processor of the present invention simplifies IOP firmware processing to save the current block transfer context on occurrence of a SCSI disconnect and to restore the saved context on occurrence of a SCSI reselect.

Abstract: A single host adapter hardware I/O control block contains information used to specify a transfer of data from a first target device to a host system and in addition information that specifies whether the data is mirrored, and if so, identifies a second target device on which the data is to be read. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Abstract: The present invention provides a method for sharing I/O facilities among logical partitions. A remote translation control entry table is created on a hosted partition appearing to own a virtual copy of the I/O facilities to be shared. The remote translation control entry table on the hosted partition is loaded with data from a hypervisor in response to requests made by the OS running in the hosted partition. The hypervisor, in response to requests from the OS running in the hosting partition, copies the data from the remote translation control entry into a standard translation control entry table on the hosting partition owning the physical I/O facilities that target the I/O page buffers of the hosted partition to perform the desired I/O operation. The I/O page buffers of the hosted partition are accessed by the hosting partition's I/O facilities using the data stored in the standard translation control entry table.

Abstract: A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

Abstract: The invention relates to a Universal Serial Bus (USB) with two wireless communication hubs (USB hubs). One of these hubs is connected to a first host computer, and both USB hubs are connected to a plurality of I/O devices. Each USB hub includes a wireless adapter and an antenna connected to the wireless adapter. The wireless adapter of each USB hub comprises a transmitting/receiving unit for transmitting data via the antenna to the wireless adapter of the other USB hub or receiving data via the antenna from the wireless adapter of the other USB hub. The wireless adapter also comprises a wireless dual port, which is automatically configured upstream or downstream when the first host computer is connected to one of the USB hubs.

Abstract: A message processing scheme capable of realizing both a portability and a unified way of handling and managing e-mails of a given user is disclosed. The collective message processing and the unified message accesses are realized by storing and managing messages from a plurality of message delivery servers in the message processing device that is unique to the user. All mails destined to the user are collected at the message processing device regardless of a current location of the user, so that the user only needs to view mails on this message processing device.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up the data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction.

Abstract: A system for moving physically stored data in a distributed, virtualized storage network is disclosed. A group of data sets is written to a first storage device as part of a write operation such as migration. A plurality of storage devices partially filled with data are designated as substitutes. The write operation to the first storage device is suspended upon receiving a request to read a data set stored in the first storage device, such as occurs in a recall operation. A second storage device is then selected from the plurality of substitute storage devices. The write operation is continued by writing data sets from the group of data sets included in the write operation that were not written to the first storage device to the selected second storage device. The requested data is then read from the first storage device.

Abstract: A CPU unit writes a command for instructing a control CPU specified information for each I/O unit, each I/O unit decodes a command instructed by the CPU unit so as to determine whether or not it is information specified by the control CPU, and holds the corresponding information specified by the control CPU in the I/O unit, the CPU units issue commands for instructing the reset control to all the I/O units, and each I/O unit decodes the command instructing its reset control, and when it has determined that the corresponding command is instructed from the CPU unit of the controlling end, it follows the reset controlling instruction so that the resetting operation of the specific I/O unit on the system specified by the CPU unit is controlled.

Abstract: A system and method are disclosed which allow unstored computed results to be accessed without the normal overhead associated with traditional data forwarding and bypass techniques. Through the use of multiplexers and bi-directional OR controllers the unstored data is readily accessible for use before it is stored in a register file. The circuitry used also allows bi-directional travel across a register file or bank as information is passed between the bi directional controllers used. Latches can also be used in the circuitry. Additionally, the features of the invention allow the required number of select signals fed to the multiplexers used to be reduced over conventional methods. These reductions are possible through circuitry disclosed herein.

Abstract: Methods and systems for overlapping data flow within an extended copy command over a network, including, at a router in a network: receiving an extended copy command from a first host to a first target device; determining an initial network status if the network status is unknown; initializing a set of read-write parameters; and executing the extended copy command for a first segment of the extended copy command, and for one or more subsequent segments, by overlapping one or more read and one or more write commands of the extended copy command.

Abstract: A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Abstract: An initiator holds commands corresponding to ORBs issued to a target in an I/O request queue until it receives a completion response from the target. The target has read and write execution agents, and processes commands from the initiator. When a connection between the initiator and target is disconnected, and is connected again, the initiator deletes all ORBs, and generates and issues ORBs again to the target on the basis of the commands held in the I/O request queue. Upon processing an ORB, the target holds an identifier of the ORB whose processing is in progress, and the address of a buffer which is undergoing a read or write. After re-connection, the target compares the held identifier with the identifier of an ORB re-issued by the initiator. If the two identifiers match each other, the target restarts the read or write from the held address.

Abstract: A signal data receiving device for receiving data via a digital interface. The signal data receiving device has a receiving terminal data holding device for holding data concerning a state of a terminal via which data is received, and wherein the terminal state data includes terminal operating mode information. Suspend reasons concerning suspend in the operating mode information are classified using a receiving data state and a device operation state as classification criteria. These classifications and each classified suspend reason are capable of being displayed on another device connected to the digital interface.

Abstract: The present invention provides an apparatus and methodology that allows a host computer to control a data storage device that is remotely located relative to the host computer utilizing the same software that is used to control data storage devices that are locally or directly connected to the host computer. In one embodiment, a host computer is provided that includes a virtual adapter that is capable of converting unencoded SCSI command related information from an operating system into encoded SCSI command related information that is capable of being transmitted over a network to a remotely located SCSI data storage device, i.e., a SCSI data storage device that is separated from the host computer by more than the distance set forth in the SCSI specification. The virtual adapter is also capable of decoding encoded SCSI command related information received from a remotely located SCSI data storage device into unencoded SCSI command related information that is suitable for processing by the operating system.

Abstract: A technique for providing concurrent non-blocking access to a circular queue is provided. The concurrent non-blocking circular queue also may be configured such that cache-coherent requesters and a non-cache-coherent requester (e.g., software and hardware) both may concurrently access the queue. Further, the queue may be configured such that the probability of occurrence of the ABA race condition may be minimized.

Abstract: Several systems and methods are described for accessing one of multiple groups of peripheral devices. One of the systems includes a host system, multiple peripheral devices, and a host adapter. The peripheral devices are arranged to form multiple groups, each group including at least one peripheral device. The host system is coupled to the peripheral devices via the host adapter, and accesses the peripheral devices via the host adapter. The peripheral devices of each group receive a group access signal for controlling accesses from the host system. The host adapter includes a control register and signal routing logic. The signal routing logic is coupled to the control register and to each of the groups of peripheral devices. The control register stores a value for selecting one of the groups of peripheral devices. The host system may include a central processing unit (CPU) configured to write the value to the control register.

Abstract: An apparatus and method is disclosed for providing a user with task-specific information that includes a portable instruction system that may be worn by a user, and includes, a computer sufficiently lightweight and designed to be worn by a user to which a memory has been connected. The system includes a display device that can receive display signals from the computer for visual display to the user and an input device by which the user enters commands to the computer. An instructional program is provided that the computer accesses and stores in memory in response to a user command and displays information concerning a task to be performed by the user on the display device in response to commands from the user.

Abstract: An open network system for supporting input/output (I/O) operations for non-standard I/O devices are disclosed. The system includes a server coupled to a plurality of I/O devices through an open network and an extended open system protocol that supports communication with devices that are not personal computers (PCs). These devices include magnetic stripe readers, check readers, smart card readers, credit card terminals, screen phone terminals, PIN pads, printers, and the like. The extended open network protocol includes tags which identify device and input operations and attributes which identify the location, data exchange method, and data variable names for the retrieval, acquisition, and submission of data between the server and I/O devices. Preferably, the open network protocol is implemented in a Hyper Text Transport Protocol (HTTP).

Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.

Abstract: A data transfer apparatus includes a reception unit for receiving data from the first external device; a storage unit for storing the data received by the reception unit; an output unit for receiving data and outputting the data to a second external device; a retransmission request receiving unit for receiving a retransmission request signal from the second external device; and a transfer control unit for having a first transfer performed when the receiving unit has received data from the first external device, the first transfer transferring the data using direct memory access (DMA) directly to both the output unit and the storage unit in parallel, and having a second transfer performed when retransmission request receiving unit has received the retransmission request signal, the second transfer transferring data, which has already been stored in the storage unit by the first transfer, to the output unit.

Abstract: Systems, devices, and methods. A double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

Abstract: Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user.

Abstract: The present invention provides a method for fibre channel control units to execute commands locally when a channel sends a repeat execute indicator in conjunction with certain other field settings, wherein the control unit will repeat and chain control words until certain predefined conditions occur.

Abstract: An open network system for supporting input/output (I/O) operations for non-standard I/O devices are disclosed. The system includes a server coupled to a plurality of I/O devices through an open network and an extended open system protocol that supports communication with devices that are not personal computers (PCs). These devices include magnetic stripe readers, check readers, smart card readers, credit card terminals, screen phone terminals, PIN pads, printers, and the like. The extended open network protocol includes tags which identify device and input operations and attributes which identify the location, data exchange method, and data variable names for the retrieval, acquisition, and submission of data between the server and I/O devices. Preferably, the open network protocol is implemented in a Hyper Text Transport Protocol (HTTP).

Abstract: An accelerated filesystem includes a fast-path and a slow-path. The fast-path includes an enhanced storage controller and an enhanced network processing function. Uncontested READ and WRITE operations are processed on the fast-path. A READ session is initialized by obtaining file-storage metadata that is tagged with a session ID. The session ID is provided to the enhanced network processing function, and to the application as a file handle, and the tagged metadata is provided to the enhanced storage controller. Subsequent access is facilitated by communicating the file handle from the application to the enhanced network processing function, which passes the file handle to the enhanced storage controller in response. The enhanced storage controller executes a file handle to block list translation by employing the tagged metadata to retrieve the appropriate data. The retrieved data is transmitted to the application via the enhanced network processing function.