Abstract: A storage area network (SAN) fibre channel arbitrated loop (FCAL) multiple system, multiple resource, storage enclosure and a method are provided for performing enclosure maintenance concurrent with device operations. The storage enclosure includes a plurality of storage resources or storage devices, a plurality of IO adapters (IOAs) coupled to the storage area network and a pair of enclosure services node cards. Each enclosure services node card includes loop connections for the plurality of storage resources. Each enclosure services node card includes a respective global bus connection and a loop connection to each of the plurality of IOAs. Each enclosure services node card is used concurrently by the multiple systems to manage the plurality of storage resources. In the method for performing enclosure maintenance concurrent with device operations, identical maintenance procedures are implemented for the enclosure services node cards and the storage devices.

Abstract: A method and system enable cross connection of an incoming data stream to one or more outgoing data streams. Each data stream comprises respective incoming and outgoing frames. Each frame includes one or more rows, and each row comprises a respective plurality of data segments. A reserved memory space is provided having a data storage capacity equal to an integer multiple of a data segment and less than one complete row. A data segment of an incoming row of an incoming frame is written to the reserved memory space. Subsequently, the data segment of the incoming row is read to an outgoing row of an outgoing frame from the reserved memory space. The writing and reading steps are timed such that the data segment is read from the reserved memory space before being over-written by another data segment.

Abstract: Methods and apparatus are provided for transferring data words from a source to a destination. The apparatus includes a datapath buffer coupled by a first data bus to the source and coupled by a second data bus to the destination, write control logic for writing a first number of data words in the datapath buffer in response to a first source transfer condition and for writing a second number of data words in the datapath buffer in response to a second source transfer condition, and read control logic for reading the first number of data words from the datapath buffer in response to a first destination transfer condition and for reading the second number of data words from the datapath buffer in response to a second destination transfer condition.

Abstract: Two transfer modes of a band-guaranteed cycle and an event-driven asynchronous cycle are defined in a multimedia bus. In the band-guaranteed cycle, stream data is transferred between nodes in real time using a reserved band for each cycle time. Both a single-edge access and a double-edge access are provided for the stream data transfer in the band-guaranteed cycle, and it is possible to select one of the single-edge access and double-edge access for each data transfer between nodes. The transfer band of stream data on the bus can thus be expanded and the transfer efficiency of AV stream can be improved.

Abstract: A transparent latch (18) and a logic conditioning circuit (10) are disclosed. The transparent latch (18) receives signals from conditioning circuit (10), including a test input that indicates whether the transparent latch is in a testing mode or an operational mode. When the transparent latch (18) is in a testing mode, the transparent latch acts as a buffer or flow-through logic circuitry, permitting the logic circuitry that includes transparent latch (18) to be tested according to existing test methodologies. When the transparent latch is not in testing mode, the transparent latch (18) acts as a transparent latch (18), holding the state of the input when the clock signal is in a first state and allowing the input to propagate to the output when the clock signal is in a second state.

Abstract: A request interface device and method for operating the device and its components are described. The request interface device comprises a bus interface unit (BIU) and a requesting device. The requesting device generates a transfer request for data or command information, along with state information determining the manner in which the requestor will transfer the data or command information associated with the request once the transfer request is granted. The transfer request and the associated state information are sent to the BIU, freeing the requestor to generate new requests wile the first transfer request is waiting to be granted. The transfer request and associated information is stored in a queue within the BIU while the BIU logic gains access to the host bus.

Abstract: A bus architecture system is disclosed. The bus architecture system is formed within an integrated circuit device 30 having a communications port 34 configured to permit interface with electronics systems not illustrated. The port 34 connects to a communications module 32 forming part of a sequential bus arrangement incorporating a number of modules 36A-36E of the device 30 and a number of uni-directional interconnections 38A-38F arranged between sequential ones of those modules 36A-36E. The bus architecture system provides for the configuration of an ASIC prior to actual operation of the ASIC, and also for examination of the operation of the ASIC for debugging purposes.

Abstract: In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

Abstract: A server transmits an open command which orders to open ports when data is transmitted to terminals. The open command is formed with a plurality of bits so as to have flags corresponding to each port of the terminals. Among a plurality of the bits, only the bits corresponding to the ports to be opened are set to be, for example, 1 and the rest is set to be, for example, 0. In each of the terminals, each of the receivers receives the open command, and judges whether the bits corresponding itself in the open command is, for example, 1 or not. When the bit is 1, the terminal opens the port.

Abstract: A system and method that enhances overall computer system performance by implementing a secondary bus infrastructure to avoid data phase transaction latencies during primary bus information transfers. In accordance with an embodiment of the invention, the system includes a first bus, coupled to a host adapter and a plurality of media adapters, and a second bus, coupled to the host adapter and a select number of media adapters. The host adapter includes a host first bus controller, coupled to the first bus, and a host second bus controller, coupled to the second bus. Each of the media adapters contain a media first bus controller, coupled to the first bus, and a select number of media adapters contain a media second bus controller, coupled to the second bus.

Abstract: An integral USB MODEM/USB LAN card peripheral comprises a first connector connected to a computer; a second connector connected to a telephone line; a third connector connected to LAN; a USB controller used to collect and dispatch internet data; wherein the USB controller has a micro-controller connected to a first memory, and a USB SIE (serial bus interface engine) connected between the first connector and the micro-controller. The micro-controller is connected to a MODEM module and an ether network media access controller through an internal bus, wherein the MODEM module is connected to the second connector for accessing Internet; and the ether network media access controller connected to the third connector through a physical layer for accessing LAN. Therefore, the present invention enables a computer to access LAN and Internet simultaneously; and the remote users to share compute resource with other users.

Abstract: A modular electronic device has a cabinet frame, a plurality of push-in modules with module frames retained in the cabinet frame side-by-side, and printed circuit boards mounted in the module frames, and electronic components carried by said printed circuit boards. Each of these modules has autonomous data transmitting connections for communicating directly with each of the other ones of the modules.

Abstract: The present invention discloses a method and apparatus for processing a packet of data received by a first-in-first-out (FIFO). In one embodiment, a message in the packet of data is recognized. Based on a plurality of control bits encoded in the message, a delimiting condition in the packet of data is determined. An operation is performed which is responsive to the delimiting condition. The operation controls the transfer of the packet of data from the FIFO to a memory.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A method and apparatus for automatically configuring a configurable integrated circuit. One embodiment comprises a method for automatically loading data including configuration data to a configurable integrated circuit upon initialization of a system in which the configurable integrated circuit is embedded. The method of one embodiment comprises storing a plurality of commands and a plurality of data elements in a non-volatile memory of the system. The method further comprises reading contents of an initial address in the non-volatile memory. If the initial address contains a command, depending upon a type of the command, the method comprises writing contents of a next address in the non-volatile memory to a register space of the configurable integrated circuit, to a configuration space of the configurable integrated circuit, or to a command space of the configurable integrated circuit.

Abstract: The present invention relates to a method of transmitting data stream including multi-path data stream sections to a connected digital television. This data stream transmitting method checks the number of maximum multiple paths of data streams recorded in a recording medium when a reproduction is requested, copies an uni-path stream section read from the recording medium so that the number of total same stream sections is equal to a target number which is determined based on the maximum number, assigns each stream section to a virtual channel to form multi-channel streams, and transmits the multi-channel streams to an outer device through a digital interface. Through this data stream transmitting method, it is possible to transmit an angle- or story-based stream segment a viewer wants to view among multi-path stream so that the stream of the selected angle or story may be presented seamlessly at the borders between neighboring stream sections by very simple algorithm.

Abstract: A method and apparatus assists communication between a writer of a shared file and the reader of the shared file without requiring the use of a shared file. When the writer fills a buffer with information and provides a write commend to write the buffer to a shared file, the buffer is not written to a file. Instead, the pointer to the buffer is passed to the reader, and the writer may be suspended until the reader indicates it has read the file. Alternately, two buffers may be used, with the contents of the buffer used by the writer copied to a second buffer, allowing the writer to reuse the first buffer before the reader has completed reading the contents of the second buffer.

Abstract: A device, system and methods of data management are disclosed, which facilitate the implementation of improved mirroring, back-up, volume remapping, extent relocation, prefetching, caching, data reformatting, statistic gathering, and data translation, among others. A new, intelligent I/O stream splitter is disclosed that may intercept and alter an I/O stream received by the splitter from a communications link. For example, in the case of mirroring, the intelligent splitter may intercept write commands and associated data from a mainframe that target a specific storage location on a specific control unit. The splitter may then transmit the intercepted I/O stream to the targeted control unit and storage location over one link and in parallel transmit on another link an altered version of the intercepted I/O stream to another control unit, which is responsible for holding a mirrored version of the data.

Abstract: A method for more efficient buffer control of the configuration of hardware devices. In representative embodiments of the method described in the present patent document, (1) a given configuration is permitted to span exclusive access to the hardware by other processes and (2) different configurations may share the same data buffer. Current configuration of the hardware device is maintained by always placing the current configuration at the beginning of the data buffer. This first entry, comprising the current configuration, is the header of the buffer's data. All subsequent instructions will follow this header, as will any subsequent modifications to the devices' configuration. Since instructions contained in the buffer are to be executed sequentially, the device will always be set to the correct configuration, even when exclusive access between different data sets of the buffer is lost.

Abstract: A mechanism that includes an apparatus and method for ensuring that all transactions within any flow control class completes is herein provided. The mechanism includes a plunge transaction that is inserted in each pending transaction queue and which is transmitted to a particular destination device. All prior transactions in a flow control class are deemed to be complete when the destination device receives the plunge transactions in the flow control class.

Abstract: A method and system for demultiplexing packets of a message is provided. The demultiplexing system receives packets of a message, identifies a sequence of message handlers for processing the message, identifies state information associated with the message for each message handler, and invokes the message handlers passing the message and the associated state information. The system identifies the message handlers based on the initial data type of the message and a target data type. The identified message handlers effect the conversion of the data to the target data type through various intermediate data types.

Abstract: A method and apparatus is presented providing high-performance lossless data compression implemented in hardware for improving network communications. A compression module useful in a switching platform is also presented capable of compressing data stored in buffer memory. Instructions for a compression task are assigned to the compression module by a microprocessor writing a control block to a queue in stored local memory. The control block informs the compression module of the size and location of the unprocessed data, as well as a location in the buffer memory for storing the processed data and the maximum allowed size for the compressed data. Using this technique, the microprocessor can limit the compression of data to those data streams allowing compression, to those segments that are susceptible to compression, and to those segments that are large enough to show a transmission speed improvement via compression.

Abstract: The object of the present invention is, while employing only a simple structure, to engage in rapid communication with an external device and to display results of the communication. According to the present invention, disclosed is an electronic apparatus, which comprises conversion means for converting a target image into image signals, supply means for supplying, to a monitor, signals in consonance with the image signal obtained by the conversion means in order to reproduce the target image, communication means for using a DS-Link method to perform bidirectional communication with an external device handling the image signal for the target image and control means for displaying on the monitor information concerning the external device that is obtained by the communication means.

Abstract: A method and apparatus are provided for interactively guiding a user through a scanner installation procedure. When a scanner installation program is launched, the scanner installation program causes various screens having various options to be displayed to a user. The screens provide the user with information that guides the user step-by-step through the scanner installation procedure. The scanner installation program automatically detects which I/O ports of the user's computer are available for connection to the scanner and displays a message to the user indicating which I/O port(s) is available for connection to the scanner. The scanner installation program then provides the user with the option of seeing a visual demonstration of steps that need to be taken by the user in connecting the scanner to the available I/O port of the computer.

Abstract: In an example embodiment, a data transfer method adaptively transfers data from a host device to a target device across a channel-based interconnect. The method includes determining whether or not the size of the data to be transferred is greater than the maximum payload of a cell for the channel-based interconnect. If the size of the data to be transferred is not greater than the maximum payload, then a single cell is transferred from the host device to the target device which includes all of the data. If the size of the data to be transferred is greater than the maximum payload, then a request message is transferred from the host device to the target device. The request message includes a portion of said data to be transferred and control information indicating that not all of the data to be transferred is included in the request message.

Abstract: A keyboard system includes keyboard having an internal circuit therein, at least one I/O device, and a transceiver module. The transceiver module on the main body of the keyboard receives signals from I/O devices and transmits audio signals from at least one external device connected to the keyboard system. The keyboard further includes a plurality of pointers indicative of which I/O device is connected to the keyboard.

Abstract: Method of passing inbound messages to an I/O processor's local memory. A message is received in a messaging unit within the I/O processor. The messaging unit is read to fetch the message. A free local message frame address is retrieved from the messaging unit. A direct memory access unit coupled to the messaging unit is set up. The message is then copied into the I/O processor's local memory.

Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

Abstract: A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry 300, multi-channel selection circuitry 310, and companding circuitry 320. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry 320 performs optional expansion or compression of received or transmitted data using &mgr;-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.

Abstract: Data fed in through a PIO or UART is first converted into IrDA-protocol-conforming data by a CPU executing a software program stored in a ROM, and the resulting data is then fed by way of a bus to a modulation circuit so as to be modulated. A signal fed in to a demodulation circuit is first demodulated to restore IrDA-protocol-conforming data, and the demodulated data is then converted back into its original data by the CPU executing the software program stored in the ROM. The restored data is fed by way of the bus to the PIO or UART.

Abstract: A system for scanning data into a host from a peripheral location. A peripheral, such as a multifunction peripheral having printer and scanner functionality, is coupled to a host, such as a personal computer. The system includes a user interface at the peripheral that can be utilized in selecting a desired target, such as an application or file, at the host. The peripheral user interface also can be used to select a networked site, such as a networked file. Thus, a user can scan desired data at the peripheral to a remote application or file without providing input at the user interface of the host.

Abstract: A circuit board, for use with a high speed backplane, includes transmitter and receiver with circuitry for correcting for multipath signal errors. A training sequence that is often a pseudo-random signal is transmitted by the transmitter on a first circuit board to a receiver located on a second circuit board. The receiver on the second circuit board includes an analog-to-digital signal converter, an equalizer, and a binary digital-to-analog reconverter for receiving the training sequence. The equalizer preferably comprises a series of connected registers having taps in between, a plurality of individual weighting means attached to each of the taps, and a summing means connected to the weighting means. A training sequence is transmitted from the first circuit board to the receiver on the second circuit board, enabling the receiver to adaptively determine a set of weighting means coefficients for correcting the multipath errors in subsequent signals.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A digitizer for use in a measurement system. The digitizer acquires data from an external source, and includes a static random access memory (SRAM) which stores a scan list comprising entries specifying digitizer operations such as switch time, settle time, measure time, looping, and mathematical operation specifications such as scaling, adding, and averaging specifications. The looping specification may include instructions to repeatedly execute one or more entries in the scan list. The digitizer includes a programmable logic element (e.g. an FPGA) coupled to the SRAM which accesses and executes the scan list to acquire analog signals from the source. The digitizer may include an analog-to-digital converter to convert the analog signals to digital signals, as well as a multiplexer to read the analog signals from multiple channels, a signal conditioner to modify the analog signals from the multiplexer, and an amplifier to amplify the analog signals from the signal conditioner.

Abstract: A software system implemented in a medical device includes an allocation scheme for allocating storage of cardiac data. The software system enables storing cardiac data in a plurality of addressable locations. When all available locations within the plurality of addressable locations are full, a scratch location is assigned based on predetermined episode type priorities and characteristics. The priorities represent a graduated order based on the clinical significance of the cardiac episode under consideration. The characteristics provide classifications based on fastest rate, longest duration and last to occur care for each of the priorities.

Abstract: An emulation system functions to translate instructions comprising a target application of a target system into corresponding instructions native to a host system and executes the instructions on the host system. During execution, the emulation system encounters target disk read/write operations. As the memory architectures of the host and target computer systems differ, the data in host memory is conformed to a target memory format when data in keyboard memory buffer is processed. Also, the host and target disk controllers cause storage of data on diskettes in differing byte orders. However, the emulation system performs disk/read write operations without byte-reversal prior to disk-write or subsequent to disk read operations. Thus, the host does not produce storage media having data conforming to that of target storage media.

Abstract: An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Abstract: Digital pixel data is transferred from a computer system to video display hardware in a forward direction. However, there are many reasons for digital pixel data to be transferred in both directions along a cable connecting a computer and a monitor. This invention describes a method of sending digital data from a monitor back to the computer in a reverse direction. In transmission of digital pixel data in a forward direction, there are horizontal and vertical blanking periods during which special characters are transmitted in order to resynchronize the digital pixel data to a clock signal. In such a system the transmission of these special characters only requires a portion of the blanking periods. During the remainder to the blanking period, some of or all of the data paths can be used in order to transmit digital data in a reverse direction. Where all data paths are used, the beginning and end of the usable portion of the blanking periods may last for a fixed number of clock cycles.

Abstract: The present invention provides an electronic switching device for a universal serial bus (USB) interface, which can connect several different electronic devices each having a universal serial bus (USB) interface when needed. By manually enabling a switch of the electronic switching device for a universal serial bus (USB) interface, a trigger signal generated from a trigger signal generator will be outputted to a control signal generator to generate a control signal for connecting related electronic devices. A delay signal generator can be added to avoid the intermediate devices being operated unintentionally.

Abstract: A serial interface or port is configured so that: a Read command and a Write command can be performed substantially simultaneously; a shortened Read command, followed by another Read command, can be performed in reduced time, due to the shortening of the first Read command; and a continuous stream of Read commands can be performed consecutively with no time delay By performing Read and Write commands simultaneously on associated channels at a serial interface, the time required for such performance is reduced by as much as 50 percent.

Abstract: Computer system performance may be significantly enhanced by optimizing data throughput during input/output (I/O) operations. In turn, data throughput, during an I/O operation, may be optimized by adaptively modifying the I/O strategy at runtime, and/or continuously throughout the I/O operation, regardless of the specific hardware configuration associated with the I/O devices involved with the I/O operation, as well as additional factors that might otherwise impact the efficiency of the I/O operation.

Abstract: The invention provides apparatus for the transfer of data/command between a master controller and one or more client controllers. The apparatus in accordance with the invention includes a bi-directional data bus for conveying plural bits of data or command between a master controller and one or more client controllers; direction signal controlling the direction in which data or command bits are conveyed on the data bus as between the master controller and a connected one of the one or more client controllers; a pair of ready signals including a transmit ready signal asserted by a source of data or command bits placed on the data bus and including a receive ready signal asserted by a destination for the data or command bits placed on the data bus; and a clock signal for indicating the presence of valid data or command bits on the data bus on a leading or trailing edge thereof. Preferably, a command/data signal is also provided to indicate the type of information placed on the data bus by the source.

Abstract: An I/O expansion device for additional inputs and outputs, and an apparatus and a method for applying this device. The device includes a connector (CN1) for the connection with a parallel port, a plurality of 4-bit input/output ports, and an I/O expansion circuit (100) having a 4-bit data bus for data transfer between a plurality of 4-bit input/output ports and the connector. The I/O expansion circuit (100) includes a control input CTRL including a strobe PROG for controlling fetch of the command for selecting the input/output ports and an operation mode, a data input DIN that recieves a command in accordance with the state transition of the strobe PROG and data to be transferred to the input/output port selected by the command and a data output DOUT for giving the state of the selected port through the connector.

Abstract: Methods and system for a message resource pool with asynchronous and synchronous modes of operation. One or more buffers, descriptors, and message elements are allocated for a user. Each element is associated with one descriptor and at least one buffer. The allocation is performed by the message resource pool. The buffers and the descriptors are registered with a unit management function by the message resource pool. Control of an element and associated descriptor and at least one buffer is passed from the message resource pool to the user upon request by the user. The control of the element and associated descriptor and at least one buffer is returned from the user to the message resource pool once use of the element and associated descriptor and at least one buffer by the user has completed.

Abstract: An information processing apparatus having a simplified switching function of a user is disclosed that can reduce the processing burden upon a CPU and eliminate an action that is not intended by its user. If an application, which implements a function of a device or the like that is not supported as a standard device by an OS and is started up for each user, has been started up by a first user who is not active at present, that is, a user in a logon state whose desktop has been switched to that of a second user, then part of the processing of the application is temporarily stopped. Then, if it is detected that the first user is rendered operative, that is, when the desktop is switched to that of the first user, the processing of the application of the first user is re-started.

Abstract: Access control to protected resources in a multiprocessor system is implemented without additional use of the processor bus. A bridge interconnects each processor with shared resources. The bridge has a semaphore corresponding to each protected resource indicating if the corresponding resource is available. The bridge halts a processor requesting access to any resource having a corresponding semaphore indicating the requested resource is not available.

Abstract: A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. The transaction interface uses information derived from the data packets received to form message control blocks, particular for each individual task, and places the control blocks into the proper task queue. The transaction interface forms a dispatcher message control block and places it into the scheduler/dispatcher queue to initiate the task. If there are no other message control blocks in the queue particular for the called task, the called task is immediately started. Otherwise, the message control block waits in the queue to eventually be operated on.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: In an example embodiment, a method of delivering a command from an initiator device also transfers data identified by the command to a target device. The data is transferred between the initiator device and the target device according to a selected maximum payload size. The method includes determining whether or not the size of the data associated with the command is greater than the selected maximum payload size. If the size of the data associated with the command is not greater than the selected maximum payload size, then a block is transferred to or from the target device which includes the command and all of the data associated with the command.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.